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| november 2007 rev 1 1/1176 RM0004 reference manual programmer?s reference manual for book e processors introduction this reference manual gives an overview of book e, a version of the powerpc architecture intended for embedded pr ocessors. to ensure applicat ion level compatibility with the powerpc architecture developed by apple, ibm, and freescale, book e incorporates the user level resources defined in the user instruction set architecture (uisa), book i, of the aim architectural definition. www.st.com
RM0004 contents 2/1176 contents about this book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 suggested reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 terminology conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 part i: book e and book e impl ementation standards . . . . . . . . . . . . . . . . . . . . . 32 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.1 overview book e and the book e implementation standards (eis) . . . . . 33 1.1.1 auxiliary processing units (apus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.2 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4 interrupts and exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4.1 exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4.2 interrupt classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4.3 interrupt categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4.4 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5 memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.1 address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5.2 mmu assist registers (mas1?mas7) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.5.3 process id registers (pid0?pid2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.4 tlb coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.5 atomic update memory references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.6 memory access ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.5.7 cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.5.8 programmable page characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 contents RM0004 3/1176 1.6 performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.1 global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.2 performance monitor counter registers . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.3 local control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.7 legacy support of powerpc architecture . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.7.1 instruction set compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.7.2 memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.7.3 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.7.4 memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.7.5 requirements for system reset generation . . . . . . . . . . . . . . . . . . . . . . 45 1.7.6 little-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2 register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.2 register model for 32-bit book e implemen tations . . . . . . . . . . . . . . . . . 47 2.2.1 special-purpose registers (sprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3 registers for integer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3.1 general purpose registers (gprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3.2 integer exception register (xer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4 registers for floating-point operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.4.1 floating-point registers (fprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.4.2 floating-point status and control register (fpscr) . . . . . . . . . . . . . . . . 58 2.5 registers for branch operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.5.1 condition register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.5.2 link register (lr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.5.3 count register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.6 processor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.6.1 machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.7 hardware implementation-dependent registers . . . . . . . . . . . . . . . . . . . . 71 2.7.1 hardware implementation dependent register 0 (hid0) . . . . . . . . . . . . 71 2.7.2 hardware implementation dependent register 1 (hid1) . . . . . . . . . . . . 74 2.7.3 processor id register (pir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.7.4 processor version register (pvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.7.5 system version register (svr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.8 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.8.1 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 RM0004 contents 4/1176 2.8.2 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.8.3 time base (tbu and tbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.8.4 decrementer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.8.5 decrementer auto-reload register (decar) . . . . . . . . . . . . . . . . . . . . . 80 2.9 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.9.1 interrupt registers defined by book e . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.10 software use sprs (sprg0?sprg7 and usprg0) . . . . . . . . . . . . . . . . 89 2.11 l1 cache registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.11.1 l1 cache control and status register 0 (l1csr0) . . . . . . . . . . . . . . . . . 90 2.11.2 l1 cache control and status register 1 (l1csr1) . . . . . . . . . . . . . . . . . 92 2.11.3 l1 cache configuration register 0 (l1cfg0) . . . . . . . . . . . . . . . . . . . . . 94 2.11.4 l1 cache configuration register 1 (l1cfg1) . . . . . . . . . . . . . . . . . . . . . 95 2.11.5 l1 flush and invalidate control register 0 (l1finv0) . . . . . . . . . . . . . . . 96 2.12 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.12.1 process id registers (pid0?pidn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.12.2 mmu control and status register 0 (mmucsr0) . . . . . . . . . . . . . . . . . . 98 2.12.3 mmu configuration register (mmucfg) . . . . . . . . . . . . . . . . . . . . . . . . 99 2.12.4 tlb configuration registers (tlb n cfg) . . . . . . . . . . . . . . . . . . . . . . . 100 2.12.5 mmu assist registers (mas0?mas7) . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.13 debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.13.1 debug control registers (dbcr0?dbcr3) . . . . . . . . . . . . . . . . . . . . . 108 2.13.2 debug status register (dbsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.13.3 instruction address compare registers (iac1?iac4) . . . . . . . . . . . . . . 117 2.13.4 data address compare registers (dac1?dac2) . . . . . . . . . . . . . . . . . 118 2.13.5 data value compare registers (dvc1 and dvc2) . . . . . . . . . . . . . . . . 118 2.14 spe and spfp apu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.14.1 signal processing, embedded floating-point status, control register (spefscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.14.2 accumulator (acc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.15 alternate time base registers (atbl and atbu) . . . . . . . . . . . . . . . . . . 123 2.16 performance monitor registers (pmrs) . . . . . . . . . . . . . . . . . . . . . . . . . 124 2.16.1 global control register 0 (pmgc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 2.16.2 user global control register 0 (upmgc0) . . . . . . . . . . . . . . . . . . . . . . 126 2.16.3 local control a registers (pmlca0?pmlca3) . . . . . . . . . . . . . . . . . . . 127 2.16.4 user local control a registers (upmlca0?upmlca3) . . . . . . . . . . . . 128 2.16.5 local control b registers (pmlcb0?pmlcb3) . . . . . . . . . . . . . . . . . . . 128 contents RM0004 5/1176 2.16.6 user local control b registers (upmlcb0?upmlcb3) . . . . . . . . . . . . 129 2.16.7 performance monitor counter registers (pmc0?pmc3) . . . . . . . . . . . 129 2.16.8 user performance monitor counter registers (upmc0?upmc3) . . . . . 129 2.17 device control registers (dcrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.18 book e spr model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.18.1 invalid spr references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.18.2 synchronization requirements for sprs . . . . . . . . . . . . . . . . . . . . . . . 130 2.18.3 reserved sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 2.18.4 allocated sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3 instruction model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.1 operand conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.1.1 data organization in memory and data transfers . . . . . . . . . . . . . . . . . 133 3.1.2 alignment and misaligned accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.2 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 3.2.1 classes of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.2.2 instruction forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.2.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.3 instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.3.1 book e user-level instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.3.2 supervisor level instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 3.3.3 recommended simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . 185 3.3.4 book e instructions with implementation-specific features . . . . . . . . . 185 3.3.5 eis instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 3.3.6 context synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.4 instruction fetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.5 memory synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.6 eis-specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.6.1 spe and embedded fl oating-point apus . . . . . . . . . . . . . . . . . . . . . . . 186 3.6.2 integer select ( isel ) apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.6.3 performance monitor apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.6.4 cache locking apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 3.6.5 machine check apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.6.6 vle extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.7 instruction listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 RM0004 contents 6/1176 4 interrupts and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 4.2 eis interrupt definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 4.2.1 recoverability from interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 4.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 4.4 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 4.5 interrupt classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 4.5.1 requirements for system reset generation . . . . . . . . . . . . . . . . . . . . . 254 4.6 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 4.7 interrupt definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 4.7.1 critical input interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 4.7.2 machine check interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 4.7.3 data storage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.7.4 instruction storage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 4.7.5 external input interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.7.6 alignment interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.7.7 program interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 4.7.8 floating-point unavailable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 4.7.9 system call interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 4.7.10 auxiliary processor unavailable interrupt . . . . . . . . . . . . . . . . . . . . . . . 267 4.7.11 decrementer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 4.7.12 fixed-interval timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 4.7.13 watchdog timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 4.7.14 data tlb error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 4.7.15 instruction tlb error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 4.7.16 debug interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 4.7.17 eis-defined interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 4.8 performance monitor interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 4.9 partially executed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 4.10 interrupt ordering and masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 4.10.1 guidelines for system software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 4.10.2 interrupt order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 4.11 exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 5 storage architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 contents RM0004 7/1176 5.2 memory and cache coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 5.2.1 memory/cache access attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 5.2.2 shared memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 5.3 cache model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 5.3.1 cache programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 5.3.2 primary (l1) cache model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.4 storage model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.4.1 storage programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.4.2 the storage architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 5.4.3 virtual address (va) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.4.4 address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.4.5 process id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 5.4.6 address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 5.4.7 address translation and the st eis . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 5.4.8 permission attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 5.4.9 translation lookaside buffer (tlb) arrays . . . . . . . . . . . . . . . . . . . . . . 317 5.4.10 tlb management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 tlb configuration information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 tlb entries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 reading and writing tlb entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 invalidating tlb entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 5.4.11 mas registers and exception handling . . . . . . . . . . . . . . . . . . . . . . . . 325 6 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 6.1 notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 6.2 instruction fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 6.3 description of instruction operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 6.3.1 spe apu saturation and bi t-reverse models . . . . . . . . . . . . . . . . . . . . 336 6.3.2 embedded floating-point conversion models . . . . . . . . . . . . . . . . . . . . 337 6.3.3 integer saturation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 6.3.4 embedded floating-point results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 6.4 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 part ii: eis-defined extensions to the book e architecture. . . . . . . . . . . . . . . . . 822 7 auxiliary processing units (apus) . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 RM0004 contents 8/1176 7.1 integer select apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 7.1.1 integer select apu programming model . . . . . . . . . . . . . . . . . . . . . . . 823 7.1.2 using isel to improve conditional branch performance . . . . . . . . . . . . 824 7.2 performance monitor apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 7.2.1 performance monitor apu programming model . . . . . . . . . . . . . . . . . 824 7.3 signal processing engine apu (spe apu) . . . . . . . . . . . . . . . . . . . . . . 826 7.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 7.3.2 nomenclature and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 7.3.3 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 7.3.4 instruction definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 7.4 embedded vector and scalar single-precision floating-point apus (spfp apus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 7.4.1 nomenclature and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 7.4.2 embedded floating-point apus programming model . . . . . . . . . . . . . . 832 7.4.3 embedded floating-point apu operations . . . . . . . . . . . . . . . . . . . . . . 839 7.4.4 implementation options summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 7.5 machine check apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 7.5.1 machine check apu programming model . . . . . . . . . . . . . . . . . . . . . . 843 7.6 debug apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 7.6.1 debug apu programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 7.6.2 debug apu register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 7.6.3 debug apu instruction model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 7.7 alternate time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 7.7.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 8 storage-related apus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 8.1 cache line locking apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 8.1.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 8.2 direct cache flush apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 8.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 8.2.2 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 8.3 cache way partitioning apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 8.3.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 8.3.2 interaction with the cache locking apu . . . . . . . . . . . . . . . . . . . . . . . . 851 9 vle introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 contents RM0004 9/1176 9.1 compatibility with powerpc book e . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 9.2 instruction mnemonics and operands . . . . . . . . . . . . . . . . . . . . . . . . . . 853 10 vle storage addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 10.1 data memory addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 10.2 instruction memory addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . 854 11 vle compatibility with the eis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 11.2 vle extension processor and storage control extensions . . . . . . . . . . . 856 11.2.1 eis instruction extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 11.2.2 book e instruction extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 11.2.3 eis mmu extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 11.2.4 eis debug apu extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 12 vle instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 12.1 processor control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 12.1.1 system linkage instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 12.1.2 processor control register manipulation instructions . . . . . . . . . . . . . . 860 12.1.3 instruction synchronization instruction . . . . . . . . . . . . . . . . . . . . . . . . . 861 12.2 branch operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 12.2.1 registers for branch operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 12.2.2 branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 12.3 condition register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 12.4 integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 12.4.1 integer load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 12.4.2 integer store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 12.4.3 integer arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 12.4.4 integer logical and move instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 870 12.4.5 integer compare and bit test instructions . . . . . . . . . . . . . . . . . . . . . . . 872 12.4.6 integer select instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 12.4.7 integer trap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 12.4.8 integer rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 12.5 storage control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 12.5.1 storage synchronization instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 876 12.5.2 cache management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 RM0004 contents 10/1176 12.5.3 tlb management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 12.5.4 instruction alignment and byte ordering . . . . . . . . . . . . . . . . . . . . . . . . 877 12.6 instruction listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 13 vle instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 13.1 book e? and eis-defined instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 891 13.2 immediate field and displacement field enc odings . . . . . . . . . . . . . . . . . 895 14 vle instruction index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 14.1 instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 14.2 instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . 984 14.3 instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 14.4 instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . 1014 appendix a instruction set listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 a.1 instructions sorted by mnemonic ( decimal and hexadecimal). . . . . . . . 1028 a.2 instructions sorted by primary opc odes (decimal and hexadecimal) . . 1048 a.3 instructions sorted by mnemonic (binary) . . . . . . . . . . . . . . . . . . . . . . . 1063 a.4 instructions sorted by opcode (binary) . . . . . . . . . . . . . . . . . . . . . . . . . 1083 a.5 instruction set legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097 appendix b simplified mnemonics for powerpc instructions. . . . . . . . . . . . 1110 b.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 b.2 subtract simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 b.2.1 subtract immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 b.2.2 subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 b.3 rotate and shift simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . 1111 b.3.1 operations on words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 b.4 branch instruction simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . 1112 b.4.1 key facts about simplified branch mnemonics . . . . . . . . . . . . . . . . . . 1114 b.4.2 eliminating the bo operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114 b.4.3 incorporating the bo branch prediction . . . . . . . . . . . . . . . . . . . . . . . 1116 b.4.4 the bi operand?cr bit and field representations . . . . . . . . . . . . . . . 1117 b.4.5 simplified mnemonics that incorporate the bo operand . . . . . . . . . . 1120 b.4.6 simplified mnemonics that incorporate cr conditions (eliminates bo and replaces bi with cr s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123 contents RM0004 11/1176 b.5 compare word simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . 1128 b.6 condition register logical simplified mnem onics . . . . . . . . . . . . . . . . . . 1128 b.7 trap instructions simplified mnemonics. . . . . . . . . . . . . . . . . . . . . . . . . 1129 b.8 simplified mnemonics for accessing sprs . . . . . . . . . . . . . . . . . . . . . . 1131 b.9 recommended simplified mnemonics. . . . . . . . . . . . . . . . . . . . . . . . . . 1131 b.9.1 no-op ( nop ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 b.9.2 load immediate ( li ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 b.9.3 load address ( la ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 b.9.4 move register ( mr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 b.9.5 complement register ( not ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 b.9.6 move to condition register ( mtcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 b.10 eis-specific simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 b.10.1 integer select ( isel ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 b.10.2 spe mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 b.11 comprehensive list of simplified mnemonics . . . . . . . . . . . . . . . . . . . . 1133 appendix c programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143 c.1 synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143 c.1.1 synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144 c.1.2 lock acquisition and release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 c.1.3 list insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 c.1.4 synchronization notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 c.2 multiple-precision shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148 c.3 floating point conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 c.3.1 conversion from floating-point number to signed integer word . . . . . 1150 c.3.2 conversion from floating-point number to unsigned integer word . . . 1151 c.4 floating point selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151 c.4.1 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 appendix d guidelines for 32- bit book e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154 d.1 registers on 32-bit book e implementations. . . . . . . . . . . . . . . . . . . . . 1154 d.2 addressing on 32-bit book e implementations . . . . . . . . . . . . . . . . . . . 1154 d.3 tlb fields on 32-bit book e implementations . . . . . . . . . . . . . . . . . . . . 1154 d.4 32-bit book e software guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155 d.4.1 32-bit instruction selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155 d.4.2 32-bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155 RM0004 contents 12/1176 appendix e embedded floating- point results . . . . . . . . . . . . . . . . . . . . . . . . . 1156 e.1 notation conventions and general rules . . . . . . . . . . . . . . . . . . . . . . . . 1156 e.2 add, subtract, multiply, and divide results . . . . . . . . . . . . . . . . . . . . . . . 1157 e.3 double- to single-precision conversion . . . . . . . . . . . . . . . . . . . . . . . . . 1160 e.4 single- to double-precision conversion . . . . . . . . . . . . . . . . . . . . . . . . . 1161 e.5 conversion to unsigned. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 e.6 conversion to signed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 e.7 conversion from unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 e.8 conversion from signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 e.9 *abs, *nabs, and *neg operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 15 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167 i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7 k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168 l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168 n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169 o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169 p. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 r. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175 list of tables RM0004 13/1176 list of tables table 1. conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 2. acronyms and abbreviated terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 table 3. terminology conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4. instruction field conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5. interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6. interrupt vector registers and exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 7. book e special purpose registers (by spr abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 8. eis?defined sprs (by spr abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 9. xer field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 10. fpscr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 11. floating-point result flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 12. bi operand settings for cr fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 13. cr0 bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 14. cr setting for floating-point instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 15. cr setting for compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 16. cr0 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 17. condition register setting for compare instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 18. branch to link register instruction comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 19. branch to count register instruction comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 20. msr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 21. floating-point exception bits?msr[fe0,fe1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 22. hid0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 23. pvr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 24. tcr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 25. tsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 26. ivor assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 27. exception syndrome register (esr) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 28. mcsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 29. l1csr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 30. l1csr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 31. l1cfg0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 32. l1cfg1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 33. l1finv0 fields?l1 direct cache flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 table 34. mmucsr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 35. mmucfg field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 36. tlbncfg field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 37. mas0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 38. mas1 field descriptions?descriptor context and configuration control . . . . . . . . . . . . . . 102 table 39. mas2 field descriptions?epn and page attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 40. mas3 field descriptions?rpn and access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 41. mas4 field descriptions?hardware replacement assist configuration . . . . . . . . . . . . . . . 105 table 42. mas5 field descriptions?extended search pids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 43. mas 6 field descriptions?search pids and search as. . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 44. mas 7 field descriptions?high order rpn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 45. dbcr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 46. dbcr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 47. dbcr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 48. dbsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 RM0004 list of tables 14/1176 table 49. spefscr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 50. atbl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 51. atbu field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 52. performance monitor registers?supervisor level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 53. performance monitor registers?user level (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 54. pmgc0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 55. pmlca0?pmlca3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 56. pmlcb0 ?pmlcb3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 57. pmc0?pmc3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 29 table 58. system response to an invalid spr reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 59. synchronization requirements for sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 60. allocated sprs defined by the eis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1 table 61. address characteristics of aligned operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 62. allocated instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 63. preserved instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 64. synchronization requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 65. integer arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 66. integer 32-bit compare instructions (l = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 67. integer logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 68. integer rotate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 69. integer shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 70. floating-point load instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 71. floating-point store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 72. floating-point move instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 73. floating-point elementary arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 74. floating-point multiply-add instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 54 table 75. floating-point rounding and conversion instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 76. cr field settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 77. floating-point compare and select instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 78. floating-point status and control register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 79. integer load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 80. integer store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 81. integer load and store with byte-reverse instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 82. integer load and store multiple instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 83. integer load and store string instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 61 table 84. floating-point load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 85. floating-point store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 86. store floating-point single behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 87. store floating-point double behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 88. bo bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 89. bo operand encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 90. branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 91. condition register logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 92. trap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 93. system linkage instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 94. move to/from condition register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 95. move to/from special-purpose register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 96. book e special-purpose registers (by spr abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 97. implementation-specific sprs (by spr abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 98. memory synchronization instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 table 99. user-level cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 100. system linkage instructions?supervisor-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 list of tables RM0004 15/1176 table 101. move to/from machine state register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 102. supervisor-level cache management instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 103. tlb management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 104. implementation-specific instructions summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 105. eis-defined instructions (e xcept spe and spfp instructions) . . . . . . . . . . . . . . . . . . . . . 185 table 106. spe apu vector multiply instru ction mnemonic structure . . . . . . . . . . . . . . . . . . . . . . . . 188 table 107. mnemonic extensions for multiply-accumulate instructions . . . . . . . . . . . . . . . . . . . . . . . 189 table 108. spe apu vector instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 109. vector and scalar floating-point apu instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 110. integer select apu instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 111. performance monitor apu instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 112. performance monitor registers?supervisor level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 113. performance monitor registers?user level (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 114. cache locking apu instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 115. machine check apu instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 116. system linkage instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 117. system register manipulation instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 118. instruction synchronization instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 119. vle extension bo32 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 03 table 120. vle extension bo16 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 04 table 121. branch instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 122. condition register instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 123. basic integer load instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 124. integer load byte-reverse instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 125. integer load multiple instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 126. integer load and reserve instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 127. basic integer store instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 128. integer store byte-reverse instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 129. integer store multiple instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 07 table 130. integer store conditional instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 table 131. integer arithmetic instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 132. integer logical instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 133. cr settings for compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 134. cr settings for integer bit test instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 135. integer compare and bit test instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 136. integer select instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 137. integer trap conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 138. integer trap instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 139. integer rotate instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 140. integer rotate with mask instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 141. integer shift instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 142. storage synchronization instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 143. cache management instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 144. tlb management instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 145. instructions listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 146. instructions listed by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 147. list of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 148. interrupt types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 149. interrupt registers defined by the powerpc architecture . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 150. asynchronous and synchronous interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 151. interrupt and exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 table 152. critical input interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 RM0004 list of tables 16/1176 table 153. machine check interrupt settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 154. data storage interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 155. data storage interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 table 156. instruction storage interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 157. instruction storage interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 63 table 158. external input interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 table 159. alignment interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 160. program interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 table 161. msr[fe0,fe1] settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 162. program interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 163. floating-point unavailable interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 table 164. system call interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 table 165. auxiliary processor unavailable interr upt register settings . . . . . . . . . . . . . . . . . . . . . . . . 268 table 166. decrementer interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 68 table 167. fixed-interval timer interrupt register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 69 table 168. watchdog timer interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 table 169. data tlb error interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 table 170. data tlb error interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 table 171. instruction tlb error interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 table 172. instruction tlb error interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 table 173. debug interrupt register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 table 174. spe/embedded fl oating-point apu unavailable interrupt r egister settings . . . . . . . . . . . . 272 table 175. embedded floating-point data interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . 272 table 176. embedded floating-point round interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . 273 table 177. operations to avoid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 table 178. eis asynchronous exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 79 table 179. eis synchronous exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 180. load and store ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 table 181. memory barrier when coherency is required (m = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 table 182. cumulative memory barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 183. storage related msr fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 184. exception syndrome register (esr) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 table 185. page size and epn field comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 table 186. real address generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 table 187. permission control for instruction, data read, and data write accesses . . . . . . . . . . . . . . 315 table 188. permission control and cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 table 189. tlb entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 table 190. fields for ea format of tlbivax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 table 191. mas register update summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 table 192. mas settings for an instruction or data tlb error interrupt. . . . . . . . . . . . . . . . . . . . . . . . 327 table 193. mas settings for permissions violation isi or dsi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 table 194. mmu assist register field updates?eis definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 table 195. notation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 table 196. instruction field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 table 197. rtl notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 table 198. operator precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 199. conversion models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 200. bi operand settings for cr fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 table 201. bi operand settings for cr fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 table 202. bi operand settings for cr fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 table 203. data samples and sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 table 204. operations with special values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 list of tables RM0004 17/1176 table 205. operations with special values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 table 206. operations with special values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 table 207. effect of sprn[5] and msr[pr]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 table 208. recoding with isel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 table 209. performance monitor registers?supervisor level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 table 210. performance monitor registers?user level (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . 825 table 211. performance monitor apu instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6 table 212. mnemonic extensions for multiply accumulate instructions . . . . . . . . . . . . . . . . . . . . . . . 830 table 213. embedded vector floating-point instruction opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 table 214. embedded scalar single-precision floating-point instruction opcodes . . . . . . . . . . . . . . . 834 table 215. embedded scalar double-precision floating-point instruction opcodes . . . . . . . . . . . . . . . 834 table 216. eis-defined dbsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 45 table 217. dbcr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 table 218. data storage addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 table 219. instruction storage addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4 table 220. tlb entry 0 reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 table 221. mas2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 table 222. mas4 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 table 223. system linkage instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 table 224. system register manipulation instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 table 225. instruction synchronization instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 table 226. cr0 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 table 227. condition register setting for compare instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 table 228. branch to link register instruction comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 table 229. branch to count register instruction comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 table 230. vle extension bo32 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 64 table 231. vle extension bo16 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 65 table 232. branch instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 table 233. condition register instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 table 234. basic integer load instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 table 235. integer load byte-reverse instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 table 236. integer load multiple instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 table 237. integer load and reserve instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 table 238. basic integer store instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 table 239. integer store byte-reverse instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 table 240. integer store multiple instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 68 table 241. integer store conditional instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8 table 242. integer arithmetic instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 table 243. integer logical instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 table 244. cr settings for compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 table 245. cr settings for integer bit test instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 table 246. integer compare and bit test instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 table 247. integer select instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 table 248. integer trap conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 table 249. integer trap instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 table 250. integer rotate instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875 table 251. integer rotate with mask instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875 table 252. integer shift instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875 table 253. storage synchronization instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 table 254. cache management instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 table 255. tlb management instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 table 256. instructions listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 RM0004 list of tables 18/1176 table 257. instructions listed by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 table 258. book e? and eis-defined instructions listed by mnemonic . . . . . . . . . . . . . . . . . . . . . . . 891 table 259. immediate field and displacement field encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 table 260. notation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 table 261. instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 table 262. 32-bit instruction encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 table 263. 16-bit vle instructions sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 table 264. 32-bit instruction encodings (by mnemonic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 table 265. instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 000 table 266. 32-bit instruction encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 table 267. instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) . . . . . . . . . . . . . . . . . . . . . . . . 1017 table 269. instructions sorted by mnemonic (decimal and hexadecimal) . . . . . . . . . . . . . . . . . . . . 1028 table 270. instructions sorted by primary opcodes (decimal and hexadecimal) . . . . . . . . . . . . . . . 1048 table 271. instructions sorted by mnemonic (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063 table 272. instructions sorted by opcode (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 83 table 273. powerpc instruction set legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 table 274. powerpc instruction set legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 table 275. subtract immediate simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 table 276. subtract simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 table 277. word rotate and shift simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112 table 278. branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112 table 279. bo bit encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115 table 280. bo operand encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115 table 281. cr0 and cr1 fields as updated by integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . 1118 table 282. bi operand settings for cr fields for branch comparisons . . . . . . . . . . . . . . . . . . . . . . . 1119 table 283. cr field identification symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 table 284. branch simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 table 285. branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121 table 286. simplified mnemonics for bc and bca without lr update . . . . . . . . . . . . . . . . . . . . . . . 1121 table 287. simplified mnemonics for bclr and bcctr without lr update . . . . . . . . . . . . . . . . . . . . . 1122 table 288. simplified mnemonics for bcl and bcla with lr update . . . . . . . . . . . . . . . . . . . . . . . . . 1122 table 289. simplified mnemonics for bclrl and bcctrl with lr update . . . . . . . . . . . . . . . . . . . . . . 1123 table 290. standard coding for branch conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124 table 291. branch instructions and simplified mnemonics that incorporate cr conditions . . . . . . . 1124 table 292. simplified mnemonics with comparison conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 table 293. simplified mnemonics for bc and bca without comparison conditions or lr update. . . 1126 table 294. simplified mnemonics for bclr and bcctr without comparison conditions or lr update 1126 table 295. simplified mnemonics for bcl and bcla with comparison conditions, lr update . . . . . . 1127 table 296. simplified mnemonics for bclrl and bcctrl with comparison conditions, lr update. . . . 1127 table 297. word compare simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128 table 298. condition register logical simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128 table 299. standard codes for trap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 129 table 300. trap simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130 table 301. to operand bit encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130 table 302. additional simplified mnemonics for accessing sprgs . . . . . . . . . . . . . . . . . . . . . . . . . 1131 table 303. simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 table 304. shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 table 305. comparison to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 table 306. minimum and maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 table 307. simple if-then-else constructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 table 308. notation conventions and general rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156 list of tables RM0004 19/1176 table 309. floating-point results summary?add, sub, mul, div . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157 table 310. floating-point results summary?single convert from double . . . . . . . . . . . . . . . . . . . . . 1160 table 311. floating-point results summary?double convert from single . . . . . . . . . . . . . . . . . . . . . 1161 table 312. floating-point results summary?convert to unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 table 313. floating-point results summary?convert to signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 table 314. floating-point results summary?convert from unsigned . . . . . . . . . . . . . . . . . . . . . . . . 1162 table 315. floating-point results summary?convert from signed . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 table 316. floating-point results summary?*abs, *nabs, *neg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 table 317. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175 RM0004 list of figures 20/1176 list of figures figure 1. eis programming model register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 figure 2. effective-to-real address translation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 3. register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 4. spe and floating point apu gpr usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 5. relationship of timer facilities to the time base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 figure 6. register indirect with immediate index addressing for integer loads/stores . . . . . . . . . . . 158 figure 7. register indirect with index addressing for integer loads/stores. . . . . . . . . . . . . . . . . . . . 158 figure 8. register indirect addressing for integer loads/stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 9. branch relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 10. branch conditional relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 65 figure 11. branch to absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 12. branch conditional to absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 13. branch conditional to link register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 14. branch conditional to count register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 15. integer and fractional operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 16. virtual address space in book e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 figure 17. current address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 figure 18. current pid value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 figure 19. virtual address and tlb-entry comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 figure 20. effective-to-real address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 figure 21. granting of access permission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 figure 22. tlbs accessed through mas registers and tlb instructions. . . . . . . . . . . . . . . . . . . . . . 320 figure 23. instruction description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 figure 24. vector absolute value ( evabs ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 figure 25. vector add immediate word ( evaddiw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 figure 26. vector add signed, modulo, integer to accumulator word ( evaddsmiaaw ) . . . . . . . . . . . 470 figure 27. vector add signed, saturate, integer to accumulator word ( evaddssiaaw ) . . . . . . . . . . . 471 figure 28. vector add unsigned, modulo, integer to accumulator word ( evaddumiaaw ) . . . . . . . . . 472 figure 29. vector add unsigned, saturate, integer to accumulator word ( evaddusiaaw ) . . . . . . . . . 473 figure 30. vector add word ( evaddw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 figure 31. vector and ( evand ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 figure 32. vector and with complement ( evandc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 figure 33. vector compare equal ( evcmpeq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 figure 34. vector compare greater than signed ( evcmpgts ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 figure 35. vector compare greater than unsigned ( evcmpgtu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 figure 36. vector compare less than signed ( evcmplts ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 figure 37. vector compare less than unsigned ( evcmpltu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 figure 38. vector count leading signed bits word ( evcntlsw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 figure 39. vector count leading zeros word ( evcntlzw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 figure 40. vector divide word signed ( evdivws ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 figure 41. vector divide word unsigned ( evdivwu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 figure 42. vector equivalent ( eveqv ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 figure 43. vector extend sign byte ( evextsb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 figure 44. vector extend sign half word ( evextsh ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 figure 45. evldd results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 figure 46. evlddx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 figure 47. evldhx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 figure 48. evldw results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 list of figures RM0004 21/1176 figure 49. evldwx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 figure 50. evlhhesplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 figure 51. evlhhesplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 figure 52. evlhhossplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 figure 53. evlhhossplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 figure 54. evlhhousplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 figure 55. evlhhousplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 figure 56. evlwhe results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 figure 57. evlwhex results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 figure 58. evlwhos results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 figure 59. evlwhosx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 figure 60. evlwhou results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 figure 61. evlwhoux results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 figure 62. evlwhsplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 figure 63. evlwhsplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 figure 64. evlwwsplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 figure 65. evlwwsplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 figure 66. high order element merging ( evmergehi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 figure 67. high order element merging ( evmergehilo ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 figure 68. low order element merging ( evmergelo ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 figure 69. low order element merging ( evmergelohi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 figure 70. evmhegsmfaa (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 figure 71. evmhegsmfan (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 figure 72. evmhegsmiaa (even form). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 figure 73. evmhegsmian (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 figure 74. evmhegumiaa (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 figure 75. evmhegumian (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 figure 76. even multiply of two signed modulo fractional elements (to accumulator) ( evmhesmf ) . 545 figure 77. even form of vector half-word multiply ( evmhesmfaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . 546 figure 78. even form of vector half-word multiply ( evmhesmfanw ) . . . . . . . . . . . . . . . . . . . . . . . . . 547 figure 79. even form for vector multiply (to accumulator) ( evmhesmi ) . . . . . . . . . . . . . . . . . . . . . . 548 figure 80. even form of vector half-word multiply ( evmhesmiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . 549 figure 81. even form of vector half-word multiply ( evmhesmianw ) . . . . . . . . . . . . . . . . . . . . . . . . . 550 figure 82. even multiply of two signed saturate fractional elements (to accumulator) ( evmhessf ) . 552 figure 83. even form of vector half-word multiply ( evmhessfaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 554 figure 84. even form of vector half-word multiply ( evmhessfanw ). . . . . . . . . . . . . . . . . . . . . . . . . . 555 figure 85. even form of vector half-word multiply ( evmhessiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 557 figure 86. even form of vector half-word multiply ( evmhessianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 559 figure 87. vector multiply half words, even, unsigned, modulo, integer (to accumulator) ( evmheumi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 figure 88. even form of vector half-word multiply ( evmheumiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . 561 figure 89. even form of vector half-word multiply ( evmheumianw ) . . . . . . . . . . . . . . . . . . . . . . . . . 562 figure 90. even form of vector half-word multiply ( evmheusiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 564 figure 91. even form of vector half-word multiply ( evmheusianw ). . . . . . . . . . . . . . . . . . . . . . . . . . 566 figure 92. evmhogsmfaa (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 figure 93. evmhogsmfan (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 figure 94. evmhogsmiaa (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 figure 95. evmhogsmian (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 figure 96. evmhogumiaa (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 figure 97. evmhogumian (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 figure 98. vector multiply half words, odd, signed, modulo, fractional (to accumulator) ( evmhosmf ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 RM0004 list of figures 22/1176 figure 99. odd form of vector half-word multiply ( evmhosmfaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 574 figure 100. odd form of vector half-word multiply ( evmhosmfanw ). . . . . . . . . . . . . . . . . . . . . . . . . . 575 figure 101. vector multiply half words, odd, signed, modulo, integer (to accumulator) ( evmhosmi ) . 576 figure 102. odd form of vector half-word multiply ( evmhosmiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 577 figure 103. odd form of vector half-word multiply ( evmhosmianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 578 figure 104. vector multiply half words, odd, signed, saturate, fractional (to accumulator) ( evmhossf ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 figure 105. odd form of vector half-word multiply ( evmhossfaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 582 figure 106. odd form of ve ctor half-word multiply ( evmhossfanw ) . . . . . . . . . . . . . . . . . . . . . . . . . 584 figure 107. odd form of vector half-word multiply ( evmhossiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 586 figure 108. odd form of vector half-word multiply ( evmhossianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 588 figure 109. vector multiply half words, odd, unsigned, modulo, integer (to accumulator) ( evmhoumi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 figure 110. odd form of vector half-word multiply ( evmhoumiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 590 figure 111. odd form of vector half-word multiply ( evmhoumianw ). . . . . . . . . . . . . . . . . . . . . . . . . . 591 figure 112. odd form of vector half-word multiply ( evmhousiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 593 figure 113. odd form of vector half-word multiply ( evmhousianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 595 figure 114. initia lize accumulator ( evmra ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 figure 115. vector multiply word high signed, modulo, fractional (to accumulator) ( evmwhsmf ). . . . 597 figure 116. vector multiply word high signed, modulo, integer (to accumulator) ( evmwhsm ) . . . . . . 598 figure 117. vector multiply word high signed, saturate, fractional (to accumulator) ( evmwhssf ). . . . 600 figure 118. vector multiply word high unsigned, modulo, integer (to accumulator) ( evmwhumi ) . . . 601 figure 119. vector multiply word low signed, modulo, inte ger & accumula te in words evmwlsmiaaw ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 figure 120. vector multiply word low signed, mo dulo, integer and accumulate negative in words ( evmwlsmianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 figure 121. vector multiply word low signed, saturate, integer & accumulate in words ( evmwlssiaaw ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 figure 122. vector multiply word low signed, saturate, integer & accumulate negative in words ( evmwlssianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 figure 123. vector multiply word low unsigned, modulo, integer ( evmwlumi ) . . . . . . . . . . . . . . . . . . 608 figure 124. vector multiply word low unsigne d, modulo, integer & accumulate in words ( evmwlumiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 figure 125. vector multiply word low unsigned, modulo, integer & accumu late negative in words ( evmwlumianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 figure 126. vector multiply word low unsigne d, saturate, integer & accumulate in words ( evmwlusiaaw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 figure 127. vector multiply word low unsigned, saturate, integer & accumulate negative in words ( evmwlusianw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 figure 128. vector multiply word signed, modulo, fractional (to accumulator) ( evmwsmf ). . . . . . . . . 615 figure 129. vector multiply word signed, modulo, fractional & accumulate ( evmwsmfaa ) . . . . . . . . . 616 figure 130. vector multiply word signed, modulo, fractional & accumulate negative ( evmwsmfan ) . 617 figure 131. vector multiply word signed, modulo, integer (to accumulator) ( evmwsmi ). . . . . . . . . . . 618 figure 132. vector multiply word signed, modulo, integer & accumulate ( evmwsmiaa ). . . . . . . . . . . 619 figure 133. vector multiply word signed, modulo, integer & accumulate negative ( evmwsmian ) . . . 620 figure 134. vector multiply word signed, saturate, fractional (to accumulator) ( evmwssf ). . . . . . . . . 621 figure 135. vector multiply word signed, saturate, fractional, & accumulate ( evmwssfaa ) . . . . . . . . 622 figure 136. vector multiply word signed, saturate, fractional & accumulate negative ( evmwssfan ) . 624 figure 137. vector multiply word unsigned, modulo, integer (to accumulator) ( evmwumi ) . . . . . . . . 625 figure 138. vector multiply word unsigned, modulo, integer & accumulate ( evmwumiaa ). . . . . . . . . 626 figure 139. vector multiply word unsigned, modulo, integer & accumulate negative ( evmwumian ) . 627 figure 140. vector nand ( evnand ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 list of figures RM0004 23/1176 figure 141. vector negate ( evneg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 figure 142. vector nor ( evnor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 figure 143. vector or ( evor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 figure 144. vector or with complement ( evorc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 figure 145. vector rotate left word ( evrlw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 figure 146. vector rotate left word immediate ( evrlwi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 figure 147. vector round word ( evrndw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 figure 148. vector select ( evsel ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 figure 149. vector shift left word ( evslw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 figure 150. vector shift left word immediate ( evslwi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 figure 151. vector splat fractional immediate ( evsplatfi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 figure 152. evsplati sign extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 figure 153. vector shift right word immediate signed ( evsrwis ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 figure 154. vector shift right word immediate unsigned ( evsrwiu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 figure 155. vector shift right word signed ( evsrws ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 figure 156. vector shift right word unsigned ( evsrwu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 figure 157. evstdd results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 figure 158. evstddx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 figure 159. evstdh results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 figure 160. evstdhx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 figure 161. evstdw results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 figure 162. evstdwx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 figure 163. evstwhe results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 figure 164. evstwhex results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 figure 165. evstwho results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 figure 166. evstwhox results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 figure 167. evstwwe results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 figure 168. evstwwex results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 figure 169. evstwwo results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 figure 170. evstwwox results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 figure 171. vector subtract signed, modulo, integer to accumulator word ( evsubfsmiaaw ) . . . . . . . 659 figure 172. vector subtract signed, saturate, integer to accumulator word ( evsubfssiaaw ) . . . . . . . 660 figure 173. vector subtract unsigned, modulo, integer to accumulator word ( evsubfumiaaw ) . . . . . 661 figure 174. vector subtract unsigned, saturate, integer to accumulator word ( evsubfusiaaw ) . . . . . 662 figure 175. vector subtract from word ( evsubfw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 figure 176. vector subtract immediate from word ( evsubifw ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 figure 177. vector xor ( evxor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 figure 178. two-element vector operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 figure 179. floating-point data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 figure 180. bi field (bits 11?14 of the instruction encoding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118 RM0004 about this book 24/1176 about this book the primary objective of this reference is to provide a view of the programming model defined by book e and the book e implementation standards (eis). book e is a powerpc? architecture definition for embedded processors that ensures binary compatibility with the user in struction set architecture (u isa) portion of the powerpc architecture as it was jointly developed by apple, ibm, and motorola (now freescale semiconductor, inc.). this book should be used with the user documentation for individual implementations; such documents provide a high-level summary of the information that appears here, as well as implementation-specific features and implementation differences that are not described here. this document distinguishes between the three levels of the architectural and implementation definition, as follows: the book e architecture ?book e defines a se t of user-level instructions and registers that are drawn from the uisa portion of the aim definition of the powerpc architecture. book e also include numerous other supervisor -level registers and instructions as they were defined in the aim version of the powerpc architecture for the virtual environment architecture (vea) and the operating environm ent architecture (oea). because book e defines a much different model for operating system resources such as the mmu and interrupts, it defines many new registers and instructions. book e implementation standards (eis). in many cases, the book e architecture definition provides a very general framework, leaving many higher-level details up to the implementation. to ensure consistency among its book e implementations, working standards were defined, providing an additional layer of architecture between book e and actual devices. this layer includes more specific definitions of book e features as well as extensions to the archit ecture, typically in the form of auxiliary processi ng units (apus), which define additional regist ers, instructions, and interr upts that provide specially targeted capabilities. note that some apus are implem entation-specific and are available only on individual devices. the apus described here are those that are implemented on multiple processo rs or families of processors. the eis guarantees that if an apu is implemented, it conforms to the eis architecture described here. information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. as with any technical documentation, it is the readers? responsibility to be su re they are using the most recent version of the documentation. audience it is assumed that the reader has the appropriate general knowledge regarding operating systems, microprocessor system design, and the basic principles of risc processing to use the information in this manual. about this book RM0004 25/1176 organization following is a summary and a brief description of the major sections of this manual: part i: book e and book e implementation standards ,? describes the programming model defined by the powerpc book e architecture and the eis. it consists of the following chapters: ? chapter 1: overview ,? provides a general discussion of the programming, interrupt, cache, and memory management models as they are defined by book e and the eis. ? chapter 2: register model ,? is useful for software engineers who need to understand the programming model in general and the functionality of each register. ? chapter 3: instruction model ,? provides an overview of the addressing modes and a description of the instructions. instructions are organized by function. ? chapter 4: interrupts and exceptions ,? provides an overview of the book e? and eis-defined interrupts and exception conditions that can cause them. ? chapter 5: storage architecture ,? describes the cache and mmu portions of the eis. ? chapter 6: instruction set ,? functions as a handbook for the instruction set. instructions are sorted by mnemonic. each instruction description includes the instruction formats and an individualized legend that provides such information as the level or levels of the architecture in which the instruction may be found and the privilege level of the instruction. part ii: eis-defined extensions to the book e architecture ,? describes the auxiliary procession units (apus) defined by the eis. it consists of th e following chapters: ? chapter 7: auxiliary pr ocessing units (apus) ,? describes extensions to the book e architecture defined by the eis. these include the following: - chapter 7.1: integer select apu ? - chapter 7.2: performance monitor apu ? - chapter 7.3: signal processi ng engine apu (spe apu) ? - chapter 7.4: embedded vector and scalar single-precision floating-point apus (spfp apus) ? - chapter 7.5: machine check apu ? - chapter 7.6: debug apu ? ? chapter 8: storage-related apus .? describes the following apus defined by the storage architecture: - chapter 8.1: cache line locking apu ? - chapter 8.2: direct cache flush apu ? - chapter 8.3: cache way partitioning apu ? RM0004 about this book 26/1176 subsequent chapters describe the vle extension - chapter 9: vle introduction ? - chapter 10: vle storage addressing ? - chapter 11: vle comp atibility with the eis ? - chapter 12: vle instruction classes ? - chapter 13: vle instruction set ? - chapter 14: vle instruction index ? the following appendixes are included: ? appendix a: instruction set listings ,? lists all instructions except those defined by the vle extension instructions by both mnemonic and opcode, and includes a quick reference table with general information, such as the architecture level, privilege level, form, and whether the instruction is optional. vle instruction opcodes are listed in section 13: vle instruction set .? ? appendix b: simplified mnemonics for powerpc instructions ,? describes simplified mnemonics, which are provided for easier coding of assembly language programs. simplified mnemonics are defined for the most frequently used forms of branch conditional, compare, trap, rotate and shift, and certain other instructions defined by the powerpc? architecture and by implementations of and extensions to the powerpc architecture. ? appendix c: programming examples ,? gives examples of how memory synchronization instructions can be used to emulate various synchronization primitives and to provide more complex forms of synchronization. it also describes multiple precision shifts. ? appendix d: guidelines for 32-bit book e ,? provides guidelines used by 32-bit book e implementations; a set of guidelines is also outlined for software developers. application software written to these guidelines can be labeled 32-bit book e applications and can be expected to execute properly on all implementations of book e, both 32-bit and 64-bit implementations. ? appendix e: embedded floating-point results , ? provides guidelines used by 32-bit book e implementations; a set of guidelines is also outlined for software developers. application software written to these guidelines can be labeled 32-bit book e applications and can be expected to execute properly on all implementations of book e, both 32-bit and 64-bit implementations. this book includes a glossary and an index. suggested reading RM0004 27/1176 suggested reading this section lists additional reading that provides background for the information in this manual as well as general information about the architecture. general information the following documentation, published by morgan-kaufmann publishers, 340 pine street, sixth floor, san francisco, ca, provides useful information about the powerpc architecture and computer architecture in general: the powerpc architecture: a specificatio n for a new family of risc processors , second edition, by international business machines, inc. related documentation st documentation is available from the sources listed on the back cover of this manual; the document order numbers are included in parentheses for ease in ordering: reference manuals?these books (formerly called user?s manuals) provide details about individual implementations and are intended for use with the eref . addenda/errata to reference manuals?because some processors have follow-on parts an addendum is provided that describes the additional features and functionality changes. these addenda are intended for use with the corresponding reference manuals. hardware specifications?hardware specificat ions provide specific data regarding bus timing, signal behavior, and ac, dc, and thermal characteristics, as well as other design considerations. technical summaries?each device has a technical summary that provides an overview of its features. this document is roughly the equivalent to the overview (chapter 1) of an implementation?s reference manual. application notes?these short documents address specific design issues useful to programmers and engineers working with st processors. additional literature is published as new processors become available. RM0004 suggested reading 28/1176 conventions this document uses the following notational conventions: table 1. conventions additional conventions used with instruction encodings are described in ta b l e 1 9 5 . convention description cleared/set when a bit takes the value zero, it is said to be cleared; when it takes a value of one, it is said to be set. mnemonics instruction mnemonics are shown in lowercase bold. italics italics indicate variable command parameters, for example, bcctr x. book titles in text are set in italics. internal signals are set in italics, for example, qual bg 0x prefix to denote hexadecimal number 0b prefix to denote binary number r a, r b instruction syntax used to identify what is typically a source gpr r d instruction syntax used to identify a destination gpr fr a, fr b, fr c instruction syntax used to identify a source fpr fr d instruction syntax used to identify a destination fpr reg[field] abbreviations for registers are shown in uppercase text. specific bits, fields, or ranges appear in brackets. for example, msr[le] refers to the little-endian mode enable bit in the machine state register. x in some contexts, such as signal encodings, an unitalicized x indicates a don?t care. x an italicized x indicates an alphanumeric variable. n an italicized n indicates an numeric variable. ? not logical operator & and logical operator | or logical operator || concatenation operator; for example, 010 || 111 is the same as 010111 indicates a reserved field in a r egister. although these bits can be written to as ones ? acronyms and abbreviations RM0004 29/1176 acronyms and abbreviations ta bl e 2 contains acronyms and abbreviations that are used in this document. table 2. acronyms and abbreviated terms term meaning cr condition register ctr count register dtlb data translation lookaside buffer ea effective address ecc error checking and correction fpr floating-point register fpu floating-point unit gpr general-purpose register ieee institute of electrical and electronics engineers itlb instruction translation lookaside buffer l2 secondary cache lifo last-in-first-out lr link register lru least recently used lsb least-significant byte lsb least-significant bit mmu memory management unit msb most-significant byte msb most-significant bit msr machine state register nan not a number nia next instruction address no-op no operation oea operating environment architecture pte page table entry risc reduced instruct ion set computing rtl register transfer language simm signed immediate value spr special-purpose register tb time base register tlb translation lookaside buffer RM0004 acronyms and abbreviations 30/1176 uimm unsigned immediate value uisa user instruction set architecture va virtual address vea virtual environment architecture vle variable length encoding xer register used primarily for indicating conditions such as carries and overflows for integer operations table 2. acronyms and abbreviated terms (continued) term meaning terminology conventions RM0004 31/1176 terminology conventions ta bl e 3 lists certain terms used in this manual that differ from the architecture terminology conventions. ta bl e 4 describes instruction field notation conventions used in this manual. table 3. terminology conventions the architecture spec ification this manual extended mnemonics simplified mnemonics privileged mode (or privileged state) supervisor level problem mode (or problem state) user level real address physical address relocation translation out-of-order memory accesses speculative memory accesses storage (locations) memory storage (the act of) access table 4. instruction field conventions the architecture specif ication equivalent to: ba, bb, bt crb a, crb b, crb d (respectively) bf, bfa crf d, crf s (respectively) dd ds ds flm fm fra, frb, frc, frt, frs fr a, fr b, fr c, fr d, fr s (respectively) fxm crm ra, rb, rt, rs r a, r b, r d, r s (respectively) si simm uimm ui uimm /, //, /// 0...0 (shaded) RM0004 part i: book e and book e implementation standards 32/1176 part i: book e and book e implementation standards part i describes the registers and instructions defined by the book e architecture and by the book e implementation standards (eis). it contains the following chapters: chapter 1: overview ,? provides a general discussion of the programming, interrupt, cache, and memory management models as they are defined by book e and the eis. chapter 2: register model ,? is useful for software engineers who need to understand the programming model in general and the functionality of each register. chapter 3: instruction model ,? provides an overview of the addressing modes and a description of the instructions. instructions are organized by function. chapter 4: interrupts and exceptions ,? provides an overview of the book e? and eis? defined interrupts and exception conditions that can cause them. chapter 5: storage architecture ,? describes the cache and mmu portions of the eis. overview RM0004 33/1176 1 overview this document describes the book e version of the powerpc? architecture as it is further defined by the book e implementation standards (eis) and implemented on book e cores. this chapter includes ov erviews of the following: features of the book e version of the powerpc architecture and implementation- details defined by the eis the book e and eis programming model the book e and eis interrupt model the book e and eis memory management model architectural compatibility and migration fr om the original version of the powerpc architecture as defined by apple, ibm, and motorola (referred to as the aim version of the powerpc architecture) 1.1 overview book e and the bo ok e implementation standards (eis) book e is a version of the powerpc architecture intended for embedded processors. to ensure application-level compatibility with the powerpc architecture developed by apple, ibm and freescale, book e incorporates the user-level resources defined in the user instruction set architecture (uisa), book i, of the aim architectural definition. because operating systems for embedded processors have different needs than those for desktop systems, book e defines more flexible interrupt and memory management models. instead of the segmented memory model defined by the aim architecture, book e provides a page-based memory system that supports multiple variable-sized pages managed through translation lookaside buffers (tlbs). interrupt offsets can be programmed through interrupt-specific interrupt vector offset registers (ivors). book e defines the interrupt vector prefix register (ivpr), which is programmed with a prefix value that is concatenated with the ivor values to place the interrupt vector table anywhere in memory. as a consequence, some resources defined by the aim version of the architecture are no longer supported and new ones are provided. for example, segment and block address translation (bat) registers are gone, and new instructions, registers, and interrupts have been defined for managing page translation and protection through tlbs. moreover, the book e arch itecture allows greater flexibility. for example, book e defines the tlb write entry ( tlbwe ) and tlb read entry ( tlbre ) instructions only very generally, leaving details of their execution and behavior up to the implementation. however, to ensure compatibility among book e implementations, the book e implementa tion standard (eis) defines more specifically ho w these instructions work. RM0004 overview 34/1176 1.1.1 auxiliary processing units (apus) book e supports the use of auxiliary processi ng units (apus), which allocate opcode and register space for extending the instruction set without affecting the instruction set defined by book e. this facilitates the development of special-purpose resources that are useful to some embedded environments but impractical for others. note that instructions from multiple apus may be assigned the same opcode numbers of the allocated opcode space. the eis defines many apus. these apus are not required on all devices, but devices that implement them do so strictly following the eis architectural definition. in addition, an implementation may also provide an apu that is not a part of the eis. apus may consist of any combination of instructions, optional behavior of book e?defined instructions, registers, register files, fields within book e?defined registers, interrupts, or exception conditions within book e?defined interrupts. chapter 7: auxiliary pr ocessing units (apus) ,? provides an overview of specific apus. 1.2 instruction set the instruction set of a st 32-bit book e?compliant device includes the following: the book e instruction set for 32-bit implem entations. this is composed primarily of the user-level instructions defined by the uisa. some implementations do not include the book e floating-point instructions or the load string word indexed instruction ( lswx ). instructions defined by eis apus. these include the following: ? integer select apu. this apu consists of the integer select instruction ( isel ), which incorporates an if - then-else statement that selects between two source registers by comparison to a cr bit. this instruction eliminates conditional branches, decreases band latency, and reduces the code footprint. ? spe (signal processing engine) apu instructions. spe instructions treat 64-bit gprs as a vector of two 32-bit elements (some instructions also read or write 16- bit elements). chapter 3.6.1: spe an d embedded floati ng-point apus on page 186 ,? lists spe apu vector instructions. ? the embedded vector floating-point apu provides instructions that use the upper and lower words of the 64-bit gprs for single-precision, vector floating-point calculations. ? the embedded scalar single-precision apu provides instructions that use the lower 32 bits of the gprs for single-prec ision, scalar floating-point calculations. ? the embedded scalar double-precision apu instructions use the 64-bit gprs for floating-point calculations. ? performance monitor apu?this apu defines two instructions, mfpmr and mtpmr , used for reading and writing the performance monitor registers (pmrs). ? cache block lock and unlock apu, co nsisting of the following instructions: - data cache block lock clear ( dcblc ) - data cache block touch and lock set ( dcbtls ) - data cache block touch for store and lock set ( dcbtstls ) - instruction cache block lock clear ( icblc ) - instruction cache block touch and lock set ( icbtls ) overview RM0004 35/1176 1.3 register set note: devices that implement a particular core may not implement all registers defined by that core. figure 1. eis programming model register set (1.) the 64-bit gpr registers are accessed by the spe as se parate 32-bit operands by spe instructions. only spe vector instructions can access the upper word. (2.) usprg0 is a separat e physical register from sprg0. (3.) eis-defined registers; not part of the book e architecture. user-level registers register files instruction-accessible registers user general spr (read/write) 0 31 32 63 0 31 32 63 32 63 user spr general 0 (upper) gpr0 1 (lower) general-purpose registers (gprs) cr condition register spr 256 usprg0 2 gpr1 spr 9 ctr count register general sprs (read-only) gpr31 spr 8 lr link register spr 259 sprg3 spr general registers 3?7 fpr0 floating-point registers (fprs) spr 260 sprg4 spr 1 xer integer exception register fpr1 fpscr floating-point status/control register spr 263 sprg7 fpr31 spr 512 spefscr 3 sp/embedded fp status/control register time-base registers (read-only) performance monitor registers (pmrs) acc 3 accumulator spr 268 tbl time base lower/upper pmr 128?131 upmlcas 3 local control registers a0?a3 b0?b3 spr 269 tbu pmr 256?259 upmlcbs 3 l1 cache (read-only) spr 526 at b l 3 alternate time base lower/upper pmr 384 upmgc0 3 global control register spr 515 l1cfg0 3 l1 cache configuration registers 0?1 spr 527 at b u 3 spr 516 l1cfg1 3 pmr 0?3 upmcs 3 counters 0?3 supervisor-level registers interrupt registers configuration registers 32 63 32 63 32 63 spr 63 ivpr interrupt vector prefix register spr 400 ivor0 interrupt vector offset registers 0?15 msr machine state register spr 401 ivor1 spr 26 srr0 save/restore registers 0/1 spr 1023 svr 3 system version register spr 27 srr1 spr 415 ivor15 spr 286 pir processor id register spr 58 csrr0 critical srr 0/1 processor version register spr 59 csrr1 spr 528 ivor32 3 interrupt vector offset registers 32?35 spr 287 pvr spr 570 mcsrr0 3 machine check srr 0/1 spr 529 ivor33 3 timer/decrementer registers spr 571 mcsrr1 3 spr 530 ivor34 3 spr 574 dsrr0 3 debug srr 0/1 spr 531 ivor35 3 spr 22 dec decrementer spr 575 dsrr1 3 decrementer auto-reload register mmu control and status (read/write) spr 54 decar exception syndrome register spr 62 esr mmu control and status register 0 spr 1012 mmucsr0 3 spr 284 tbl time base lower/upper spr 572 mcsr 3 machine check syndrome register spr 285 tbu spr 624 mas0 3 mmu assist registers 0?7 spr 573 mcar 3 machine check address register spr 625 mas1 3 spr 340 tcr timer control register spr 61 dear data exception address register spr 336 tsr timer status register spr 630 mas6 3 spr 944 mas7 3 miscellaneous registers debug registers spr 48 pid0 process id registers 0?2 spr 272?279 sprg0?7 general sprs 0?7 spr 308?310 dbcr0?2 debug control 0?2 spr 633 pid1 3 hardware implementation dependent 0?1 spr 561 dbcr3 debug control 3 spr 1008 hid0 3 spr 634 pid2 3 spr 1009 hid1 3 spr 304 dbsr debug status register mmu control and status (read only) performance monitor registers spr 312?315 iacs instruction address compare1?4 spr 1015 mmucfg 3 mmu configuration pmr 400 pmgc0 3 global control spr 316?317 dacs data address compare 1?2 spr 688 tlb0cfg 3 tlb configuration 0/1 pmr 16?19 pmc0?3 3 counter registers 0?3 spr 318?319 dvcs data value compare 1?2 spr 689 tlb1cfg 3 pmr 144?147 pmca0?3 3 local control a0?a3 l1 cache (read/write) pmr 272?275 pmcb0?3 3 local control b0?b3 spr 1010 l1csr0 3 l1 cache control/status registers 0/1 spr 1011 l1csr1 3 l1 flush and invalidate control register 0 spr 1015 l1finv0 3 RM0004 overview 36/1176 1.4 interrupts and exception handling book e and the eis support an extended exception handling model, with nested interrupt capability and extensive interrupt vector pr ogrammability. the following sections define the exception model, including an overview of exception handling as implemented in a st book e device, a brief description of the exception classes, and an overview of the registers involved. 1.4.1 exception handling in general, interrupt processing begins with an exception that occurs due to external conditions, errors, or program execution problems. when the exception occurs, the processor checks to verify that interrupt processing is enabled for that particular exception. if enabled, the interrupt causes the state of the processor to be saved in the appropriate registers, and prepares to begin execution of the handler located at the associated vector address for that particular exception. once the handler is executing, the implementation may need to check one or more bits in the exception syndrome regist er (esr) or the spefscr, depen ding on the exception type, to verify the specific cause of the exception and take appropriate action. the interrupts are described in chapter 1.4.4: interrupt registers ,? and in ta bl e 6 . 1.4.2 interrupt classes all interrupts may be categorized as asynch ronous/synchronous and critical/noncritical. asynchronous interrupts are caused by events that are independent of instruction execution. the address reported in the save/restore register is that of the instruction that would have executed next had the asynchronous interrupt not occurred. synchronous interrupts are caused directly by the execution or attempted execution of instructions. synchronous inputs can be precise or imprecise: ? synchronous precise interrupts are those that precisely indicate the address of the instruction causing the exception that generated the interrupt or, in some cases, the address of the next instruction in program order. the interrupt type and status bits allow determination of which of the two instructions has been addressed in the appropriate save/restore register. ? synchronous imprecise interrupts may indicate the address of the instruction causing the exception that generated the interrupt or some instruction after the instruction causing the interrupt. if the interrupt was caused by either the context synchronizing mechanism or the exec ution synchronizing mechanism, the address in the appropriate save/restore register is the address of the interrupt forcing instruction. if the interrupt was not caused by either of those mechanisms, the address in the save/restore register is the last instruction to start execution and may not have completed. no instruction following the instruction in the save/restore register has executed. 1.4.3 interrupt categories book e defines critical and noncritical interrupt categories, and the eis defines the machine check and debug interrupt categories. each category has a separate set of save and restore registers to which machine state and a return address are automatically written when an interrupt is taken. each category has a return from interrupt instruction that uses the save and restore registers to reestablish the machine state of the interrupted process and overview RM0004 37/1176 provides the address within that process at which to resume execution after the interrupt handler completes. additional resources are provided for masking some of these interrupt categories, as described in the following: debug apu interrupt (if present)?although book e defines debug as a critical interrupt, the eis defines a separate debug apu. debug save and restore registers (dsrr0/dsrr1) save state when a debug interrupt is taken; rdci restores state at the end of the interrupt handler. these interrupts are masked by setting the machine check enable bit, msr[de]. machine check apu interrupt (if present)?although book e defines machine check as a critical interrupt, the eis defines a separate machine check apu. machine check save and restore registers (mcsrr0/mcsrr1) save state when a machine check interrupt is taken; rfmci restores state at the end of the interrupt handler. these interrupts are masked by setting the machine check enable bit, msr[me]. noncritical interrupts?first-level interrupts that allow the processor to change program flow to handle conditions generated by external signals, errors, or unusual conditions arising from program execution or from programmable timer-related events. these interrupts are largely identical to those defined by the oea portion of the power pc architecture. they use save and restore registers (srr0/srr1) to save processor state and the rfi instruction to restore state. asynchronous noncritical interrupts can be masked by the external interrupt enable bit, msr[ee]. critical interrupts?can be taken during a noncritical interrupt or during regular program flow. they use the critical save and restore registers (csrr0/csrr1) to save state when they are taken; they use the rfci instruction to restore state. these interrupts can be masked by the critical enable bit, msr[ce]. book e defines the critical input and watchdog timer in terrupts as critical interrupts. one interrupt of each category can be reported at a time; when it is taken, no program state is lost. save/restore register pairs are serially reusable, so program state may be lost when an unordered interrupt is taken. see section 4.10: interrupt ordering and masking .? 1.4.4 interrupt registers the registers associated with interrupt and exception handling are described in ta bl e 5 . table 5. interrupt registers register description non critical interrupt registers srr0 save/restore register 0?stores th e address of the instruction causin g the exception or the address of the instruction that will execute after the rfi instruction. srr1 save/restore register 1?saves machine state on non critical interrupts and restores machine state after an rfi instruction is executed. critical interrupt registers csrr0 critical save/restore register 0?on critical in terrupts, csrr0 stores either the address of the instruction causing the exception or the address of the instruction that will execute after the rfci instruction. csrr1 critical save/restore register 1?csrr1 saves mach ine state on critical interrupts and restores machine state after an rfci instruction is executed. RM0004 overview 38/1176 ta bl e 6 lists ivor registers and associated interrupts. machine check inte rrupt registers mcsrr0 machine check save/restore register 0?stores the address of the instructi on that executes after rfmci executes. mcsrr1 machine check save/restore register 1?mcsrr1 st ores machine state on machine check interrupts and restores machine state (if recoverable) after an rfmci instruction is executed. mcar machine check address register?mcar holds the addres s of the data or instruction that caused the machine check interrupt. mcar contents are not meaningful if a signal triggered the machine check interrupt. debug interrupt registers dsrr0 debug save/restore register 0?stores the address of the instructi on that executes after rfdi executes. dsrr1 debug save/restore register 1?stores machine state on machine check interrupts and restores machine state (if re coverable) after rfmci executes. syndrome registers mcsr machine check syndrome register?mcsr saves machine state information on machine check interrupts and restores machine state after an rfmci instruction is executed. esr exception syndrome register?esr provides a syndrome to differentiate between the different kinds of exceptions that generate the same interrupt type. upon generation of a specific exception type, the associated bit is set and all other bits are cleared. spe and embedded floating-point apu interrupt registers spefscr signal processing and embedded floating-point status and control register?provides interrupt control and status as well as various condition bits as sociated with the operations performed by the spe apu and the embedded floating-point apus. other interrupt registers dear data exception address register?dear contains the address that was referenced by a load, store, or cache management instruction that caused an ali gnment, data tlb miss, or data storage interrupt. ivpr interrupt vector prefix register?i vpr[32?47] contains the high-order 16 bits of the address of the exception processing routines defined in the ivor registers. ivors interrupt vector offset registers?the ivors cont ain the low-order offset of the address of the exception processing routines defined in the ivor registers. see ta bl e 6 . table 5. interrupt registers (continued) register description overview RM0004 39/1176 each interrupt has an associated interrupt vector address, obtained by concatenating the ivpr and ivor values (ivpr[32?47]||ivor n [48?59]||0b0000). the resulting address is that of the instruction to be executed when that interrupt occurs. ivpr and ivor values are indeterminate on reset, and must be initialized by the system software using mtspr . for more information, see chapter 4: interrupts and exceptions .? table 6. interrupt vector registers and exception conditions register interrupt book e?defined ivors ivor0 critical input ivor1 machine check interrupt offset ivor2 data storage interrupt offset ivor3 instruction storage interrupt offset ivor4 external input interrupt offset ivor5 alignment interrupt offset ivor6 program interrupt offset ivor7 floating-point unavailable interrupt offset ivor8 system call interrupt offset ivor9 auxiliary processor unavailable interrupt offset ivor10 decrementer interrupt offset ivor11 fixed-interval timer interrupt offset ivor12 watchdog timer interrupt offset ivor13 data tlb error interrupt offset ivor14 instruction tlb error interrupt offset ivor15 debug interrupt offset eis-defined ivors ivor32 spe apu unavailable interrupt offset ivor33 embedded floating-point data exception interrupt offset ivor34 embedded floating-point round exception interrupt offset ivor35 performance monitor interrupt offset RM0004 overview 40/1176 1.5 memory management the eis supports demand-paged virtual memory as well other memory management schemes that depend on precise control of effective-to-physical address translation and flexible memory protection as defined by book e. the mapping mechanism consists of software-managed tlbs that support variable-sized pages with per-page properties and permissions. the following properties can be configured for each tlb: user mode page execute access user mode page read access user mode page write access supervisor mode page execute access supervisor mode page read access supervisor mode page write access write-through required (w) caching inhibited (i) memory coherence required (m) guarded (g) endianness (e) user-definable (u0?u3), a 4-bit implementation-specific field 1.5.1 address translation figure 2 shows a typical translation flow, although each implementation may differ in the specific details. the mmu translates 32-bit effective addresses generated by loads, stores, and instruction fetches into 32-bit real addresses (used for memory bus accesses) using an interim 41-bit virtual address. overview RM0004 41/1176 figure 2. effective-to-real address translation flow as figure 2 shows, address translation starts with an effective address that is prepended with an address space (as) value and a process id to construct a virtual address (va). the virtual address is then translated into a real address based on the translation information found in the on-chip tlb of the appropriate l1 mmu. the as bit for the access is selected from the value of msr[is] or msr[ds], for instruction or data accesses, respectively. the appropriate l1 mmu (instruction or data) is checked for a matching address translation. the instruction l1 mmu and data l1 mmu operate independently and can be accessed in parallel, so that hits for instruction accesses and data accesses can occur in the same clock. if an l1 mmu misses, the request for translation is forwarded to the unified (instruction and data) l2 mmu. if found, the contents of the tlb entry are concatenated with the byte address to obtain the physical address of the requested access. on misses, the l1 tlb entries are replaced from their l2 tlb counterparts using a true lru algorithm. 1.5.2 mmu assist registers (mas1?mas7) book e defines spr numbers for the mmu assist registers, used to hold values either read from or to be written to the tlbs and information required to identify the tlb to be accessed. book e leaves mas register bit definitions up to the implementations. to ensure consistency among st book e processors, certain aspects of the implementation are defined by the book e standard; more specific details are left to individual implementations. mas3 implements the real page number (rpn), the user attribute bits (u0?u3), and effective page number byte address real page number byte address 32-bit effective address (ea) 32-bit real address 15?20 bits* 12?17 bits* 15?20 bits* 12?17 bits* l2 mmu (unified) three 41-bit virtual addresses (vas) 8 bits msr ??? is ds ??? instruction access data as pid0 pid1 pid2 l1 mmus instruction l1 mmu data l1 mmu 2 tlbs 2 tlbs * number of bits depends on page size (4 kbytes?256 mbytes) 16-entry fully-assoc. vsp array 256-entry 2-way set assoc. array (tlb0) RM0004 overview 42/1176 permission bits (ux, sx, uw, sw, ur, sr) that specify user and supervisor read, write, and execute permissions. some cores may not does not implement all of the mas registers. mas registers are affected by the following instructions: mas registers are accessed with the mtspr and mfspr instructions. the tlb read entry instruction ( tlbre ) causes the contents of a single tlb entry from the l2 mmu to be placed in defined locations in mas0?mas3. the tlb entry to be extracted is determined by information written to mas0 and mas2 before the tlbre instruction is executed. the tlb write entry instruction ( tlbwe ) causes the information stored in certain locations of mas0?mas3 to be written to the tlb specified in mas0. the tlb search indexed instruction ( tlbsx ) updates mas registers conditionally, based on success or failure of a lookup in the l2 mmu. the lookup is specified by the instruction encoding and specific search fiel ds in mas6. the values placed in the mas registers may differ, depending on a successful or unsuccessful search. for tlb miss and certain mmu-related dsi/isi exceptions, mas4 provides default values for updating mas0?mas2. 1.5.3 process id regi sters (pid0?pid2) the book e architecture identifies a single process id register (pid). the eis defines additional pids to hold values used to c onstruct the virtual addresses for each access. among these pids, pid0 is the book e?defined pid. these process ids provide an extended page sharing capability. which of these three virtual addresses is used for translation is controlled by the tid field of a matching tlb entry, and when tid = 0x00 (identifying a page as globally shared), the pid values are ignored. a hit to multiple tlb entries in the l1 mmu (even if they are in separate arrays) or a hit to multiple entries in the l2 mmu is considered to be a programming error. 1.5.4 tlb coherency tlb entries can be invalidated as defined in the book e architecture. the tlbivax instruction invalidates a matching local tlb entry. 1.5.5 atomic update memory references book e supports atomic update memory references for both aligned word forms of data using the load and reserve and store conditional instruction pair, lwarx and stwcx. . typically, a load and reserve instruction establishes a reservation and is paired with a store conditional instruction to achieve the atomic operation. however, the programmer is responsible for preserving reservations across context switches and for protecting reservations in multiprocessor implementations. 1.5.6 memory access ordering to optimize performance, book e supports weakly ordered references to memory. thus, a processor manages the order and synchronization of instructions to ensure proper execution when memory is shared between multiple processes or programs. the cache and data memory control attributes, along with msync and mbar , provide the required access overview RM0004 43/1176 control; msync and mbar are also broadcast to provide the appropriate control in the case of multiprocessor or s hared memory systems. 1.5.7 cache control instructions book e cache control instructions perform a full range of cache control functions, including cache locking by line. the eis defines the following cache locking instructions: data cache block lock clear ( dcblc ) data cache block touch and lock set ( dcbtls ) data cache block touch for store and lock set ( dcbtstls ) instruction cache block lock clear ( icblc ) instruction cache block touch and lock set ( icbtls ) 1.5.8 programmable page characteristics cache and memory attributes are programmable on a per-page basis. in addition to the write-through, caching-inhibited, memory cohe rency enforce, and guarded characteristics defined by the wimg bits, book e defines an endianness bit, e, that selects big- or little- endian byte ordering on a per-page basis. 1.6 performance monitoring the eis provides a performance monitoring capability th at supports counting of events such as processor clocks, instruction cache misses, data cache misses, mispredicted branches, and others. the count of these events may be configured to trigger a performance monitor exception. this interrupt is assigned to vector offset register ivor35. the register set associated with performance moni toring consists of counter registers, a global control register, and local control registers. these registers are read/write from supervisor mode, and each register is reflected to a corresponding read-only register for user mode. the mtpmr and mfpmr instructions move data to and from these registers. an overview of the performance monitoring registers is provided in the following sections. for more information, see chapter 7.2: performance monitor apu .? 1.6.1 global control register the performance monitor global control register 0 (pmgc0) provides global control of the performance monitor from supervisor mode. from this register all counters may be frozen, unfrozen, or configured to freeze on an enabled condition or event. additionally, the performance monitoring facility may be disabled or enabled from this register. the pmgc0 contents are reflected to upmgc0, which may be read from user mode using mfpmr . 1.6.2 performance moni tor counter registers there are four counter register s (pcm0?pcm3) provided in the performance monitor facility. these 32-bit registers hold the current count for software-selectable events and can be programmed to generate an exception on overflow. they can be accessed from supervisor mode using mtpmr and mfpmr . their contents are reflected to upcm0?upcm3, which can be read from user mode with mfpmr . the exception generated on overflow can be masked by clearing msr[ee]. RM0004 overview 44/1176 1.6.3 local control registers for each counter register, there are two corresponding local control registers. these two registers specify which of the 128 available events is to be counted, the action to be taken on overflow, and options for freezing a counter value under given modes or conditions. pmlca0?pmlca3 provide fields that allow freezing of the corresponding counter in user mode, supervisor mode, or under software control. the overflow condition may be enabled or disabled from these registers. register contents are reflected to upmcla0? upmlca3, which can be read from user mode with mfpmr . pmlcb0?pmlcb3 provide count scaling for each counter register using configurable threshold and multiplier values. the threshold is a 6-bit value and the multiplier is a 3- bit encoded value, allowing 8 multiplier values in the range of 1 to 128. any counter may be configured to increment only when an event occurs more than [threshold multiplier] times. the contents of these registers are reflected to upmclb0?upmlcb3, which can be read from user mode with mfpmr . 1.7 legacy support of powerpc architecture in general, st book e processors support the user-level portion of the aim architecture. the following subsections highlight the main differences. for specific details, refer to the relevant chapter. 1.7.1 instruction set compatibility the following sections generally describe co mpatibility between book e and aim powerpc instruction sets. user instruction set the user mode instruction set defined by the aim version of the powerpc architecture is compatible with st book e processo rs with the following exceptions: floating-point functionality provided by the embedded floating-point apus differs from the aim defined floating-point isa. also, the vector and double-precision floating-point apus use 64-bit gprs rather than the fprs defined by the uisa. most porting of floating-point operations ca n be handled by recompiling; however, there are new instructions specific to the apus. string instructions are typically not implemented; therefore, trap emulation must be provided to ensure backward compatibility. supervisor instruction set the supervisor mode instruction set defined by the aim version of the powerpc architecture is compatible with the eis wit h the following exceptions: the mmu architecture is different, so some tlb manipulation instructions have different semantics. instructions that support the bats and segment registers are not implemented. interrupt vectors are defined by the book e ivor n and ivpr sprs. additional instructions are defined for returning from book e?defined critical interrupts ( rfci ) and apu-specific interrupts. overview RM0004 45/1176 1.7.2 memory subsystem both book e and the aim version of the powerpc architecture provide separate instruction and data memory resources. the eis provides additional cache control features, including cache locking. 1.7.3 interrupt handling interrupt handling is generally the same as that defined in the aim version of the powerpc architecture, with the following differences: (see chapter 1.4 ) book e defines a new critical interrupt, providing an extra le vel of interrupt nesting. the critical interrupt includes external critical and watchdog timer time-out inputs. the machine check apu implements the machine check exception differently from the book e and from the aim definition. it defines the return from machine check interrupt instruction, rfmci , and two machine check save/restore registers, mcsrr0 and mcsrr1. book e processors can use ivpr and ivors to set exception vectors individually. to provide compatibility, they can be set to the address offsets defined in the oea. unlike the aim version of the powerpc architecture, book e does not define a reset vector; execution begins at a fixed virtual address, 0xffff_fffc. some sprs are different from those defined in the aim version of the powerpc architecture, particularly those related to the mmu functions. much of this information has been moved to a new exception syndrome register (esr). timer services are generally compatible, although book e defines a new decrementer auto reload feature and the fixed-interval timer critical interrupt. 1.7.4 memory management st book e processors implement a straightforward virtual address space that complies with the book e mmu definition, which eliminates segment registers and block address translation resources. book e defines resources for fixed 4-kbyte pages and multiple, variable page sizes that can be configured in a single implementation. tlb management is provided with new in structions and sprs. 1.7.5 requirements for sy stem reset generation book e does not specify a system reset interrupt as was defined in the aim version of the powerpc architecture, but typically, system reset is initiated either by asserting a signal or by software (for example, writing a 1 to dbcr0[34], if msr[de] = 1 at reset, instead of invoking a reset interrup t, fetching at address 0xffff_fffc, as defined by book e. in addition to the book e reset definition, the eis and the implementation define specific aspects of mmu page translation and protection mechanisms. unlike the aim version of the powerpc core, as soon as instruction fetching begins, the core is in virtual mode with a hardware-initialized tlb entry. 1.7.6 little-endian mode unlike the aim version of the powerpc, where the little-endian mode is controlled on a system basis, book e supports control of byte ordering on a memory page basis. additionally, true little-endian mode is supported by byte swapping. RM0004 register model 46/1176 2 register model this chapter describes the register model and indicates the architecture level at which each register is defined. 2.1 overview although this chapter organizes registers according to their functionality, they can be differentiated according to how they are accessed, as follows: register files. these user-level registers are accessed explicitly through source and destination operands of computational, load/store, logical, and other instructions. book e defines two types of register files: ? general-purpose registers (gprs), used as source and destination operands for most operations (except book e?defined floating-point instructions, which use fprs). see chapter 2.3.1: general purpose registers (gprs) .? ? floating-point registers (fprs), used for book e?defined floating-point instructions. see chapter 2.4.1: floating-point registers (fprs) .? special-purpose registers (sprs)?sprs are accessed by using the book e?defined move to special-purpose register ( mtspr ) and move from special-purpose register ( mfspr ) instructions. chapter 2.2.1: special-purpose registers (sprs) ,? lists sprs. system-level registers that are not sprs. these are as follows: ? machine state register (msr). msr is accessed with the move to machine state register ( mtmsr ) and move from machine state register ( mfmsr ) instructions. see chapter 2.6.1: machine state register (msr) .? ? condition register (cr) bits are grouped into eight 4-bit fields, cr0?cr7, which are set as follows (see chapter 2.5.1: condition register (cr) ? ): - specified cr fields can be set by a move to the cr from a gpr ( mtcrf ). - a specified cr field can be set by a move to the cr from another cr field ( mcrf ), from the fpscr ( mcrfs ), or from the xer ( mcrxr ). - cr0 can be set as the implicit result of an integer instruction. - cr1 can be set as the implicit result of a floating-point instruction. - a specified cr field can be set as the result of an integer or floating-point compare instruction (including spe and spfp compare instructions). ? the floating-point status and control register (fpscr). see chapter 2.4.2: floating-point status and control register (fpscr) .? ? the eis-defined accumulator, which is accessed by signal processing engine (spe) apu instructions that update the accumulator. see chapter 2.14.2: accumulator (acc) .? device control registers (dcrs). book e defines the existence of a dcr address space and the instructions to access them, but does not define particular dcrs. the on-chip dcrs exist architecturally outside the processor core and thus are not part of book e. the contents of dcr dcrn can be read into a gpr using mfdcr r d , dcrn. gpr contents can be written into dcr dcrn using mtdcr dcrn ,r s. see chapter 2.17: device control registers (dcrs) .? performance monitor registers (pmrs). (performance monitor apu) similar to sprs, pmrs are accessed by using the eis-defined move to performance monitor register register model RM0004 47/1176 ( mtpmr ) and move from performance monitor register ( mfspr ) instructions. see chapter 2.16: performance monitor registers (pmrs) .? 2.2 register model for 32-bi t book e implementations book e implementations include the following types of software-accessible registers: registers that are accessed as part of instruction execution. these include the following: ? the following registers are used for integer operations and are described in chapter 2.3: registers for integer operations ? : - general-purpose registers (gprs)?book e defines a set of 32 gprs used to hold source and destination operands for load, store, arithmetic, and computational instructions, and to read and write to other registers. - integer exception register (xer)?xer bits are set based on the operation of an instruction considered as a whole, not on intermediate results. (for example, the subtract from carrying instruction ( subfc ), the result of whic h is specified as the sum of three values, sets bits in the xer based on the entire operation, not on an intermediate sum.) ? registers for floating-point operations. these include the following: - floating-point registers (fprs)?32 registers used to hold source and destination operands for book e defined floating-point operations. note that the embedded floating-point apus do not implement fprs; they use gprs for floating-point operands. - floating-point status and control register (fpscr)?used with floating-point operations. these registers are described in chapter 2.4: registers for floating- point operations .? ? condition register (cr)?used to record conditions such as overflows and carries that occur as a result of executing arithmetic instructions (including those implemented by the spe and spfp apu s). the cr is described in chapter 2.5: registers for branch operations .? ? machine state register (msr)?used by the operating system to configure parameters such as user/supervisor mode, address space, and enabling of RM0004 register model 48/1176 asynchronous interrupts. msr is described in chapter 2.6.1: machine state register (msr) .? special-purpose registers (sprs). ? book e?defined special-purpose registers (sprs) that are accessed explicitly using mtspr and mfspr instructions. these registers are listed in ta b l e 7 in chapter 2.2.1: special-purpose registers (sprs) .? ? eis?defined sprs that are ac cessed explicitly using the mtspr and mfspr instructions. these registers are listed in ta bl e 8 in chapter 2.2.1: special- purpose registers (sprs) .? ? sprs are described by function in the following sections: - chapter 2.5: registers for branch operations ? - chapter 2.6: processor control registers ? - chapter 2.7: hardware implementation-dependent registers ? - chapter 2.8: timer registers ? - chapter 2.9: interrupt registers ? - chapter 2.10: software use sprs (sprg0?sprg7 and usprg0) ? - chapter 2.11: l1 cache registers ? - chapter 2.12: mmu registers ? - chapter 2.13: debug registers ? - chapter 2.14: spe and spfp apu registers ? - chapter 2.15: alternate time base registers (atbl and atbu) ? eis-defined performance monitor registers, described in chapter 2.16: performance monitor registers (pmrs) .? pmrs are like sprs, but are accessed with eis-defined move to and move from pmr instructions ( mtpmr and mfpmr ). eis-defined device control registers (dcrs). book e defines a format for implementing device-specific device-control registers. see chapter 2.17: device control registers (dcrs) .? book e defines 32- and 64-bit registers. however, except for the 64-bit fprs, only bits 32? 63 of book e?s 64-bit registers (such as lr, ctr, the gprs, srr0, and csrr0) are required to be implemented in hardware in a 32-bit book e implementation. likewise, all book e integer instructions defined to return a 64-bit result return only bits 32? 63 of the result on a 32-bit book e implemen tation. spe apu vector instructions return 64- bit values; spfp apu instructions return single-precision 32-bit values. as with the instruction set and other aspects of the architecture, book e defines some features very specifically, for example, resources that ensure compatibility with implementations of the powerpc isa. other resources are either defined as optional or are defined in a very general way, leaving specific details up to the implementation. register model RM0004 49/1176 figure 3. register model (1.) the 64-bit gpr registers are ac cessed by the spe as separate 32-bit operands by spe instructions. only spe vector instructions can access the upper word. (2.) usprg0 is a separate phy sical register from sprg0. (3.) eis-defined registers; not part of the book e architecture. user-level registers register files instruction-accessible registers user general spr (read/write) 0 31 32 63 0 31 32 63 32 63 user spr general 0 (upper) gpr0 1 (lower) general-purpose registers (gprs) cr condition register spr 256 usprg0 2 gpr1 spr 9 ctr count register general sprs (read-only) gpr31 spr 8 lr link register spr 259 sprg3 spr general registers 3?7 fpr0 floating-point registers (fprs) spr 260 sprg4 spr 1 xer integer exception register fpr1 fpscr floating-point status/control register spr 263 sprg7 fpr31 spr 512 spefscr 3 sp/embedded fp status/control register time-base registers (read-only) performance monitor registers (pmrs) acc 3 accumulator spr 268 tbl time base lower/upper pmr 128?131 upmlcas 3 local control registers a0?a3 b0?b3 spr 269 tbu pmr 256?259 upmlcbs 3 l1 cache (read-only) spr 526 at b l 3 alternate time base lower/upper pmr 384 upmgc0 3 global control register spr 515 l1cfg0 3 l1 cache configuration registers 0?1 spr 527 at b u 3 spr 516 l1cfg1 3 pmr 0?3 upmcs 3 counters 0?3 supervisor-level registers interrupt registers configuration registers 32 63 32 63 32 63 spr 63 ivpr interrupt vector prefix register spr 400 ivor0 interrupt vector offset registers 0?15 msr machine state register spr 401 ivor1 spr 26 srr0 save/restore registers 0/1 spr 1023 svr 3 system version register spr 27 srr1 spr 415 ivor15 spr 286 pir processor id register spr 58 csrr0 critical srr 0/1 processor version register spr 59 csrr1 spr 528 ivor32 3 interrupt vector offset registers 32?35 spr 287 pvr spr 570 mcsrr0 3 machine check srr 0/1 spr 529 ivor33 3 timer/decrementer registers spr 571 mcsrr1 3 spr 530 ivor34 3 spr 574 dsrr0 3 debug srr 0/1 spr 531 ivor35 3 spr 22 dec decrementer spr 575 dsrr1 3 decrementer auto-reload register mmu control and status (read/write) spr 54 decar exception syndrome register spr 62 esr mmu control and status register 0 spr 1012 mmucsr0 3 spr 284 tbl time base lower/upper spr 572 mcsr 3 machine check syndrome register spr 285 tbu spr 624 mas0 3 mmu assist registers 0?7 spr 573 mcar 3 machine check address register spr 625 mas1 3 spr 340 tcr timer control register spr 61 dear data exception address register spr 336 tsr timer status register spr 630 mas6 3 spr 944 mas7 3 miscellaneous registers debug registers spr 48 pid0 process id registers 0?2 spr 272?279 sprg0?7 general sprs 0?7 spr 308?310 dbcr0?2 debug control 0?2 spr 633 pid1 3 hardware implementation dependent 0?1 spr 561 dbcr3 debug control 3 spr 1008 hid0 3 spr 634 pid2 3 spr 1009 hid1 3 spr 304 dbsr debug status register mmu control and status (read only) performance monitor registers spr 312?315 iacs instruction address compare1?4 spr 1015 mmucfg 3 mmu configuration pmr 400 pmgc0 3 global control spr 316?317 dacs data address compare 1?2 spr 688 tlb0cfg 3 tlb configuration 0/1 pmr 16?19 pmc0?3 3 counter registers 0?3 spr 318?319 dvcs data value compare 1?2 spr 689 tlb1cfg 3 pmr 144?147 pmca0?3 3 local control a0?a3 l1 cache (read/write) pmr 272?275 pmcb0?3 3 local control b0?b3 spr 1010 l1csr0 3 l1 cache control/status registers 0/1 spr 1011 l1csr1 3 l1 flush and invalidate control register 0 spr 1015 l1finv0 3 RM0004 register model 50/1176 2.2.1 special-purpose registers (sprs) sprs are on-chip registers that are architecturally part of the processor core. they control the use of the debug facilities, timers, inte rrupts, memory manage ment unit, and other architected processor resources and are accessed with the mtspr and mfspr instructions. unlisted encodings are reserved for future use. ta bl e 7 summarizes sprs defined in book e. the spr numbers are used in the instruction mnemonics. bit 5 in an spr number indicates whether an spr is accessible from user or supervisor software. an mtspr or mfspr instruction that specifies an unsupported spr number is considered an inva lid instruction. invalid instru ctions are treated as follows: if the invalid spr falls within the range spec ified as user mode ( spr[5] = 0), an illegal exception is taken. if supervisor software attempts to access an invalid supervisor-level spr (spr[5] = 1), results are undefined. if user software attempts to access an invalid supervisor-level spr, a privilege exception is taken. table 7. book e special purpose registers (by spr abbreviation) spr abbreviation name defined spr number access supervisor only decimal binary csrr0 critical save/restore register 0 (csrr0) 58 00001 11010 read/write yes csrr1 critical save/restore register 1 (csrr1) 59 00001 11011 read/write yes ctr count register (ctr) 9 00000 01001 read/write no dac1 data address compare registers (dac1?dac2) 316 01001 11100 read/write yes dac2 data address compare registers (dac1?dac2) 317 01001 11101 read/write yes dbcr0 debug control registers (dbcr0?dbcr3) 1 308 01001 10100 read/write yes dbcr1 debug control registers (dbcr0?dbcr3) 2 309 01001 10101 read/write yes dbcr2 debug control registers (dbcr0?dbcr3) 3 310 01001 10110 read/write yes dbsr debug status register (dbsr) 304 01001 10000 read/clear (1) ye s dear data exception address register (dear) 61 00001 11101 read/write yes dec decrementer register 22 00000 10110 read/write yes decar decrementer auto-reload register (decar) 54 00001 10110 write-only yes dvc1 data value compare registers (dvc1 and dvc2) 1 318 01001 11110 read/write yes register model RM0004 51/1176 dvc2 data value compare registers (dvc1 and dvc2) 2 319 01001 11111 read/write yes esr exception syndrome register (esr) 62 00001 11110 read/write yes iac1 iac2 iac3 iac4 instruction address compare registers (iac1?iac4) 312 313 314 315 01001 11000 01001 11001 01001 11010 01001 11011 read/write yes ivor0 interrupt vector offset registers (ivors) critical input 400 01100 10000 read/write yes ivor1 interrupt vector offset registers (ivors) machine check interrupt offset 401 01100 10001 read/write yes ivor10 interrupt vector offset registers (ivors) decrementer interrupt offset 410 01100 11010 read/write yes ivor11 interrupt vector offset registers (ivors) fixed-interval timer interrupt offset 411 01100 11011 read/write yes ivor12 interrupt vector offset registers (ivors) watchdog timer interrupt offset 412 01100 11100 read/write yes ivor13 interrupt vector offset registers (ivors) data tlb error interrupt offset 413 01100 11101 read/write yes ivor14 interrupt vector offset registers (ivors) instruction tlb error interrupt offset 414 01100 11110 read/write yes ivor15 interrupt vector offset registers (ivors) debug interrupt offset 415 01100 11111 read/write yes ivor2 interrupt vector offset registers (ivors) data storage interrupt offset 402 01100 10010 read/write yes ivor3 interrupt vector offset registers (ivors) instruction storage interrupt offset 403 01100 10011 read/write yes table 7. book e special purpose register s (by spr abbreviation) (continued) spr abbreviation name defined spr number access supervisor only decimal binary RM0004 register model 52/1176 ivor4 interrupt vector offset registers (ivors) external input interrupt offset 404 01100 10100 read/write yes ivor5 interrupt vector offset registers (ivors) alignment interrupt offset 405 01100 10101 read/write yes ivor6 interrupt vector offset registers (ivors) program interrupt offset 406 01100 10110 read/write yes ivor7 interrupt vector offset registers (ivors) floating-point unavailable interrupt offset 407 01100 10111 read/write yes ivor8 interrupt vector offset registers (ivors) system call interrupt offset 408 01100 11000 read/write yes ivor9 interrupt vector offset registers (ivors) apu unavailable interrupt offset 409 01100 11001 read/write yes ivpr interrupt vector offset registers (ivors) interrupt vector 63 00001 11111 read/write yes lr link register (lr) 8 00000 01000 read/write no pid process id registers (pid0? pidn) 48 00001 10000 read/write yes pir processor id register (pir) 286 01000 11110 read-only yes pvr processor version register (pvr) 287 01000 11111 read-only yes sprg0 sprg1 sprg2 sprg3 sprg4 sprg5 sprg6 sprg7 software use sprs (sprg0? sprg7 and usprg0) 272 273 274 275 276 277 278 279 01000 10000 01000 10001 01000 10010 01000 10011 01000 10100 01000 10101 01000 10110 01000 10111 read/write yes srr0 save/restore register 0 (srr0) 26 00000 11010 read/write yes srr1 save/restore register 1 (srr1) 27 00000 11011 read/write yes tbl tbu time base (tbu and tbl) 284 285 01000 11100 01000 11101 write-only yes table 7. book e special purpose register s (by spr abbreviation) (continued) spr abbreviation name defined spr number access supervisor only decimal binary register model RM0004 53/1176 ta bl e 8 lists eis-defined sprs. compilers should recognize the mnemonic name given in this table when parsing instructions. tcr timer control register (tcr) 340 01010 10100 read/write yes tsr timer status r egister (tsr) 336 01010 10000 read/clear (2) ye s usprg0 usprg3 usprg4 usprg5 usprg6 usprg7 software use sprs (sprg0? sprg7 and usprg0) (3) 256 259 260 261 262 263 01000 00000 01000 00011 01000 00100 01000 00101 01000 00110 01000 00111 read/write read-only read-only read-only read-only read-only no utbl time base (tbu and tbl) 268 01000 01100 read-only no utbu time base (tbu and tbl) 269 01000 01101 read-only no xer integer exception register (xer) 1 00000 00001 read/write no 1. the dbsr is read using mfspr . it cannot be directly written to. inst ead, dbsr bits corresponding to 1 bits in the gpr can be cleared using mtspr . 2. the tsr is read using mfspr . it cannot be directly written to. inst ead, tsr bits corresponding to 1 bits in the gpr can be cleared using mtspr . 3. user-mode read access to sprg3 is implementation-dependent table 7. book e special purpose register s (by spr abbreviation) (continued) spr abbreviation name defined spr number access supervisor only decimal binary table 8. eis?defined sprs (by spr abbreviation) spr abbreviation name spr number access supervisor only section/page at b l alternate time base lower 526 read-only no section 2.15 on page 123 at b u alternate time base upper 527 read-only no section 2.15 on page 123 dbcr3 debug control register 3 561 read/write yes on page 115 dsrr0 debug save/restore register 0 574 r/w yes on page 86 dsrr1 debug save/restore register 1 575 r/w yes on page 87 hid0 hardware implementation dependent register 0 1008 read/write yes section 2.7.1 on page 71 hid1 hardware implementation dependent register 1 1009 read/write yes section 2.7.2 on page 74 ivor32 spe/embedded floa ting-point apu unavailable interrupt offset 528 read/write yes on page 83 ivor33 embedded floating-point data exception interrupt offset 529 read/write yes on page 83 ivor34 embedded floating-point round exception interrupt offset 530 read/write yes on page 83 RM0004 register model 54/1176 ivor35 performance monitor 531 read/write yes on page 83 ivor36 processor doorbell interrupt. defined by processor signalling apu. 532 read/write yes on page 83 ivor37 processor doorbell critical interrupt. defined by processor signalling apu. 533 read/write yes on page 83 l1cfg0 l1 cache configuration register 0 515 read-only no section 2.11.1 on page 90 l1cfg1 l1 cache configuration register 1 516 read-only no section 2.11.2 on page 92 l1csr0 l1 cache control and status register 0 1010 read/write yes section 2.11.1 on page 90 l1csr1 l1 cache control and status register 1 1011 read/write yes section 2.11.2 on page 92 l1finv0 l1 flush and invalidate control register 0 1016 read/write yes section 2.11.5 on page 96 mas0 mmu assist register 0 624 read/write yes section 2.12.5 on page 101 mas1 mmu assist register 1 625 read/write yes section 2.12.5 on page 101 mas2 mmu assist register 2 626 read/write yes section 2.12.5 on page 101 mas3 mmu assist register 3 627 read/write yes section 2.12.5 on page 101 mas4 mmu assist register 4 628 read/write yes section 2.12.5 on page 101 mas5 mmu assist register 5. 629 read/write yes section 2.12.5 on page 101 mas6 mmu assist register 6 630 read/write yes section 2.12.5 on page 101 mas7 mmu assist register 7 944 read/write yes section 2.12.5 on page 101 mcar machine check address register 573 read-only yes on page 88 mcaru machine check address register upper 569 read-only yes on page 88 mcsr machine check syndrome register 572 read/write yes on page 88 mcsrr0 machine-check save/restore register 0 570 read/write yes on page 87 mcsrr1 machine-check save/restore register 1 571 read/write yes on page 87 mmucfg mmu configuration register 1015 read-only yes section 2.12.3 on page 99 mmucsr0 mmu control and status register 0 1012 read/write yes section 2.12.2 on page 98 table 8. eis?defined sprs (by spr abbreviation) (continued) spr abbreviation name spr number access supervisor only section/page register model RM0004 55/1176 2.3 registers for integer operations the following sections describe registers defined for integer computational instructions. 2.3.1 general purpose registers (gprs) book e implementations provide 32 gprs (gpr0?gpr31) for integer operations. the instruction formats provide 5-bit fields for specifying the gprs to be used in the execution of the instruction. the book e architecture defines 32-bit gprs for 32-bit implementations; however, several apus make use of gprs that are extended to 64 bits to accommodate either vector operands or embedded double-precision floating point operands. the following apus use the extended 64-bit gprs: the signal processing engine (spe) apu and the embedded vector single-precision floating-point apu treat the 64-bit operands as consisting of two, 32-bit elements, as shown in figure 4 . the embedded scalar double-precision floating-point apu treats the gprs as single 64-bit operands that accommodate ieee doub le-precision values. pid0 process id register 0. book e defines only this pid register and refers to as pid, not pid0. 48 read/write yes section 2.12.1 on page 97 pid1 process id register 1 633 read/write yes section 2.12.1 on page 97 pid2 process id register 2 634 read/write yes section 2.12.1 on page 97 spefscr signal processing and embedded floating- point status and control register 512 read/write no section 2.14.1 on page 119 svr system version register 1023 read-only yes section 2.7.5 on page 75 tlb0cfg tlb configuration register 0 688 read-only yes section 2.12.4 on page 100 tlb1cfg tlb configuration register 1 689 read-only yes section 2.12.4 on page 100 table 8. eis?defined sprs (by spr abbreviation) (continued) spr abbreviation name spr number access supervisor only section/page RM0004 register model 56/1176 figure 4. spe and floating point apu gpr usage gray text indicates that the apu does not use this register or register field. formatting of floating-point operands is as defined by ieee 754, as described in the apu chapter of the eref. as shown in figure 4 , the embedded scalar single-precision floating-point apu uses 32-bit operands that, like 32-bit book e instructions, do not affect the upper word of the 64-bit gprs. for 32-bit implementations that implemen t 64-bit gprs, all in structions except spe apu, embedded vector single-precision apu, and embedded scalar double-precision apu instructions use and return 32-bit values in gpr bits 32?63. 2.3.2 integer exception register (xer) bits in the integer exception register (xer) are set based on the operation of an instruction considered as a whole, not on intermediate results. (for example, the subtract from carrying instruction ( subfc ), the result of which is specified as the sum of three values, sets bits in the xer based on the entire operation, not on an intermediate sum.) register model instruction model user-level registers supervisor-level registers computation load/store 0 31 32 63 32 63 brinc evmra evm? evabs evadd? evand? evfsctuiz evcntl? evdiv? evmerge? evsub? logical, rotate, shift, extend, round, select, compare evldh? evldw? evldd? evl?splat? evlwhos? evlwh? evstdd? evstdh? evstdw? evstwh? int/frac int/frac general-purpose registers (gprs) msr[spe] machine state int/frac int/frac interrupt registers int/frac int/frac spr 62 esr[spe] exception syndrome spe apu ?? int/frac int/frac interrupt vector offset registers spr 405 ivor5 alignment acc accumulator spr 528 ivor32 spe/embedded floating-point original spe apu spe/floating-point status/control spr 512 spefscr vector single-precision floating-point apu 0 31 32 63 32 63 efvcf? efvct? efvabs efvadd efvcmp? efvdiv efvmul efvneg efvnabs efvsub efvtst? from spe: evmergehi evmergelo from spe: evldd evlddx evstdd evstddx single-prec. single-prec. general-purpose registers (gprs) 1 msr[spe] machine state single-prec. single-prec. interrupt registers single-prec. single-prec. spr 62 esr[spe] exception syndrome ?? single-prec. single-prec. interrupt vector offset registers spr 405 ivor5 alignment acc accumulator spr 528 ivor32 spe/embedded floating-point spe/floating-point status/control spr 512 spefscr scalar single-precision floating-point apu 0 3 1 32 63 32 63 efscf? efsct? efsabs efsadd efscmp? efsdiv efsmul efsneg efsnabs efssub efstst? uses powerpc uisa 32-bit loads and stores single-prec. general-purpose registers (gprs) 1 msr[spe] machine state single-prec. interrupt registers single-prec. spr 62 esr[spe] exception syndrome ? single-prec. interrupt vector offset registers spr 405 ivor5 alignment acc accumulator spr 528 ivor32 spe/embedded floating-point spe/floating-point status/control spr 512 spefscr scalar double-precision floating-point apu 0 31 32 63 32 63 efdcf? efdct? efdabs efdadd efdcmp? efddiv efdmul efdneg efdnabs efdsub efdtst? from spe: evmergehi evmergelo from spe: evldd evlddx evstdd evstddx double-precision general-purpose registers (gprs) 1 msr[spe] machine state double-precision interrupt registers double-precision spr 62 esr[spe] exception syndrome ? double-precision interrupt vector offset registers spr 405 ivor5 alignment acc accumulator spr 528 ivor32 spe/embedded floating-point spe/floating-point status/control spr 512 spefscr register model RM0004 57/1176 integer exception register (xer) ta bl e 9 describes xer bit definitions. spr1 access: user read-write 32 56 57 63 r so ov ca ? number of bytes w reset all zeros table 9. xer field descriptions bits name description 32 so summary overflow. set when an instruction (except mtspr ) sets the overflow bit (ov). once set, so remains set until it is cleared by mtspr[xer] or mcrxr . so is not altered by compare instructions or by other instructions (except mtspr[xer] and mcrxr ) that cannot overflow. executing mtspr[xer] , supplying the values 0 for so and 1 for ov, causes so to be cleared and ov to be set. 33 ov overflow. x-form add, subtract from, and negate instructions having oe=1 set ov if the carry out of bit 32 is not equal to the carry out of bit 33, and clear ov otherwise to indicate a signed overflow. x-form multiply low word and divide word instructions having oe=1 set ov if the result cannot be represented in 32 bits ( mullwo , divwo , and divwuo ) and clear ov otherwise. ov is not altered by compare instructions or by other instructions (except mtspr[xer] and mcrxr ) that cannot overflow. 34 ca carry. add carrying, subtract from carryi ng, add extended, and subtract from extended instructions set ca if there is a carry out of bi t 32 and clear it otherwise. ca can be used to indicate unsigned overflow for add and subtract operations that set ca. shift right algebraic word instructions set ca if any 1 bits are shifted out of a negative operand and clear ca otherwise. compare instructions and instructions that cannot carry (except shift right algebraic word, mtspr[xer] , and mcrxr ) do not affect ca. 35?56 ? reserved, should be cleared. 57?63 no. of bytes supports emulation of load and store string inst ructions. specifies the number of bytes to be transferred by a load string indexed or store string indexed instruction. RM0004 register model 58/1176 2.4 registers for floating-point operations this section details floating-point registers and their field descriptions. 2.4.1 floating-point registers (fprs) book e defines 32 floating-point registers (fpr0?fpr31). floating-point instruction formats provide 5-bit fields for specifying fprs used in instruction execution. each fpr contains 64 bits that support the floating-point format. instructions that interpret fpr contents as floating-point values use doub le-precision format for this interpretation. the computational instructions and the move and select instructions operate on data in fprs and, except for compare instructions, place the result into an fpr, and optionally place status information into the cr. load and store double instructions are provided that transfer 64 bits of data between memory and the fprs with no conversion. load single instructions are provided to transfer and convert floating-point values in floating-point single format from memory to the same value in floating-point double format in the fprs. store single instructions are provided to transfer and convert floating-point values in floating-point double format from the fprs to the same value in floating-point single format in memory. instructions are provided that manipulate the fpscr and the cr explicitly. some of these instructions copy data between an fpr and the fpscr. the computational instructions and the select instruction acce pt values from the fprs in double format. for single-precision arithmet ic instructions, all input values must be representable in single format; if they are not, the result placed into the target fpr, and the setting of status bits in the fpscr and in the cr (if rc = 1), are undefined. 2.4.2 floating-point status and control r egister (fpscr) the fpscr, shown below, controls how floating-point exceptions are handled and records status resulting from floating-point operati ons. fpscr[32?55] are status bits; fpscr[56? 63] are control bits. floating-point status and control register (fpscr ) access: user read/write 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 r fx fex vx ox ux zx xx vxsnan vxisi vxidi vxzdz vximz vxvc fr fi c w reset all zeros 48 51 52 53 54 55 56 57 58 59 60 61 62 63 r fpcc ? vxsoft vxsqrt vxcvi ve oe ue ze xe ni rn w reset all zeros register model RM0004 59/1176 the exception bits, fpscr[35?45,53?55], are sticky; once set they remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0 . exception summary bits fpscr[fx,fex,vx] are not considered to be exception bits, and only fx is sticky. fex and vx are simply the ors of other fpscr bits, and so are not listed among the fpscr bits affected by the various instructions. fpscr fields are described in ta bl e 1 0 . table 10. fpscr field descriptions bits name description 32 fx floating-point exception summary. every floating-point instruction, except mtfsfi and mtfsf , implicitly sets fx if that instru ction causes any of the floating-point exception bits in the fpscr to change from 0 to 1. mcrfs , mtfsfi, mtfsf, mtfsb0 , and mtfsb1 can alter fpscr[fx] explicitly. 33 fex floating-point enabled exception summary. fex is the or of all the floating-point exception bits masked by their respective enable bits. mcrfs , mtfsfi , mtfsf , mtfsb0 , and mtfsb1 cannot alter fpscr[fex] explicitly. 34 vx floating-point invalid operation exception summary. vx is the or of all the invalid operation exception bits. mcrfs , mtfsfi , mtfsf , mtfsb0 , and mtfsb1 cannot alter fpscr[vx] explicitly. 35 ox floating-point overflow exception 36 ux floating-point underflow exception 37 zx floating-point zero divide exception 38 xx floating-point inexact exception. fpscr[xx] is a sticky version of fpscr[fi] (see below). thus the following rules completely describe how fpscr[xx] is set by a given instruction: if the instruction affects fpscr[fi], the new fpscr[xx] value is obtained by oring the old value of fpscr[xx] with the new value of fpscr[fi]. if the instruction does not af fect fpscr[fi], the value of fpscr[xx] is unchanged. 39 vxsnan floating-point invalid operation exception (snan) 40 vxisi floating-point invalid operation exception ( ? ) 41 vxidi floating-point invalid operation exception ( ) 42 vxzdz floating-point invalid operation exception (0 0) 43 vximz floating-point invalid operation exception ( 0 ) 44 vxvc floating-point invalid operation exception (invalid compare). 45 fr floating-point fraction rounded. the last arithmetic or rounding and conversion instruction incremented the fraction during ro unding. this bit is not sticky. 46 fi floating-point fraction inexact. the last arithmetic or rounding and conversion instruction either produced an inexact result during rounding or caused a disabled overflow exception. this bit is not sticky. the definition of fpscr[xx] describes the relationship between fpscr[fi] and fpscr[xx]. 47? 51 fprf floating-point result flags. set as described below in ta bl e 1 0 . for arithmetic, rounding, and conversion instructions, fprf is set based on t he result placed into the target register, except that if any portion of the result is undef ined, the value placed into fprf is undefined. 47 c floating-point result class descriptor. arithmetic , rounding, and conversion instructions may set this bit with the fpcc bits, to indicate the class of the result. RM0004 register model 60/1176 48? 51 fpcc floating-point condition code. floating-point compar e instructions set one of the fpcc bits and clear the other three fpcc bits. arithmetic, rou nding, and conversion instructions may set the fpcc bits with the c bit to indicate the class of the result. in this case, the three high-order fpcc bits retain their relational significance indicating that the value is less t han, greater than, or equal to zero. 48floating-point less than or negative (fl or <) 49floating-point greater th an or positive (fg or >) 50floating-point equal or zero (fe or =) 51floating-point unordered or nan (fu or ?) 52 ? reserved, should be cleared. 53 vxsoft floating-point invalid operation exception (software request). can be altered only by mcrfs , mtfsfi , mtfsf , mtfsb0 , or mtfsb1 . 54 vxsqrt floating-point invalid operation exception (invalid square root). note that vxsqrt is defined even for implementat ions that do not support either of the two optional instructions that set it, fsqrt [ . ] and frsqrte [ . ]. defining it for all implementations gives software a standard interface for handling square root exceptions. if an implementation does not support fsqrt [ . ] or frsqrte [ . ], software can simulate the instru ction and set vxsqrt to reflect the exception. 55 vxcvi floating-point invalid operation exception (invalid integer convert) 56 ve floating-point invalid operation exception enable 57 oe floating-point overflow exception enable 58 ue floating-point underflow exception enable 59 ze floating-point zero divide exception enable 60 xe floating-point inexact exception enable 61 ni floating-point non-ieee mo de. if ni = 1, the remaining fpscr bits may have meanings other than those given in this document and results of floating-point operations need not conform to the ieee standard. if the ieee-conf orming result of a floating- point operation would be a denormalized number, the result of that operatio n is 0 (with the same sign as the denormalized number) if fpscr[ni] = 1 and other requirement s specified in the user?s manual for the implementation are met. the other effects of setting ni may differ among implementations. setting ni is intended to permit results to be approximate and to cause performance to be more predictable and less data-dependent than when ni = 0. for example, in non-ieee mode, an implementation returns 0 instead of a denormalized number and may return a large number instead of an infinity. in non-ieee mode an implementation should provide a means for ensuring that all results are produced without software assistance (that is, without causing an enabled exception type program interrupt or a floating- point unimplemented instruction exception type program interrupt and without invoking an emulation assist). the means may be controlled by one or more other fpscr bits (recall that the other fpscr bits have implementation-dependent meanings if ni = 1). 62? 63 rn floating-point rounding control (rn). 00round to nearest 01round toward zero 10round toward +infinity 11round toward ?infinity table 10. fpscr field descriptions (continued) bits name description register model RM0004 61/1176 ta bl e 1 1 describes floating-point result flags. 2.5 registers for branch operations this section describes registers used by book e branch and cr operations. 2.5.1 condition register (cr) the 32-bit cr reflects the result of certain operations and provides a mechanism for testing and branching. condition register (cr) cr bits are grouped into eight 4-bit fields, cr0?cr7, which are set as follows: specified cr fields can be set by a move to the cr from a gpr ( mtcrf ). a specified cr field can be set by a move to the cr from another cr field ( mcrf ), from the fpscr ( mcrfs ), or from the xer ( mcrxr ). cr0 can be set as the implicit re sult of an inte ger instruction. cr1 can be set as the implicit resu lt of a floating-point instruction. a specified cr field can be set as the result of either an integer or a floating-point compare instruction (including spe and spfp compare instructions). instructions are provided to perform logical operations on individual cr bits and to test individual cr bits (see condition register instructions on page 204 ? ). note that instructions that access cr bits (for example, branch conditional ( bc ), cr logicals, and move to condition register field ( mtcrf )) determine the bit position by adding table 11. floating-point result flags result flags result value class c<>=? 10001quiet nan 01001?infinity 01000?normalized number 11000?denormalized number 10010?zero 00010+zero 10100+denormalized number 00100+normalized number 00101+infinity access: user read/write 32 35 36 39 40 43 44 47 48 51 52 55 56 59 60 63 r cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 w reset all zeros RM0004 register model 62/1176 32 to the operand value. for example, in conditional branch instructions, the bi operand accesses bit bi + 32, as shown in ta bl e 1 2 . table 12. bi operand settings for cr fields cr n bits cr bits bi description cr0[0] 32 00000 negative (lt)?set when the result is negative. for spe compare and te st instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. cr0[1] 33 00001 positive (gt)?set when the result is positive (and not zero). for spe compare and te st instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise. cr0[2] 34 00010 zero (eq)?set when the result is zero. for spe compare and te st instructions: set to the or of the result of the compare of the high and low elements. cr0[3] 35 00011 summary overflow (so). copy of xer[so] at the instruction?s completion. for spe compare and test instructions: set to the and of the result of the compare of the high and low elements. cr1[0] 36 00100 copy of fpscr[fx] at the instru ction?s completion. negative (lt) for spe and spfp compare a nd test instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. cr1[1] 37 00101 copy of fpscr[fex] at the instru ction?s completion. positive (gt) for spe and spfp compare a nd test instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise. cr1[2] 38 00110 copy of fpscr[vx] at the inst ruction?s completion. zero (eq) for spe and spfp compare a nd test instructions: set to the or of the result of the compare of the high and low elements. cr1[3] 39 00111 copy of fpscr[ox] at the instruction?s completion. summary overflow (so) for spe and spfp compare a nd test instructions: set to the and of the result of the compare of the high and low elements. cr n [0] 40 44 48 52 56 60 01000 01100 10000 10100 11000 11100 less than or floating-point less than (lt, fl). for integer compare instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). for floating-point compare instructions: fr a < fr b. for spe and spfp compare a nd test instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. register model RM0004 63/1176 cr setting for integer instructions for all integer word instructions in which the rc bit is defined and set, and for addic. , andi. , and andis. , cr0[32?34] are set by signed comparison of bits 32?63 of the result to zero; cr[35] is copied from the final state of xer[so]. the rc bit is not defined for double-word integer operations. if (target_register) 32?63 < 0 then c 0b100 else if (target_register) 32?63 > 0 then c 0b010 else c 0b001 cr0 c || xer so the value of any undefined portion of the result is undefined, and the value placed into the first three bits of cr0 is undefined. cr 0 bits are interpreted as described in ta b l e 1 3 . note that cr0 may not reflect the true (infinitely precise) result if overflow occurs. cr n [1] 41 45 49 53 57 61 01001 01101 10001 10101 11001 11101 greater than or floating-point greater than (gt, fg). for integer compare instructions: r a > simm or r b (signed comparison) or r a > uimm or r b (unsigned comparison). for floating-point compare instructions: fr a > fr b. for spe and spfp compare a nd test instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise. cr n [2] 42 46 50 54 58 62 01010 01110 10010 10110 11010 11110 equal or floating-point equal (eq, fe). for integer compare instructions: r a = simm, uimm, or r b. for floating-point compare instructions: fr a = fr b. for spe and spfp compare a nd test instructions: set to the or of the result of the compare of the high and low elements. cr n [3] 43 47 51 55 59 63 01011 01111 10011 10111 11011 11111 summary overflow or floating-point unordered (so, fu). for integer compare instructio ns, this is a copy of xer[so] at the completion of the instruction. for floating-point compare in structions, one or both of fr a and fr b is a nan. for spe and spfp vector compar e and test instructions: set to the and of the result of the compare of the high and low elements. table 12. bi operand settings for cr fields (continued) cr n bits cr bits bi description table 13. cr0 bit descriptions cr bit name description 32 negative (lt) bit 32 of the result is equal to one. 33 positive (gt) bit 32 of the result is equal to zero, and at least one of bits 33?63 of the result is non- zero. 34 zero (eq) bits 32?63 of the result are equal to zero. 35 summary overflow (so) this is a copy of the final state of xer [so] at the completion of the instruction. RM0004 register model 64/1176 cr setting for store conditional instructions cr0 is also set by the integer store conditional instruction, stwcx. . see instruction descriptions in chapter 3 ,? for detailed description s of how cr0 is set. cr setting for floating-point instructions for all floating-point instructions in which the rc bit is defined and set, cr1 (cr[36?39]) is copied from fpscr[32?35]. these bits are interpreted as shown in ta b l e 1 4 . cr setting for compare instructions for compare instructions, a cr field specified by th e bi field in the instruction is set to reflect the result of the comparison, as shown in ta b l e 1 5 . table 14. cr setting for floating-point instructions bit name description 36 fx floating-point exception summary. copy of final state of fpscr[ fx] at instruction completion. 37 fex floating-point enabled exception summary. copy of final state of fpscr[fex] at instruction completion. 38 vx floating-point invalid operation exception summary. copy of final state of fpscr[vx] at completion. 39 ox floating-point overflow exception. copy of final state of fpscr[ox] at instruction completion. table 15. cr setting for compare instructions cr n bit bit expression cr bits bi description aim (bi operand) book e 0?2 3?4 cr n [0] 4 * cr0 + lt (or lt ) 4 * cr1 + lt 4 * cr2 + lt 4 * cr3+ lt 4 * cr4 + lt 4 * cr5 + lt 4 * cr6 + lt 4 * cr7 + lt 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 000 001 010 011 100 101 110 111 00 less than or floating-point less than (lt, fl). for integer compar e instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). for floating-point compare instructions: fra < frb. cr n [1] 4 * cr0 + gt (or gt ) 4 * cr1 + gt 4 * cr2 + gt 4 * cr3+ gt 4 * cr4 + gt 4 * cr5 + gt 4 * cr6 + gt 4 * cr7 + gt 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 000 001 010 011 100 101 110 111 01 greater than or floating- point greater than (gt, fg). for integer compar e instructions: ra > simm or rb (signed comparison) or r a > uimm or r b (unsigned comparison). for floating-point compare instructions: fra > frb. register model RM0004 65/1176 cr bit settings in vle mode the vle extension implements the entire cr, but some comparison operations and all branch instructions are limited to using cr0? cr3. however, all book e cr field and logical operations are provided. cr bits are grouped into eight 4-bit fields, cr0?cr7, which are set in one of the following ways. specified cr fields can be set by a move to the cr from a gpr ( mtcrf ). a specified cr field can be set by a move to the cr from another cr field ( e_mcrf ). cr field 0 can be set as the implicit result of an integer instruction. a specified cr field can be set as the result of an integer compare instruction. cr field 0 can be set as the result of an integer bit test instruction. instructions are provided to perform logical operations on individual cr bits and to test individual cr bits. cr settings for integer instructions for all integer word instructions in which the rc bit is defined and set, and for addic. , the first three bits of cr field 0 (cr[32?34]) are se t by signed comparison of bits 32?63 of the result to zero, and the fourth bit of cr field 0 (cr[35]) is copied from the final state of xer[so]. if (target_register) 32:63 < 0 then c 0b100 else if (target_register) 32:63 > 0 then c 0b010 else c 0b001 cr0 c || xer so cr n [2] 4 * cr0 + eq (or eq ) 4 * cr1 + eq 4 * cr2 + eq 4 * cr3+ eq 4 * cr4 + eq 4 * cr5 + eq 4 * cr6 + eq 4 * cr7 + eq 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 000 001 010 011 100 101 110 111 10 equal or floating-point equal (eq, fe). for integer compar e instructions: r a = simm, uimm, or r b. for floating-point compare instructions: fra = frb. cr n [3] 4 * cr0 + so/un (or so/un ) 4 * cr1 + so /un 4 * cr2 + so /un 4 * cr3 + so /un 4 * cr4 + so/un 4 * cr5 + so/un 4 * cr6 + so/un 4 * cr7 + so/un 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 000 001 010 011 100 101 110 111 11 summary overflow or floating-point unordered (so, fu). for integer compare instru ctions, this is a copy of xer[so] at instruction completion. for floating-point compare instructions, one or both of fra and frb is a nan. table 15. cr setting for compare instructions (continued) cr n bit bit expression cr bits bi description aim (bi operand) book e 0?2 3?4 RM0004 register model 66/1176 if any portion of the result is undefined, the value placed into the first three bits of cr field 0 is undefined. the bits of cr field 0 are interpreted as shown in ta bl e 1 6 . cr setting for compare instructions supported by the vle extension for compare instructions, a cr field specified by the cr d operand in the instruction for the e_cmph , e_cmphl , e_cmpi , and e_cmpli instructions, or cr0 for the e_cmp16i , e_cmph16i , e_cmphl16i , e_cmpl16i , se_cmp , se_cmph , se_cmphl , se_cmpi , and se_cmpli instructions is set to reflect the result of the comparison. the cr field bits are interpreted as shown in ta b l e 1 7 . a complete description of how the bits are set is given in chapter 6 ,? and in integer instructions on page 205 .? cr setting for the vle bit test instruction the bit test immediate instruction, se_btsti , also sets cr field 0. see the instruction description and also integer instructions on page 205 2.5.2 link register (lr) the link register can be used to provide the branch target address for a branch conditional to lr ( bclr x ) instruction, and it holds the return address after branch and link instructions. table 16. cr0 encodings cr bit description 32 negative (lt). bit 32 of the result is equal to 1. 33 positive (gt). bit 32 of the result is equal to 0 and at least one of bits 33?63 of the result is non-zero. 34 zero (eq). bits 32?63 of the result are equal to 0. 35 summary overflow (so). this is a copy of th e final state xer[so] at the completion of the instruction. table 17. condition register setting for compare instructions cr bit description 4 crd + 32 less than (lt). for signed-integer compare, gpr( r a or r x) < sci8 or si or gpr( r b or r y). for unsigned-integer compare, gpr( r a or r x) < u sci8 or ui or ui5 or gpr( r b or r y). 4 crd + 33 greater than (gt). fo r signed-integer compare, gpr( r a or r x) > sci8 or si or ui5 or gpr( r b or r y). for unsigned-integer compare, gpr( r a or r x) > u sci8 or ui or ui5 or gpr( r b or r y). 4 crd + 34 equal (eq). for integer compare, gpr( r a or r x) = sci8 or ui5 or si or ui or gpr( r b or r y). 4 crd + 35 summary overflow (so). for integer com pare, this is a copy of the final state of xer[so] at the completion of the instruction. register model RM0004 67/1176 link register (lr) the lr contents are read into a gpr using mfspr . the contents of a gpr can be written to the lr using mtspr . lr[62?63] are ignored by bclr instructions. link register usage in vle mode vle instructions use the lr as defined in book e, although the vle extension defines a subset of all variants of book e conditional branches involving the lr, as shown in ta bl e 1 8 . note that because vle instructions can reside on half-word boundaries, in vle mode, lr[30] is examined when the lr holds an instruction address. 2.5.3 count register (ctr) ctr can be used to hold a loop count that can be decremented and tested during execution of branch instructions that contain an appropriately encoded bo field. if the ctr value is 0 before being decremented, it is ?1 afterward. the entire ctr can be used to hold the branch target address for a branch conditional to ctr ( bcctr x ) instruction. note that because vle instructions can reside on half-word boundaries, in vle mode, ctr[30] is examined when the ct r holds an instruction address. count register (ctr) spr 8 access: user read/write 32 63 r link address w reset all zeros table 18. branch to link register instruction comparison book e vle subset instruction syntax instruction syntax branch conditional to link register branch conditional to link register & link bclr bo , bi bclrl bo , bi branch (absolute) to link register branch (absolute) to link register & link se_blr se_blrl branch conditional & link e_bcl bo , bi , bd branch conditional & link e_bcl bo32 , bi32 , bd 15 branch (absolute) & link e_bl bd24 se_bl bd8 spr 9 access: user read/write 32 63 r count value w reset all zeros RM0004 register model 68/1176 count register usage in vle mode vle instructions use the ctr as defined by in book e, although the vle extension defines a subset of the variants of book e conditional branches involving the ctr, as shown in ta bl e 1 9 . 2.6 processor control registers this section addresses machine state, processor id, and processor version registers. 2.6.1 machine stat e register (msr) the msr defines the state of the processor (that is, enabling and disabling of interrupts and debugging exceptions, enabling and disabling of address translation for instruction and data memory accesses, enabling and disabling some apus, and specifying whether the processor is in supervisor or user mode). msr contents are automatically saved, altered, and restored by the interrupt-handling mechanism. if a non-critical interrupt is taken, msr contents are automatically copied into srr1. if a critical interrupt is taken, msr contents are automatically copied into csrr1. when an rfi or rfci is executed, msr contents are restored from srr1 or csrr1. the eis-defined machine check apu defines additional save/restore resources. when a machine check interrupt is taken, mcsrr0 and mcsrr1 hold the return address and msr information. the return from mach ine check interrup t instruction, rfmci , restores mcsrr1 contents to the msr. msr contents are read into a gpr using mfmsr . the contents of a gpr can be written to msr using mtmsr . the write msr external enable instructions ( wrtee and wrteei ) can be used to set or clear msr[ee] without affecting other msr bits. machine state register (msr) table 19. branch to count register instruction comparison book e vle instruction syntax instruction syntax branch conditional to count register branch conditional to count register & link bcctr bo , bi bcctrl bo , bi branch (absolute) to count register branch (absolute) to count register & link se_bctr se_bctrl access: supervisor-only 32 36 37 38 39 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 book e/ eis r ? ap we ce ? ee pr fp me fe0 ? de fe1 ? is ds ? w eis apus r ? ucle spe ? pmm ? w reset all zeros register model RM0004 69/1176 table 20. msr field descriptions bits name description 32? 36 ? reserved, should be cleared. (1) 37 ucle (cache-locking apu) user-mode cache lock enable. used to restrict user-mode cache-line locking by the operating system. 0any cache lock instruction executed in user-mode takes a cache-locking dsi exception and sets either esr[dlk] or esr[ilk]. this allows the operating system to manage and track the locking/unlocking of cache lines by user-mode tasks. 1cache-locking instructions can be executed in user-mode and they do not take a dsi for cache-locking. (they may still take a dsi for access violations though.) 38 spe (spe, spfp, dpfp apus) spe enable. enables use of 64-bit extended gprs used by spe, single-precision vector, and double-precision floating-point apus/ 0if software attempts to execute an spe apu instruction, the spe apu unavailable exception is taken. 1software can execute any of the spe apu instructions. embedded floating-point instructions require msr[spe] to be set. an attempt to execute an embedded floating-point instruct ion when msr[spe] is 0 results in an spe apu unavailable interrupt. 39? 43 ? reserved, should be cleared. 1 44 ap apu available. book e defines the operation of ap as follows: 0the processor cannot execute apu instructions. 1the processor can execute apu instructions. 45 we wait state enable. allows the core complex to signal a request for power management, according to the states of hid0[doze], hid0[nap], and hid0[sleep]. 0the processor is not in wait state and continues processing. no power management request is signaled to external logic. 1the processor enters wait state by ceasing to execute instructions and entering low-power mode. details of how wait st ate is entered and exited and how the processor behaves in the wait state are implementation-dependent. 46 ce critical enable 0critical input and watchdog timer interrupts are disabled. 1critical input and watchdog timer interrupts are enabled. 47 ? preserved for book iii ile 48 ee external enable 0external input, decrementer, fixed-interval timer, and performance monitor interrupts are disabled. 1external input, decrementer, fixed-interval timer, and performance monitor interrupts are enabled. 49 pr user mode (problem state) 0the processor is in supervisor mode, can execute any instruction, and can access any resource (for example, gprs, sprs, and the msr). 1the processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged resource. pr also affects memo ry access control. RM0004 register model 70/1176 the floating-point exception mode bits fe0 and fe1 are described in ta bl e 2 1 . 50 fp floating-point available. 0the processor cannot execute floating-point instructions, including floating-point loads, stores, and moves. 1the processor can execute floating-point instructions. 51 me machine check enable. 0machine check interrupts are disabled. 1machine check interrupts are enabled. 52 fe0 floating-point exception mode 0. the book e definition of this bit is shown in register model RM0004 71/1176 2.7 hardware implementation-dependent registers each st book e processor implements hardware implementation-dependent registers, hid0 and hid1,which contain fields defined either by the eis or by the implementation. this section provides architectural information about hid registers and describes only those bits that are defined by the eis. note: 1 not all processors implement hid fields defined by the eis. consult the user documentation. 2 an integrated device may not use all hid fields implemented on an embedded core or may define those fields more specifically. always begin by looking at the core register descriptions in the reference manual for the integrated device. 2.7.1 hardware implementatio n dependent regist er 0 (hid0) hid0 is used for configuration and control. figure below shows the hid0 bits that are defined either generally by the eis or as part of an eis-defined apu. note that not all eis- compliant device implement all hid0 fields; see the user documentation. writing to hid0 typica lly requires synchroniza tion, as described in chapter 2.18.2 .? hardware implementation dependent register 0 (hid0) hid0 fields are described in ta b l e 2 2 . table 21. floating-point exception bits?msr[fe0,fe1] fe0 fe1 mode 0 0 ignore exceptions 0 1 imprecise nonrecoverable 1 0 imprecise recoverable 11precise spr 1008 access: supervisor-only 32 33 34 35 39 40 42 43 47 r emcp ? pwrmgmt dpm edpm ? ipr en_mas7_ update w reset all zeros 48 49 50 51 55 56 57 58 62 63 r eiec tben sel_tbclk ? dapuen sge ? eieio_en lwsync_en ? noptst nopdst nopti w reset all zeros RM0004 register model 72/1176 table 22. hid0 field descriptions bits name description 32 emcp enable machine check pin. used to mask machine check exceptions delivered to the core from the machine check input. 0machine check exceptions from the machine check signal are disabled. 1machine check exceptions from the ma chine check signal are enabled. if msr[me] = 0, asserting the machine signal check causes a checkstop. if msr[me] = 1, asserting the machine check signal causes a machine check exception. 33 ? implementation dependent. 34 sfr sixty-four bit results. determines how t he upper 32 bits of 64-bit registers in a 64-bit implementation are computed when the processor is executing in 32-bit mode (msr[cm] = 0). 0in 32-bit mode, bits 0?31 of all 64-bit registers are not modified. explicit 64- bit instructions generate an unimplemented instruction exception when executed. 1in 32-bit mode, bits 0?31 are written wit h the same value that is written as when the processor is executing in 64-bit mode (except for the lr and any eas generated that clear bits 0?31. explic it 64-bit instructions are allowed to execute and do not generate an unimple mented instruction exception unless they would have when the processor is in 64-bit mode. 35? 39 ? implementation dependent. 40? 42 pwrmgmt power management control. t he semantics of pwrmgmt are implementation dependent. 43 dpm dynamic power management. used to en able power-saving by shutting off functional resources not in use. setting or clearing dpm should not affect performance. 0dynamic power management is disabled. 1dynamic power management is enabled. 44 edpm enhanced dynamic power management. used to enable additional power- saving by shutting off functional resources not in use. setting edpm may have adverse effects on performance. 0enhanced dynamic power management is disabled. 1enhanced dynamic power management is enabled. 45 ? implementation dependent. 46 icr interrupt inputs clear reservation. controls whether external input and critical input interrupts cause an established reservation to be cleared. 0external and critical input interrupts do not affect reservation status. 1external and critical input interrupts, when taken, clear an established reservation. 47 en_mas7_up date enable hot-wire update of mas7 register. implementations that support this bit do not update mas7 (upper rpn field) when hardware writes mas registers via a tlbre , tlbsx , or an interrupt unless this bit is set. this provides a compatibility path for processors that originally offered only 32 bits of physical addressing but have since extended past 32 bits. 0hardware updates of mas7 are disabled. 1hardware updates of mas7 are enabled. register model RM0004 73/1176 48 eiec enable internal error checking. used to control whether internal processor errors cause a machine check exception. 0 internal error reporting is disabled. internally detected processor errors do not generate a machine check interrupt. 1 internal error reporting is enabled. internally detected processor errors generate a machine check interrupt. 49 tben time base enable. used to control whether the time base increments. 0 the time base is not enabled and will not increment. 1 the time base is enabled and will increment. the rate at which the time base increments is determined by the value of hid0[sel_tbclk]. 50 sel_tbclk select time base clock. used to sele ct the source of the time base clock. 0 the time base is updated based on a core implementation specific rate. 1 the time base is updated based on an external signal to the core 51? 54 ? implementation dependent. 55 dapuen debug apu enable. controls whether the debug apu or enhanced debug apu is enabled. 0 the debug apu is disabled. debug interrupts use csrr0 and csrr1 to save state and the rfci instruction to return from the debug interrupt. 1 the debug apu is enabled; debug interrupts use dsrr0 and dsrr1 to save state and the rfdi instruction to return from the debug interrupt. 56 sge store gathering enable. turns on store gathering for non-guarded cache inhibited or write-through stores. deta ils and characteristics of how stores are gathered is implementation dependent. 0 store gathering is disabled. 1 store gathering is enabled. 57 ? implementation dependent. 58 eieio_en eieio synchronization enable. allows mbar instructions to provide the same synchronization semantics as the eieio instruction. 0 synchronization provided by mbar is performed in the book e manner. additional forms of synchronization, if implemented, are determined by the mo value. 1 synchronization provided by mbar is equivalent to eieio synchronization. the mo field is ignored. 59 lwsync_en lightweight synchronization enable. allows msync instructions to provide the same synchr onization semantics as the sync instructions from the powerpc 2.xx architecture. 0 the synchronization provided by the msync instruction is performed in the book e manner. 1 the synchronization provided by the msync instruction is based on the l field defined in powerpc 2.xx architecture sync instruction. 60 ? implementation dependent. table 22. hid0 field descriptions bits name description RM0004 register model 74/1176 2.7.2 hardware implementatio n dependent regist er 1 (hid1) the eis defines a hid1 register. hid1 contents are implementation dependent. hid1 is used for bus configuration and control. writing to hid1 requires synchronization, as described in chapter 2.18.2: synchronization requirements for sprs .? hardware implementation dependent register 1 (hid1) 2.7.3 processor id register (pir) the processor id register (pir), shown belo w, contains a value that can be used to distinguish the processor from other processors in the system. processor id register (pir) 61 noptst no-op cache touch for store instructions. controls whether data cache touch for store instructions perform no operation. 0 dcbtst , dstst , and dststt and other forms of cache touch for store instructions operate as defined by the eis and book e unless disabled by nopdst or nopti. 1 dcbtst , dstst , and dststt and other forms of cache touch for store instructions are treated as no-ops. cache line touch for store and lock instructions defined in the cache line locking apu operate as defined. 62 nopdst no-op dst , dstt , dstst , and dststt instructions. instructions that start data stream prefetching through the dst instructions produce no-operation. 0 dst , dstt , dstst , and dststt operate as defined by the eis unless disabled by noptst or nopti. 1 dst , dstt , dstst , and dststt are treated as no-ops and all current dst prefetch streams are terminated. 63 nopti no-op cache touch instructions. data and instruction cache touch instructions perform no operations. 0 dcbt , dcbtst , icbt and other forms of cache touch instructions operate as defined by the eis and book e unle ss disabled by nopdst or noptst. 1 dcbt , dcbtst , icbt and other cache touch instruction forms are treated as no-ops. cache line touch and lock instructions defined in the cache line locking apu operate as defined. table 22. hid0 field descriptions bits name description spr 1009 access: supervisor-only 32 63 r implementation dependent w reset implementation dependent spr 286 access: supervisor read-only 32 63 r processor id w reset processor specific value register model RM0004 75/1176 2.7.4 processor versi on register (pvr) the read-only processor version register (pvr), contains a value identifying the version and revision level of the processor. the pvr distinguishes between processors that differ in attributes that may affect software. processor version register (pvr) ta bl e 2 3 describes pvr fields. 2.7.5 system version register (svr) the system version register (svr), contains a read-only soc-dependent value; consult the documentation for the implementation. system version register (svr) 2.8 timer registers the time base (tb), decrementer (dec), fixed-interval timer (fit), and watchdog timer provide timing functions for the system. the re lationship of these timer facilities to each other is shown in figure 5 and is described as follows: spr 287 access: supervisor read-only 32 47 48 63 r version revision w reset processor specific value table 23. pvr field descriptions bits name description 32? 47 version a 16-bit number that identifies the version of the processor. different version numbers indicate major differences between processors, such as which optional facilities and instruct ions are supported. 48? 63 revisio n a 16-bit number that distinguishes betw een implementations of the version. different revision numbers indicate minor differences between processors having the same version number, such as clock rate and engineering change level. spr 1023 access: supervisor read-only 32 63 r system version w reset soc-specific value RM0004 register model 76/1176 figure 5. relationship of timer facilities to the time base the tb is a long-period counter driven at an implementation-dependent frequency. the decrementer, updated at the same rate as the tb, provides a way to signal an exception after a specified period unless one of the following occurs: ? dec is altered by software in the interim. ? the tb update frequency changes. the dec is typically used as a general-purpose software timer. the time base for the tb and dec is selected by the time base enable (tben) and select time base clock (sel_tbc lk) bits in hid0, as follows: ? if hid0[tben] = 1 and hid0[sel_tbclk] = 0, the time base is updated every 8 bus clocks. ? if hid0[tben] = 1 and hid0[sel_tbclk] = 1, the time base is updated by an implementation-specific clock input). software can select one from of four tb bits to signal a fixed-interval interrupt whenever the bit transitions from 0 to 1. it is typically used to trigger periodic system maintenance functions. bits that may be selected are implementation-dependent. the watchdog timer, also a selected tb bit, provides a way to signal a critical exception when the selected bit transitions from 0 to 1. it is typically used for system error recovery. if software does not respond in time to the initial interrupt by clearing the associated status bits in the tsr before the next expiration of the watchdog timer interval, a watchdog timer-generated processor reset may result, if so enabled. all timer facilities must be initialized during start-up. 2.8.1 timer control register (tcr) the tcr, provides control information for the on-chip timer of the core complex. the core complex implements two fiel ds not specified in book e: tcr[wpext] and tcr[fpext]. the 32-bit timer control register (tcr), controls the decrementer. (see chapter 2.8.4 . ) timer clock time base (incrementer) decrementer event = 0/1 detect 63 decar 32 auto-reload 63 32 tbl 63 32 tbu watchdog timer events based on one of the tb bits selected by the eis? defined tcr[wpext] concatenated with the book e?defined tcr[wp] fixed-interval timer events based on one of tb bits selected by the eis? defined tcr[fpext] concatenated with the book e?defined tcr[fp] dec ? ? ? ? ? ? (time base clock) core_tbclk register model RM0004 77/1176 timer control register (tcr) ta bl e 2 4 describes the tcr fields. spr 340 access: su pervisor read/write 32 33 34 35 36 37 38 39 40 41 42 43 46 47 50 51 63 r wp wrc wiedie fp fieare ? wpext fpext ? w reset processor specific value table 24. tcr field descriptions bits name description 32? 33 wp watchdog timer period. wh en concatenated with wpext, s pecifies one of 64-bit locations of the time base used to signal a watchdog timer exception on a transition from 0 to 1. wpext,wp = 0000_00 selects tbu[32] (the msb of the tb) wpext,wp = 1111_11 selects tbl[63] (the lsb of the tb) 34? 35 wrc watchdog timer reset control. when a watchdog reset event occurs, the value programmed into wrc is reflected on core_wrs and into tsr[wrs], but the wrc bits are reset to 00. at this point, software can reprogram wrc. although wrc can be set by software, it cannot be cleared by soft ware (except by a software-induced reset). once written to a non-zero value, wrc may no longer be altered by software. 00no watchdog timer reset will occur. tcr[wrc] resets to 00; it can be set by software, but cannot be cleared by software (except by a software-induced reset). xx other values: force processor to be reset on second time-out of watchdog timer. the exact function of any of these settings is impl ementation-dependent. 36 wie watchdog timer interrupt enable 0watchdog timer interrupts disabled 1watchdog timer interrupts enabled 37 die decrementer interrupt enable 0 decrementer interrupts disabled 1 decrementer interrupts enabled 38? 39 fp fixed interval timer period. when concatenated with fpext, fp specifies one of 64 bit locations of the time base used to signal a fixed-interval timer exception on a transition from 0 to 1. fpext||fp = 0000_00 selects tbu[ 32] (the msb of the tb) fpext||fp = 1111_11 selects tbl[63] (the lsb of the tb) 40 fie fixed interval interrupt enable 0 fixed interval interrupts disabled 1 fixed interval interrupts enabled 41 are auto-reload enable. controls whether the value in decar is reloaded into the dec when the dec value reaches 0000_0001. 0 auto-reload disabled 1 auto-reload enabled 42 ? reserved, should be cleared. 43? 46 wpe xt (eis) watchdog timer period extension (see the description for wp) RM0004 register model 78/1176 2.8.2 timer status register (tsr) as shown below, the 32-bit tsr contains status on timer events and the most recent watchdog timer-initiated processor reset. all tsr bits function as write-1-to-clear. note: register fields designated as write-1-to-clear are cleared only by writing ones to them. writing zeros to them has no effect. timer status register (tsr) ta bl e 2 5 describes tsr fields. 47? 50 fpex t (eis) fixed-interval timer period extension (see the description for fp) 51? 63 ? reserved, should be cleared. table 24. tcr field descriptions (continued) bits name description spr 336 336 access: supervisor w1c 32 33 34 35 36 37 38 63 r enw wis wrs dis fis ? w w1c w1c w1c w1c w1c reset all zeros table 25. tsr field descriptions bits name description 32 enw enable next watchdog time. when a watchdog timer time-out occurs while wis = 0 and the next watchdog time-out is enabled (enw = 1), a watchdog timer exception is generated and logged by setting wis. this is referred to as a watchdog timer first time out. a watchdog timer interrupt occurs if enabled by tcr[wie] and msr[ce]. to avoid another watchdog timer interrupt once msr[ce] is reenabled (assuming tcr[wie] is not cleared instead), the interrupt handler must reset tsr[wis] by executing an mtspr , setting wis and any other bits to be cleared and a 0 in all other bits. the data written to the tsr is not di rect data, but a mask. a 1 causes the bit to be cleared; a 0 has no effect. 0 action on next watchdog timer time-out is to set tsr[enw]. 1 action on next watchdog timer time-out is governed by tsr[wis]. 33 wis watchdog timer interrupt status. see the enw desc ription for more information about how wis is used. 0 a watchdog timer event has not occurred. 1 a watchdog timer event occurred. when msr[ce] = 1 and tcr[wie] = 1, a watchdog timer interrupt is taken. 34?35 wrs watchdog timer reset status. defined at reset (val ue = 00). set to tcr[wrc] when a reset is caused by the watchdog timer. 00 no watchdog timer reset has occurred. xx all other values are implementation-dependent. register model RM0004 79/1176 2.8.3 time base (tbu and tbl) the time base (tb), seen below, is composed of two 32-bit registers, the time base upper (tbu) concatenated on the right with the time base lower (tbl). tb provides timing functions for the system. tb is a volatile resource and must be initialized during start-up. time base upper/lower registers (tbu/tbl) the tb is interpreted as a 64-bit unsigned integer that is incremented periodically. each increment adds 1 to the least-significant bit. t he frequency at which the integer is updated is implementation-dependent. tbl increments until its value becomes 0xffff_ffff (2 32 ? 1). at the next increment, its value becomes 0x0000_0000 and tbu is incremented. this process continues until the tbu value becomes 0xffff_ffff and value tbl value becomes 0xffff_ffff (tb is interpreted as 0xffff_ffff_ffff_ffff (2 64 ? 1)). at the next increment, the tbu value becomes 0x0000_0000 and the tbl value becomes 0x0000_0000. there is no interrupt (or any other indication) when this occurs. the period depends on the driving frequency. for example, if tb is driven by 100 mhz divided by 32, the tb period is as follows: (approximately 187,000 years) the tb is implemented such that the following requirements are satisfied: loading a gpr from the tb has no effect on the accuracy of the tb. storing a gpr to the tb replaces the value in the tb with the value in the gpr. book e does not specify a relationship between the frequency at which the tb is updated and other frequencies, such as the cpu clock or bus clock in a book e system. the tb 36 dis decrementer interrupt status. 0 a decrementer event has not occurred. 1 a decrementer event occurred. when msr[ee] = tcr[die] = 1, a decrementer interrupt is taken. 37 fis fixed-interval timer interrupt status. 0 a fixed-interval timer event has not occurred. 1 a fixed-interval timer event occurred. when msr[ee] = 1 and tcr[fie ]= 1, a fixed-interval timer interrupt is taken. 38?63 ? reserved, should be cleared. table 25. tsr field descriptions (continued) bits name description spr 269 read/285 write 268 read/284 write a ccess: user read supervisor write 32 63 32 63 r tbu tbu w reset all zeros t tb 2 64 32 10mhz ------------------- - 5.90 10 12 seconds == RM0004 register model 80/1176 update frequency is not required to be constant. one of the following is required to ensure that system software can keep time of day and operate interval timers: the system provides an (implementation-dependent) interrupt to software whenever the update frequency of the tb changes and a way to determine the current update frequency. the update frequency of the tb is under the control of system software. note: 1 disabling the tb or making reading the time base privileged prevents the tb from being used to implement a covert channel in a secure system. 2 if the operating system initializes the tb on power-on to some reasonable value and the update frequency of the tb is constant, the tb can be used as a source of values that increase at a constant rate, such as for time stamps in trace entries. even if the update frequency is not constant, values read from the tb are monotonically increasing (except when the tb wraps from 2 64 ? 1 to 0). if a trace entry is recorded each time the update frequency changes, the sequence of tb values can be post-processed to become actual time values. successive readings of the tb may return identical values. it is intended that the tb be useful for ti ming reasonably short sequences of code (a few hundred instructions) and for low-overhead time stamps for tracing. 2.8.4 decrementer register the 32-bit decrementer (dec), shown below, is a decrementing counter that is updated at the same rate as the tb. it provides a way to signal a decrementer interrupt after a specified period unless one of the following occurs: dec is altered by software in the interim. the tb update frequency changes. dec is typically used as a general-purpose software timer. the decrementer auto-reload register is used to automatically reload a programmed value into dec, as described in section 2.8.5: decrementer auto-reload register (decar) .? decrementer register (dec) 2.8.5 decrementer auto-r eload register (decar) the decrementer auto-reload register is shown in figure below. if the auto-reload function is enabled (tcr[are] = 1), the auto-reload val ue in decar is written to dec when dec decrements from 0x0000_0001 to 0x0000_0000. note that writing dec with zeros by using an mtspr[dec] does not automatically generate a decrementer exception. spr 22 2 access: supervisor read/write 32 63 r decrementer value w reset all zeros register model RM0004 81/1176 decrementer auto-reload register (decar) 2.9 interrupt registers chapter 2.9.1: interrupt registers defined by book e on page 81 ,? describes registers used for interrupt handling. 2.9.1 interrupt regist ers defined by book e this section describes the following register bits and their fields: save/restore register 0 (srr0) on page 81 ? save/restore register 1 (srr1) on page 81 ? critical save/restore register 0 (csrr0) on page 82 ? critical save/restore register 1 (csrr1) on page 82 ? data exception address register (dear) on page 82 ? interrupt vector prefix register (ivpr) on page 83 ? interrupt vector offset registers (ivors) on page 83 ? exception syndrome register (esr) on page 84 ? save/restore register 0 (srr0) on a noncritical interrupt, srr0, shown in figure below, holds the address of the instruction where the interrupted process should resume. the instruction is interrupt-specific, although for instruction-caused exceptions, it is typically the address of the instruction that caused the interrupt. when rfi executes, instruction execution continues at the address in srr0. save/restore register 0 (srr0) save/restore register 1 (srr1) srr1 is provided to save and restore machine state on noncritical interrupts. when a noncritical interrupt is taken, msr contents are placed in srr1. when rfi executes, srr1 contents are placed into msr. srr1 bits that correspond to reserved msr bits are also reserved. these registers are not affected by rfci or rfmci . reserved msr bits may be altered by rfi , rfci , or rfmci . spr 54 4 access: supervisor write-only 32 63 r w decrementer auto-reload value reset all zeros spr 26 2 6 access: sup[ervisor read/write 32 63 r next instruction address w reset all zeros RM0004 register model 82/1176 save/restore register 1 (srr1) critical save/restore register 0 (csrr0) csrr0, is provided to save and restore machine state on critical interrupts. it is used by critical interrupts like srr0 is used for standard interrupts: to hold the address of the instruction to which control is passed at the end of the interrupt handler. when rfci executes, instruction execution continues at the address in csrr0. critical save/restore register 0 (csrr0) critical save/restore register 1 (csrr1) csrr1, is used to save and restore machine state on critical interrupts. when a critical interrupt is taken, msr contents are placed into csrr1. when rfci executes, csrr1 contents are restored into the msr. csrr1 bits that correspond to reserved msr bits are also reserved; reserved msr bits may be altered. critical save/restore register 1 (csrr1) data exception address register (dear) dear, is loaded with the effective address of a data access (caused by a load, store, or cache management instruction) that results in an alignment, data tlb miss, or dsi exception. data exception address register (dear) spr 27 7 access: supervisor read/write 32 63 r msr state information w reset all zeros spr 58 7 access: supervisor read/write 32 63 r next instruction address w reset all zeros spr 59 7 access: supervisor read/write 32 63 r msr state information w reset all zeros spr 61 7 access: supervisor read/write 32 63 r exception address w reset all zeros register model RM0004 83/1176 . interrupt vector prefix register (ivpr) ivpr is used with ivors to determine the vect or address. ivpr[32?47] provides the high- order 16 bits of the address of the exception processing routines. the 16-bit vector offsets are concatenated to the right of ivpr[32?47] to form the address of the exception processing routine. ivpr[48?63] are reserved. interrupt vector prefix register (ivpr) interrupt vector offset registers (ivors) ivors, hold the quad-word index from the base address provided by the ivpr for each interrupt type. interrupt vector offset registers (ivor) spr numbers corresponding to ivor16?ivor31 are reserved. ivor32?ivor47 and ivor60?ivor63 are reserved. spr numbers for ivor32?ivor63 are allocated for implementation-dependent use. ivor assignments are shown in ta bl e 2 6 . spr 63 7 access: supervisor read/write 32 47 48 63 r interrupt vector prefix ? w reset all zeros spr (see ta b l e 2 6 ) access: supervisor read/write 32 47 48 59 60 63 r ? interrupt vector prefix ? w reset all zeros table 26. ivor assignments ivor number spr interrupt type ivor0 400 critical input ivor1 401 machine check ivor2 402 data storage ivor3 403 instruction storage ivor4 404 external input ivor5 405 alignment ivor6 406 program ivor7 407 floating-point unavailable ivor8 408 system call ivor9 409 auxiliary processor unavailable (optional) ivor10 410 decrementer RM0004 register model 84/1176 exception syndrome register (esr) the esr, provides a syndrome to differentiate between different kinds of exceptions that can generate the same interrupt type. when such an interrupt is generated, bits corresponding to the specific exception that generated the interrupt are set and all other esr bits are cleared. other interrupt types do not affect esr contents. the esr does not need to be cleared by software. ta b l e 2 7 shows esr bit definitions. eis storage defines esr[dlk] and esr[ilk] to indicate user cache line locking exceptions, esr[xte] for precise external transaction errors, and esr[epid] external pid load and store exceptions. the esr is defined in book e. bits architected by eis storage are defined here. exception syndrome register (esr) ta bl e 2 7 describes esr bit definitions. ivor11 411 fixed-interval timer interrupt ivor12 412 watchdog timer interrupt ivor13 413 data tlb error ivor14 414 instruction tlb error ivor15 415 debug ivor16? ivor31 ? reserved for future architectural use ivor36?ivor63 allocated for implementation dependent use ivor32 528 spe apu unavailable ivor33 529 (embedded fp apus) embedded floating-point data exception ivor34 530 (embedded fp apus) embedded floating-point round exception ivor35 531 (performance monitor apus) performance monitor table 26. ivor assignments (continued) ivor number spr interrupt type spr62 access: supervisor read/write 32 35 36 37 38 39 40 41 42 43 44 45 46 47 55 56 57 58 59 61 62 63 book e r ? pil ppr ptr fp st ? dlk0 dlk1 ap puo bo ? w eis r ? dlk ilk ? spe ? vlemi ? mif xte w reset all zeros table 27. exception syndrome register (esr) definition bits name syndrome interrupt types 32?35 ? reserved, should be cleared. (d efined by book e as allocated.) ? 36 pil illegal instruction exception program 37 ppr privileged instruction exception program register model RM0004 85/1176 38 ptr trap exception program 39 fp floating-point operations alignment, data storage, data tlb, program 40 st store operation alignment, data storage, data tlb error 41 ? reserved, should be cleared. ? 42 dlk defined by cache line locking apu. instruction cache locking attempt. set when a dsi occurs because a dcbtls , dcbtstls , or dcblc was executed in user mode (msr[pr ] = 1) while msr[ucle] = 0. 0default 1 dsi occurred on an attempt to lock line in data cache when msr[ucle] = 0. data storage 43 ilk defined by cache line locking apu. instruction cache locking attempt. set when a dsi occurs because an icbtls or icblc was executed in user mode (msr[pr] = 1) while msr[ucle] = 0. 0default 1 dsi occurred on an attempt to lock line in instruction cache when msr[ucle] = 0. data storage 44 apu auxiliary processor operation. de fined by book e. alignment, data storage, data tlb, program 45 puo unimplemented operation exception. defined by book e. program 46 bo byte-ordering exception. defined by b ook e and the vle extension. data storage, instruction storage 47 pie imprecise exception. defined by book e. program 48?55 ? reserved. ? 56 spe defined by spe, embedded floating-point apu. spe/embedded floating-point exception bit 0default 1 any exception caused by an spe/embedded floating-point instruction occurred. data storage, data tlb error, alignment, spe unavailable, embedded fp unavailable, embedded fp data, embedded fp round 57 ? reserved, should be cleared table 27. exception syndrome register (esr) definition (continued) bits name syndrome interrupt types RM0004 register model 86/1176 note: esr information is incomplete, so system software may need to identify the type of instruction that caused the interrupt and examine the tlb entry and the esr to fully identify the exception or exceptions. for example, a data storage interrupt may be caused by both a protection violation exception and a byte-ordering exception. system software would have to look beyond esr[bo], such as the state of msr[pr] in srr1 and the tlb entry page protection bits to determine if a protection violation also occurred. eis-defined interrupt registers this section describes machine chec k save/store and syndrome registers. debug save/restore register 0 (dsrr0) on a debug interrupt, dsrr0, holds the address of the instruction where the interrupted process should resume. the instru ction is interrup t specific. see chapter 4.7.16: debug interrupt on page 271 .? when rfdi executes, instruction execution continues at the address in dsrr0. dsrr0 and dsrr1 are not affected by rfi , rfci , or other return from interrupt instructions 58 vlemi defined by vle extension. vlemi indicates that an interrupt was caused by a vle instruction. vlemi is set on an exception associated with execution or attempted ex ecution of a vle instruction. 0 the instruction page associated with the instruction causing the exception does not have the vle attribute set or the vle extension is not implemented. 1 the instruction page associated with the instruction causing the exception has the vle attribute set and the vle extension is implemented. data storage, data tlb error, instruction storage, program, system call, alignment, spe unavailable, embedded fp unavailable, embedded fp data, embedded fp round 59?61 ? reserved. defined by book e as allocated. ? 62 mif defined by the vle extension. mif indicates that an interrupt was caused by a misaligned instruction fetch (nia 62 != 0) and the vle attribute is cleared for the page or the second half of a 32-bit vle instruction caused an instruction tlb error. 0default. 1nia 62 != 0 and the instruction page associated with nia does not have the vle attribute set or the second half of a 32-bit vle instruction caused an instruction tlb error. instruction tlb error, instruction storage 63 xte external transaction error. an external transaction reported an error but the error was handled precisely by the core. the contents of srr0 contain the address of the instruct ion that initiated the transaction. 0 default. no external transaction error was precisely detected. 1 an external transaction reported an error that was precisely detected. instruction storage, data storage table 27. exception syndrome register (esr) definition (continued) bits name syndrome interrupt types register model RM0004 87/1176 debug save/restore register 0 (dsrr0) debug save/restore register 1 (dsrr1) dsrr1, is provided to save and restore machine state on debug interrupts. when a debug interrupt is taken, msr contents are placed into dsrr1. when rfdi executes, the contents of dsrr1 are restored into msr. dsrr1 bits that correspond to reserved msr bits are also reserved. (see section 2.6.1: machine state register (msr) ,? for more information.) dsrr0 and dsrr1 are not affected by rfi or rfci . reserved msr bits may be altered by rfi , rfci , or rfdi . debug save/restore register 1 (dsrr1) machine check save/restore register 0 (mcsrr0) when a machine check interrupt is taken, mcsrr0, is set to the address of the instruction where the interrupted process should resume. the instruction is interrupt-specific, although typically mcsrr0 holds address of the instruction that caused the interrupt. when rfmci is executed, instruction execution continues at this address. machine check save/restore register 0 (mcsrr0) machine check save/restore register 1 (mcsrr1) mcsrr1 is used to save and restore machine state on machine check interrupts. when a machine check interrupt is taken, msr contents are placed into mcsrr1. when rfmci executes, mcsrr1 contents are restored to msr. mcsrr1 bits that correspond to reserved msr bits are also reserved; reserved msr bits may be altered. spr 574 5 74 access: supervisor read/write 32 63 r next instruction address w reset undefined spr 575 5 74 access: supervisor read/write 32 63 r msr state information w reset implementation-specific spr 570 5 74 access: supervisor read/write 32 63 r next instruction address w reset all zeros RM0004 register model 88/1176 machine check save/restore register 1 (mcsrr1) machine check address register (mcar/mcaru) when the core complex takes a machine check interrupt, it updates mcar, to indicate the address of the data associated with the machine check. note that if a machine check interrupt is caused by a signal, mcar content s are not meaningful. errors that cause mcar contents to be updated are implementation-dependent. if mcsr[mav] = 1, the address is an effective address; if mav = 0, the address is a real address. machine check address register (mcar/mcaru) for 32-bit implementations that support physical addresses greater than 32 bits, mcaru provides an alias to the upper address bits that reside in mcar[0?31]. machine check syndrome register (mcsr) the mcsr, is used to record the cause of the machine check interrupt. in general, machine check syndrome bits correlating to specific hardware error conditions are implementation dependent. consult the users manual for a complete definition of machine check error syndromes for a specific processor. machine check syndrome register 1 (mcsr) ta bl e 2 8 describes the mcsr fields. spr 571 5 74 access: supervisor read/write 32 63 r msr state information w reset all zeros spr mcar: 573 mcaru: 569 access: supervisor read-only mcaru 32 6332 63 r machine check address 0?31 machine check address 32?63 w reset all zeros spr 572 5 74 access: read/w1c 32 43 44 45 46 47 63 r mcp ? nmi mav mea ? w reset all zeros register model RM0004 89/1176 note: the machine check interrupt handler should always write what is read back to the mcsr after the error information has been logged. writing contents that were read from the mcsr back to the mcsr clears only those status bits that were previously read. failure to clear all mcsr bits causes an asynchronous machine check interrupt when msr[me] is set. 2.10 software use sprs (s prg0?sprg7 and usprg0) software-use sprs (sprg0?sprg7 and usprg0), have no defined functionality. these are shown below: sprg0?sprg2?can be accessed only in supervisor mode. sprg3?can be written only in supervisor mode. it is readable in supervisor mode, but whether it can be read in user mode is implementation-dependent. sprg4?sprg7?can be written only in supervisor mode; readable in supervisor or user mode. usprg0?can be accessed in supervisor or user mode. table 28. mcsr field descriptions bits name description 32 mcp machine check input to core. processor core s with a machine check input pin (signal) respond to a signal input by producing an asynchronous machine check. the existence of such a signal and how such a signal is generated is implementation dependent and may be tied to a an external pin on the ic package. 33? 42 ? implementation-dependent. 43 nmi nonmaskable interrupt. set if a non-maskable interrupt (nmi) has been sent to the virtual processor. 44 mav mcar address valid. the address contained in mcar was updated by the processor and corresponds to the first detected er ror condition that contained an associated address. any subsequent machine check er rors that have associated addresses are not placed in mcar unless mav is 0 when the error is logged. 0 the address in mcar is not valid. 1 the address in mcar is valid. note: software should read mcar before clearing mav. mav should be cleared before setting msr[me]. 45 mea mcar effective address. denotes the type of address in mcar. mea has meaning only if mcsr[mav] is set. 0 the address in mcar is a physical address. 1 the address in mcar is an effective address (untranslated). 46? 63 ? implementation-dependent. RM0004 register model 90/1176 software-use sprs (sprg0?sprg7 and usprg0) software-use sprs are read into a gpr by using mfspr and are written by using mtspr . 2.11 l1 cache registers the eis defines registers that provide control and configuration and status information for the l1 cache implementation. 2.11.1 l1 cache control and stat us register 0 (l1csr0) the l1csr0, is defined by the eis. it is used for general control and status of the l1 data cache. l1 cache control and status register 0 (l1csr0) ta bl e 2 9 describes the l1csr0 fields. spr sprg0 sprg1 sprg2 sprg3 sprg4 sprg5 sprg6 sprg7 usprg0 272 273 274 259 275 260 276 261 277 262 278 263 279 256 read/write read/write read/write read-only read/write read-only read/write read-only read/write read-only read/write read-only read/write read/write supervisor supervisor supervisor user (implementation-dependent)/supervisor supervisor user/supervisor supervisor user/supervisor supervisor user/supervisor supervisor user/supervisor supervisor user/supervisor 32 63 r msr state information w reset all zeros spr 1010 supervisor read/write cache way partitioning apu bits 32 35 36 39 40 41 42 43 46 47 r wid wdd awid awdd wam ? cpe w reset all zeros cache line locking apu bits 48 49 51 52 53 54 55 56 57 60 61 62 63 r cpi ? cslc cul clo clfr cloa ? cabt cfi ce w reset all zeros register model RM0004 91/1176 table 29. l1csr0 field descriptions bits name description 32?35 wid cache way partitioning apu. way instruction disable. (bit 32 = way 0, bit 33 = way 1, ? bit 35 = way 3). 0 the corresponding way is available for replacement by instruction miss line refills. 1 the corresponding way is not available for replacement by instruction miss line refills. 36?39 wdd cache way partitioning apu. way data disable (bit 36 = way 0, bit 37 = way 1, ? bit 39 = way 3). 0 the corresponding way is available for replacement by data miss line refills. 1 the corresponding way is not available for replacement by data miss line refills 40 awid cache way partitioning apu. additional ways instruction disable. 0 additional ways beyond 0?3 are available for replacement by instruction miss line fills. 1 additional ways beyond 0?3 are not available for replacement by instruction miss line fills. 41 awdd cache way partitioning apu. additional ways data disable. 0 additional ways beyond 0?3 are available for replacement by data miss line fills. 1 additional ways beyond 0?3 are not available for replacement by data miss line fills. 42 wam cache way partitioning apu. way access mode. 0 all ways are available for access. 1 only ways partitioned for the specific type of access are used for a fetch or read operation. 43-46 ? reserved for implementation dependent use. 47 cpe dcpe [data] cache parity enable. 0 parity checking of the cache disabled 1 parity checking of the cache enabled 48 cpi dcpi [data] cache parity error injection enable. 0 parity error injection disabled 1 parity error injection enabled. note that cache parity must also be enabled (l1csr0[cpe] = 1) when this bit is set. if dcpe is not set, results are undefined and erratic behavior may occur. it is recommended that an attempt to set this bit when l1csr0[cpe] = 0 cause the bit not to be set (that is, l1csr0[cpi] = l1csr0[cpe] & l1csr0[cpi]). 49?51 ? reserved, should be cleared. 52 cslc dcslc [data]cache snoop lock clear. sticky bit set by hardware if a cache line lock was cleared by a snoop operation which caused an invalidation. note that the lock for that line is cleared whenever the line is invalidated. this bit can be cleared only by software. 0 the cache has not encountered a sn oop that invalidated a locked line. 1 the cache has encountered a snoop that invalidated a locked line. 53 cul dcul [data]cache unable to lock. sticky bit set by hardware. this bit can be cleared only by software. 0 indicates a lock set instructi on was effective in the cache 1 indicates a lock set instruction was not effective in the cache 54 clo dclo [data]cache lock overflow. sticky bit set by hardware. this bit can be cleared only by software. 0 indicates a lock overflow condition was not encountered in the cache 1 indicates a lock overflow condition was encountered in the cache RM0004 register model 92/1176 2.11.2 l1 cache control and stat us register 1 (l1csr1) l1csr1, defined as part of the eis, is used for general control and status of the l1 instruction cache. l1 cache control and status register 1 (l1csr1) ta bl e 3 0 describes the l1csr1 fields. 55 clfc dclfc [data]cache lock bits flash clear. clearing occurs regardless of the enable (l1csr0[ce]) value. 0 default. 1 hardware initiates a cache lock bits flash clear operation. cleared when the operation is complete. during a flash clear operation, writing a 1 causes undefined results; writing a 0 has no effect 56 cloa dcloa [data]cache lock overflow allocate. set by software to allow a lock request to replace a locked line when a lock overflow situation exists . implementation of this bit is optional. 0 indicates a lock overflow condition does not replace an existing locked line with the requested line 1 indicates a lock overflow condition replaces an existing locked line with the requested line 57?60 ? reserved, should be cleared. 61 cabt dcabt [data]cache operation aborted. 0 no cache operation completed improperly 1 cache operation did not complete properly 62 cfi dcfi [data]cache flash invalidate. invalidation occurs regardless of the enable (l1csr0[ce]) value. 0 no cache invalidate. 1 cache flash invalidate operation. a cache invalidation operation is initiated by hardware. once complete, this bit is cleared. during an invalidation operation, writing a 1 caus es undefined results; writing a 0 has no effect. 63 ce dce [data]cache enable. 0 the cache is not enabled. (not accessed or updated) 1 enables cache operation. table 29. l1csr0 field descriptions (continued) bits name description spr 1011 011 access: supervisor read/write cache line locking apu fields 32 46 47 48 49 51 52 53 54 55 56 57 60 61 62 63 r ? icpe icpi ? icslc icul iclo iclfr icloa ? icabt icfi ice w reset all zeros register model RM0004 93/1176 table 30. l1csr1 field descriptions bits name description 32?42 ? reserved, should be cleared. 43-46 ? reserved for implementation dependent use. 47 icpe instruction cache parity enable. see chapter 4.7.2: machine check interrupt .? 0 parity checking of the cache disabled 1 parity checking of the cache enabled 48 icpi instruction cache parity error injection enable. 0 parity error injection disabled 1 parity error injection enabled. note that cache parity must also be enabled (l1csr1[icpe] = 1) when icpi is set. if l1csr0[icpe] is not set th e results are undefined and erratic behavior may occur. it is recommended that an attempt to set this bit when l1csr0[icpe] = 0 causes the bit not to be set (that is, l1csr0[icpi] = l1csr0[icpe] & l1csr0[icpi]). 49?51 ? reserved, should be cleared. 52 icslc cache line locking apu. instruction cache snoop lock clear. sticky bit set by hardware if a cache line lock was cleared by a snoop operation that caused an invalidation. note that the lock for that line is cleared whenever the line is invalidated. this bit can be cleared only by software. 0 the cache has not encountered a snoop that invalidated a locked line. 1 the cache has encountered a snoop that invalidated a locked line. 53 icul cache line locking apu. instruction cache unable to lock. sticky bit set by hardware. this bit can be cleared only by software. 0 indicates a lock set instruction was effective in the cache 1 indicates a lock set instructio n was not effective in the cache 54 iclo dclo cache line locking apu. instruction cache lock overflow. sticky bit set by hardware. this bit can be cleared only by software. 0 indicates a lock overflow condition was not encountered in the cache 1 indicates a lock overflow condition was encountered in the cache 55 iclfc cache line locking apu. instruction cache lock bits flash clear. clearing occurs regardless of the enable (l1csr1[ice]) value. 0 default. 1 hardware initiates a cache lock bits flash clear operation. this bit is cleared when the operation is complete. during a flash clear operation, writing a 1 caus es undefined results; writing a 0 has no effect. 56 icloa cache line locking apu. instruction cache lock overflow no allocate. set by software to prevent a lock request from replacing a locked line when a lo ck overflow situation exists. implementation of this bit is optional. 0 indicates a lock overflow condition replaces an existing locked line with the requested line 1 indicates a lock overflow condition does not replace an existing locked line with the requested line 57?60 ? reserved, should be cleared. 61 icabt instruction cache operation aborted. 0 no cache operation completed improperly 1 cache operation did not complete properly RM0004 register model 94/1176 2.11.3 l1 cache configurati on register 0 (l1cfg0) the l1cfg0 register, shown below, is defined by the eis to provide configuration information for the primary (l1) data cache of the processor. if a processor implements a unified cache, l1cfg0 applies to the unified cache and l1cfg1 is not implemented. l1 cache configuration register 0 (l1cfg0) 62 icfi instruction cache flash invalidate. invalidation occurs regardless of the enable (l1csr1[ice]) value. 0 no cache invalidate. 1 cache flash invalidate operation. a cache invalid ation operation is initiated by hardware. once complete, this bit is cleared. during an invalidation operation, writing a 1 causes undefined results; writing a 0 has no effect. 63 ice instruction cache enable. 0 the cache is not enabled. (not accessed or updated) 1 enables cache operation. table 30. l1csr1 field descriptions (continued) bits name description spr 515 access: user read-only 32 33 34 35 36 37 38 39 40 41 42 43 44 45 52 63 r carch cwpa cfaha cfiswa ? cbsize crepl cla cpa cnway csize w reset implementation-dependent value table 31. l1cfg0 field descriptions bits name description 32?33 carch cache architecture 00 harvard 01 unified 34 cwpa cache way partitioning apu available. 0 unavailable 1 available 35 cfaha cache flush all by hardware available 0 unavailable 1 available 36 cfiswa direct cache flush apu available. (cache flush by set and way available.) 0 unavailable 1 available 37?38 ? reserved, should be cleared. register model RM0004 95/1176 2.11.4 l1 cache configurati on register 1 (l1cfg1) the l1cfg1 register, provides configuration information for the l1 instruction cache. if a processor implements a unified cache, l1cfg0 applies to the unified cache and l1cfg1 is not implemented. l1 cache configuration register 1 (l1cfg1) 39?40 cbsize cache line size 0032 bytes 0164 bytes 10128 bytes 11reserved 41?42 crepl cache replacement policy 00 true lru 01 pseudo lru 1x reserved 43 cla cache line locking apu available 0 unavailable 1 available 44 cpa cache parity available 0 unavailable 1 available 45?52 cnway cache number of ways minus 1. 53?63 csize cache size in kbytes. table 31. l1cfg0 field descriptions (continued) bits name description spr 516 access: user read-only 32 38 39 40 41 42 43 44 45 52 53 63 r ? icbsize icrepl icla icpa icnway icsize w reset implementation-dependent value table 32. l1cfg1 field descriptions bits name description 32?38 ? reserved, should be cleared. 39?40 icbsiz instruction cache block size 0032 bytes 0164 bytes 10128 bytes 11reserved RM0004 register model 96/1176 2.11.5 l1 flush and invalidate c ontrol register 0 (l1finv0) the direct cache flush apu defines the l1 flush and invalidate control register 0 (l1finv0), shown in figure below. the direct cache flush apu allows the programmer to flush and/or invalidate the cache by specifying the cache se t and cache way. the direct cache flush apu available bit, l1cfg0[cfiswa], is set for implementations that contain the direct cache flush apu. to address a specific physical block of the ca che, the l1finv0 is written with the cache set (l1finv0[cset]) and cache way (l1finv0[cway]) of the line that is to be flushed. no tag match in the cache is required. only the l1 data cache (or unified cache) is manipulated by the direct cache flush apu. the l1 instruction cache or any other caches in the cache hierarchy are not explicitly targeted by this apu. see chapter 8.2: direct cache flush apu on page 850 .? l1 flush and invalidate control register 0 (l1finv0) 41?42 icrepl cache replacement policy 00true lru 01pseudo lru 1xreserved 43 icla cache line locking apu available 0unavailable 1available 44 icpa cache parity available 0unavailable 1available 45?52 icnway cache number of ways minus 1. 53?63 icsize cache size in kbytes. table 32. l1cfg1 field descriptions (continued) bits name description spr 1016 access: su pervisor read/write 32 39 40 41 42 58 59 61 62 63 r cway ? cset ? ccmd w reset all zeros table 33. l1finv0 fields?l1 direct cache flush bits name descriptions 0?31 ? reserved, should be cleared. 32?39 cway cache way. specifies the cache way to be selected. 40?41 ? reserved, should be cleared. 42?58 cset cache set. specifies the cache set to be selected. register model RM0004 97/1176 2.12 mmu registers this section describes the following mmu registers and their fields: process id registers (pid0?pid2) mmu control and status register 0 (mmucsr0) mmu configuration register (mmucfg) tlb configuration registers (tlb n cfg) mmu assist registers (mas0?mas7) 2.12.1 process id re gisters (pid0?pid n ) the book e architecture specifies that a process id (pid) value be associated with each effective address (instruction or data) generated by the processor. system software uses pids to identify tlb entries that the processor uses to translate addresses for loads, stores, and instruction fetches. pid contents are compared to the tid field in tlb entries as part of selecting appropriate tlb entries for address translation. pid values are used to construct virtual addresses for accessing memory. note that individual processors may not implement all 14 bits of the process id field. book e defines one pid register that holds the pid value for the current process. st devices may implement from 1 to 15 pid registers. the number of pids implemented is indicated by the value of mmucfg[npids]. consult the user documentation for the implementation to determine if other pid registers are implemented. the suggested pid usage is for pid0 to denote private mappings for a process and for other pids to handle mappings that may be common to multiple processes. this method allows for processes sharing address space to also share tlb entries if the shared space is mapped at the same virtual address in each process. 59?61 ? reserved, should be cleared. 62?63 ccmd cache flush command. 00implementation dependent. if implement ed, the action performed on the line should be synonymous with a dcbi instruction that references the same line. 01the line specified by cway and cset is flus hed if it is modified and valid. it is implementation dependent whether it remains in the cache, or is invalidated. for an implementation, the action performed on the line should be synonymous with a dcbst instruction that references the same line. 01the line specified by cway and cset is flus hed if it is modified and valid. it is then invalidated. for an implementation, th e action performed on the line should be synonymous with a dcbf instruction that references that line. 11reserved for future use. table 33. l1finv0 fields?l1 direct cache flush bits name descriptions RM0004 register model 98/1176 process id registers (pid0?pid2) 2.12.2 mmu control and stat us register 0 (mmucsr0) the mmucsr0 register is used for general control of the l1 and l2 mmus. mmu control and status register 0 (mmucsr0) spr 48 (pid0: pid in book e); spr 633 pid1 spr 634 pid2 (pid3?pid14 are current ly not assigned to spr numbers) access: supervisor-only 32 49 50 63 r ? process id w reset all zeros spr 1012 access: su pervisor read/write 32 60 61 62 63 r ? tlb0_fi tlb1_fi ? w reset all zeros table 34. mmucsr0 field descriptions bits name description 32?60 ? reserved, should be cleared. 61 l2tlb0_fi tlb0_fi tlb0 flash invalidate (write 1 to invalidate) 0 no flash invalidate. writing a 0 to this bit during an invalidation operation is ignored. 1 tlb0 invalidation operation. hardware initiate s a tlb0 invalidation operation. when this operation is complete, this bit is cleared. wr iting a 1 during an invalidation operation causes an undefined operation. if the tlb array supports iprot, entries that have iprot set are not invalidated. 62 l2tlb1_fi tlb1_fi tlb1 flash invalidate (write 1 to invalidate) 0 no flash invalidate. writing a 0 to this bit during an invalidation operation is ignored. 1 tlb1 invalidation operation. hardware initiate s a tlb1 invalidation operation. when this operation is complete, this bit is cleared. wr iting a 1 during an invalidation operation causes an undefined operati on. this invalidation typically takes 1 cycle. 63 ? reserved, should be cleared. register model RM0004 99/1176 2.12.3 mmu configurati on register (mmucfg) mmucfg, shown below, gives configuration information about the implementation?s mmu. mmu configuration register 1 (mmucfg) spr 1015 access: supervisor read-only 32 48 49 52 53 57 58 59 60 61 62 63 r? npids pidsize ? ntlbs mavn w reset implementation specific table 35. mmucfg field descriptions bits name description 32?48 ? reserved, should be cleared. 49?52 npids number of pid registers, a 4-bit field t hat indicates the number of pid registers provided by the processor. 53?57 pidsiz e pid register size. the pidsize value is one fewer than the number of bits in each pid register implemented. the processo r implements only the least significant pidsize+1 bits in the pid registers. 58?59 ? reserved, should be cleared. 60?61 ntlbs number of tlbs. the value of ntlbs is one less than the number of software- accessible tlb structures that are implemen ted by the processor. ntlbs is set to one less than the number of tlb structures so that its value matches the maximum value of mas0[tlbsel].) 00 1 tlb 01 2 tlbs 10 3 tlbs 11 4 tlbs 62?63 mavn mmu architecture version number. indicates the version number of the architecture of the mmu implemented by the processor. 00 version 1.0 01 reserved 10 reserved 11 reserved RM0004 register model 100/1176 2.12.4 tlb configuration registers (tlb n cfg) tlbncfg registers, shown below, provide information about each specific tlb that is visible to the programming model. tlb0cfg corresponds to tlb0, tlb1cfg corresponds to tlb1, etc. tlb configuration register n (tlb0cfg) spr 688 (tlb0cfg) 689 (tlb1cfg) access: supervisor read-only 32 39 40 43 44 47 48 49 50 51 52 63 r assoc minsize maxsize iprot avail ? nentry w reset implementation-specific value table 36. tlb n cfg field descriptions bits name description 32?39 assoc associativity of tlb n. number of ways of associativity of tlb array. 0000_0000 fully associative (a value equal to nentry also indicates fully associative.) 0000_0001 1-way set associative 0000_0002 2-way set associative ? 40?43 minsize minimum page size of tlb n 0001 indicates smallest page size is 4 kbytes 0002 indicates smallest page size is 8 kbytes ? 44?47 maxsize maximum page size of tlb n 0001 indicates maximum page size is 4 kbytes 0002 indicates maximum page size is 8 kbytes ? 48 iprot invalidate protect capability of tlb n array. 0 indicates invalidate protection capability not supported. 1 indicates invalidate protection capability supported. 49 avail page size availability of tlb n array. 0 fixed selectable page size from minsize to maxsize (all tlb entries are the same size). 1 variable page size from minsize to maxsize (each tlb entry can be sized separately). 50?51 ? reserved, should be cleared. 52?63 nentry number of entries in tlb n register model RM0004 101/1176 2.12.5 mmu assist registers (mas0?mas7) mmu assist registers are defined by the eis and used by the mmu to manage pages and tlbs. note that some fields in these registers are redefined by implementations. mas register 0 (mas0) mas0, is used for mmu read/write and replacement control. mas register 0 (mas0) spr 624 access: supervisor read/write 32 33 34 35 36 47 48 51 52 61 62 63 r ? tlbse l esel ? nv w reset all zeros table 37. mas0 field descriptions bits name comments or function when set 32?33 ? reserved, should be cleared. 34?35 tlbsel selects tlb for access. 00 tlb0 01 tlb1 10 tlb2 11 tlb3 36?47 esel entry select. identifies an entry in the selected array to be used for tlbwe and tlbre . valid values for esel are from 0 to tlb n cfg[assoc] - 1. that is, esel selects the way from a set of entries determined by mas3[epn]. for fully associative tlb arrays, esel ranges from 0 to tlb n cfg[nentry] - 1. esel is also updated on tlb error exceptions (misses) and tlbsx hit and miss cases. 48?51 ? reserved, should be cleared. 52?63 nv next victim. for those tlbs that support t he nv field, provides a hint to software to identify the next victim to be target ed for a tlb miss replacement operation. if the tlb selected by mas0[tlbsel] does not support nv, this field is undefined. the computation of nv is implementation-dependent. nv is updated on tlb error exceptions (misses), tlbsx hit and miss cases, as shown in ta b l e 1 9 4 , and on execution of tlbre if the accessed tlb array supports nv. if nv is updated by a supported tlb array, nv always pres ents a value that can be used in mas0[esel]. RM0004 register model 102/1176 mas register 1 (mas1) below is the format of mas1. mas register 1 (mas1) format spr 625 access: supervisor read/write 32 33 34 47 48 50 51 52 55 56 63 r v iprot tid ?tstsize ? w reset all zeros table 38. mas1 field descriptions?descriptor context and configuration control bits name descriptions 32 v tlb valid bit. 0 this tlb entry is invalid. 1 this tlb entry is valid. 33 iprot invalidate protect. set to protect this tlb entry from invalidate operations due the execution of tlbivax , broadcast invalidations from another processor, or flash invalidations. note that not all tlb arrays are necessarily protected from invalidation with iprot. arrays that suppor t invalidate protection are denoted as such in the tlb configuration registers. 0 entry is not protected from invalidation. 1 entry is protected from invalidation. 34?35 ? reserved, should be cleared. 36?47 tid translation identity. during translation, ti d is compared with the current process ids (pids) to select a tlb entry. a tid value of 0 defines an entry as global and matches with all process ids. 48?50 ? reserved, should be cleared. 51 ts translation space. during translation, ts is compared with as (msr[is] or msr[ds], depending on the type of access) to select a tlb entry. 52?55 tsize translation size. defines the page size of the tlb entry. for tlb arrays that contain fixed-size tlb entries, tsize is ignored. for variable page-size tlb arrays, the page size is 4 tsize kbytes. tsize must be between tlb n cfg[minsize] and tlb n cfg[minsize]. note that the eis standard supports all 16 page sizes defined in book e. 0001 4 kbyte 0010 16 kbyte 0011 64 kbyte 0100 256 kbyte 0101 1 mbyte 0110 4 mbyte 0111 16 mbyte 1000 64 mbyte 1001 256 mbyte 1010 1 gbyte 1011 4 gbyte 56?63 ? reserved, should be cleared. register model RM0004 103/1176 mas register 2 (mas2) mas2, contains fields for specifying the effective page address and the storage attributes for a tlb entry. mas register 2 (mas2) spr 626 access: supervisor read/write 32 51 52 55 56 57 58 59 60 61 62 63 r epn ? acm x0 vle x1 wimge w reset undefined table 39. mas2 field descriptions?epn and page attributes bits name description 32?51 epn effective page number. depending on page size, only the bits associated with a page boundary are valid. bits that represent offsets within a pag e are ignored and should be zero. epn[0?31] are accessible only in 64-bit implementations as the u pper 32 bits of the logical address of the page. 52?55 ? reserved, should be cleared. 56?57 acm x0 alternate coherency mode. allows an implementation to employ multiple coherency methods. if the m attribute (memory coherence required) is not set for a page (m=0), the page has no coherency associated with it and acm is ignored. if the m at tribute is set for a page (m=1), acm determines the coherency domain (or protocol) used. acm values are implementation dependent. note: some previous implementations may have a storage bit in the bit 57 position labeled as x0. 58 vle x1 vle mode. identifies pages which contain instru ctions from the vle instruction set. the vle attribute is only implemented if the processor supports the vle extension. setting the vle attribute to 1 and setting the e attribute to 1 is considered a programming error and an attempt to fetch instructions from a page so marked produces an in struction storage interrupt byte ordering exception and sets esr[bo]. 0 instructions fetched from the page are decoded and executed as powerpc (and associated eis apus) instructions. 1 instructions fetched from the page are decoded and executed as vle (and associated eis apus) instructions.implementation-dependent page attribute. note: some implementations have a bit in this positio n labeled as x1. software should not use the presence of this bit (the ability to set to 1 and read a 1) to determine if the implementation supports the vle extension. 59 w write-through 0 this page is cons idered write-back with respect to the caches in the system. 1 all stores performed to this page are written through the caches to main memory. 60 i caching-inhibited 0 accesses to this page are considered cacheable. 1 the page is considered caching-inhibited. all loads and stores to the page bypass the caches and are performed directly to main memory. a read or write to a caching-inhibited page affects only the memory element specified by the operation. 61 m memory coherence required 0 memory coherence is not required. 1 memory coherence is required. this allows loads and stores to this page to be coherent with loads and stores from other processors (and device s) in the system, assuming all such devices are participating in the coherence protocol. RM0004 register model 104/1176 mas register 3 (mas3) mas3 contains fields for specifying the real page address and the permission attributes for a tlb entry. mas register 3 (mas3) 62 g guarded 0 accesses to this page are not guarded and can be performed before it is known if they are required by the sequential execution model. 1 loads and stores to this page are performed without speculation (that is, they are known to be required). 63 e endianness. determines endianness for the corresponding page. little-endian operation is true little endian, which differs from the modified little-endi an byte-ordering model optionally available in previous devices that implem ent the powerpc architecture. 0 the page is accessed in big-endian byte order. 1 the page is accessed in true little-endian byte order. table 39. mas2 field descriptions?epn and page attributes (continued) bits name description spr 627 access: supervisor read/write 32 51 52 53 54 57 58 59 60 61 62 63 r rpn(32?51) ? u0?u3 ux sx uwswur sr w reset all zeros table 40. mas3 field descriptions?rpn and access control bits name description 32?51 rpn[32?51] real page number bits 32?51. depending on page size, only the bits associated with a page boundary are valid. bits that represent offsets within a page are ignored and should be zero. if the physical address space exceeds 32 bits, rpn[0?31] are accessed through mas7. 52?53 ? reserved, should be cleared. 54?57 u0?u3 user bits. associated with a tlb entry and used by system software. for example, these bits may be used to hold information useful to a page scanning algorithm or be used to mark more abstract page attributes. 58?63 ux,sx uw,sw ur,sr permission bits (ux, sx, uw, sw, ur, sr ). user and supervisor read, write, and execute permission bits. effects of the permission bits are defined by book e. register model RM0004 105/1176 mas register 4 (mas4) mas4,contains fields for specifying default information to be pre-loaded on certain mmu related exceptions. mas register 4 (mas4) the mas4 fields are described in ta b l e 4 1 . spr 628 access: supervisor read/write 3233 34 35 36 43 44 47 48 51 52 55 56 57 58 59 60 61 62 63 r ? tlbseld ? tidseld ?tsized acmd x0d vled x1d wd id md gd ed w reset all zeros table 41. mas4 field descriptions?hardware replacement assist configuration bits name description 32?33 ? reserved, should be cleared. 34?35 tlbseld tlbsel default value. specifies the default value loaded in mas0[tlbsel] on a tlb miss exception. 36?43 ? reserved, should be cleared. 44?47 tidseld tid default selection value. specifie s which of the curr ent pid registers should be used to load mas1[tid] on a tlb miss exception. pid registers are addressed as follows: 0000 = pid0 (pid) 0001 = pid1 ... 1110 = pid14 a value that references a non-implemen ted pid register causes a value of 0 to be placed in mas1[tid]. see the im plementations documentation for a list of supported pids. 48?51 ? reserved, should be cleared. 52?55 tsized default tsize value. specifies the defau lt value loaded into mas1[tsize] on a tlb miss exception. 56?57 acmd default acm value specifies the default value loaded into mas2[acm] on a tlb miss exception. 58 vled default vle value. specifies the default value loaded into mas2[vle] on a tlb miss exception. 59 wd default w value. specifies the default value loaded into mas2[w] on a tlb miss exception. 60 id default i value. specifies the default value loaded into mas2[i] on a tlb miss exception. 61 md default m value. specifies the default value loaded into mas2[m] on a tlb miss exception. 62 gd default g value. specifies the default value loaded into mas2[g] on a tlb miss exception. 63 ed default e value. specifies the default value loaded into mas2[e] on a tlb miss exception. RM0004 register model 106/1176 mas register 5 (mas5) the optional mas5 register, contains fields for specifying pid values to be used when searching tlb entries with the tlbsx instruction. mas register 5 (mas5) mas register 6 (mas6) mas6, contains fields for specifying pid and as values to be used when searching tlb entries with the tlbsx instruction. mas register 6 (mas6) spr 629 access: supervisor read/write 32 33 34 47 48 49 50 63 r ? spid2 ? spid3 w reset all zeros table 42. mas5 field descriptions?extended search pids bits name description 32?33 ? reserved, should be cleared. 34?47 spid2 search pid2. specifies the pid2 value used when searching the tlb during execution of tlbsx . this field is optional and if implemented is valid for only the number of bits implem ented for pid registers. 48?49 ? reserved, should be cleared. 50?63 spid3 search pid3. specifies the pid3 value used when searching the tlb during execution of tlbsx . this field is optional and if implemented is valid for only the number of bits implem ented for pid registers. spr 630 access: supervisor read/write 32 33 34 47 48 49 62 63 r ? spid0 ? spid1 sas w reset all zeros table 43. mas 6 field descriptions?search pids and search as bits name description 32?33 ? reserved, should be cleared. 34?47 spid0 search pid0. specifies the value of pid0 used when searching the tlb during execution of tlbsx . spid0 is valid for only the number of bits implemented for pid registers. 48 ? reserved, should be cleared. register model RM0004 107/1176 mas register 7 (mas7) mas7, contains the high-order address bits of the rpn only for implementations that support more than 32 bits of physical address. mas register 7 (mas7) 2.13 debug registers this section describes debug-related registers that are accessible to software running on the processor. these registers are intended for use by special debug tools and debug software, and not by general application or operating system code. 49?62 spid1 search pid1. specifies the value of pid1 used when searching the tlb during execution of tlbsx .spid1 is optional, and if implemented is valid for only the number of bits im plemented for pid registers. 63 sas address space value for searches. specifies the as value used when executing tlbsx to search the tlb. spr 944 access: supervisor read/write 32 59 60 63 r rpn (0?31) w reset all zeros table 44. mas 7 field descriptions?high order rpn bits name description 32?63 rpn[0?31] real page number (bits 0?31). rpn[32?63] are accessed through mas3. table 43. mas 6 field descriptions?search pids and search as (continued) bits name description RM0004 register model 108/1176 2.13.1 debug control r egisters (dbcr0?dbcr3) the debug control registers are used to enable debug events, reset the processor, control timer operation during debug events, and set the debug mode of the processor. debug control register 0 (dbcr0) below is the dbcr0. debug control register 0 (dbcr0) spr 308 access: supervisor-only 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 redm idm rst icmp brt irpt trap iac1 iac2 iac3 iac4 dac1 dac2 w reset all zeros debug apu 48 49 56 57 58 59 60 62 63 ret ? cirpt cret vles ? ft reset all zeros table 45. dbcr0 field descriptions bits name description 32 edm external debug mode. indicates whether the processor is in external debug mode. 0 the processor is not in external debug mode. 1 the processor is in external debug mode. in some implementations, if edm = 1, some debug registers are locked and cannot be accessed. refer to the implementation documentation for any additional implementation-specific behavior. 33 idm internal debug mode. 0 debug interrupts are disabled. no debug interrupts are taken and debug events are not logged. 1 if msr[de] = 1, the occurrence of a debug event or the recording of an earlier debug event in the dbsr when msr[de] = 0 or dbcr0[idm] = 0 causes a debug interrupt. programming note: software must clear debug event status in the dbsr in the debug interrupt handler when a debug interrupt is taken before re-enabling interrupts through msr[de]. otherwise, redundant debug interrupts are taken for the same debug event. 34?35 rst reset. book e defines rst such that 00 is always no action and all other settings are implementation 0 x default (no action) 1 x a hard reset is performed on the processor. register model RM0004 109/1176 36 icmp instruction completion debug event enable 0 icmp debug events are disabled. 1 icmp debug events are enabled. note: instruction completion does not ca use an icmp debug event if msr[de]=0. 37 brt branch taken debug event enable 0 brt debug events are disabled. 1 brt debug events are enabled. note: taken branches do not cause a brt debug event if msr[de]=0. 38 irpt interrupt taken debug event enable. 0 irpt debug events are disabled. 1 irpt debug events are enabled 39 trap trap debug event enable 0 trap debug events cannot occur. 1 trap debug events can occur. 40 iac1 instruction address compare 1 debug event enable 0 iac1 debug events cannot occur. 1 iac1 debug events can occur. 41 iac2 instruction address compare 2 debug event enable. 0 iac2 debug events cannot occur. 1 iac2 debug events can occur. 42 iac3 defined by book e as instruction address compare 3 debug event enable 0 iac3 debug events cannot occur. 1 iac3 debug events can occur. 43 iac4 defined by book e as instruction address compare 4 debug event enable 0 iac4 debug events cannot occur. 1 iac4 debug events can occur. 44?45 dac1 data address compare 1 debug event enable 00 dac1 debug events cannot occur. 01 dac1 debug events can occur only if a store-type data storage access. 10 dac1 debug events can occur only if a load-type data storage access. 11 dac1 debug events can occur on any data storage access. 46?47 dac2 data address compare 2 debug event enable 00 dac2 debug events cannot occur. 01 dac2 debug events can occur only if a store-type data storage access. 10 dac2 debug events can occur only if a load-type data storage access. 11 dac2 debug events can occur on any data storage access. 48 ret return debug event enable 0 ret debug events cannot occur. 1 ret debug events can occur. note: an rfci does not cause an ret debug event if msr[de] = 0 at the time that rfci executes. 49?56 ? reserved, should be cleared. table 45. dbcr0 field d escriptions (continued) bits name description RM0004 register model 110/1176 debug control register 1 (dbcr1) dbcr1 is shown below. debug control register 1 (dbcr1) ta bl e 4 6 provides bit definitions for the dbcr1. 57 cirpt debug apu, critical interrupt taken debug event. a critical in terrupt taken debug event occurs when dbcr0[cirpt] = 1 and a critical interrupt (any interrupt that uses the critical class, that is, uses csrr0 and csrr1) occurs. 0 critical interrupt taken debug events are disabled. 1 critical interrupt taken debug events are enabled. 58 cret debug apu. critical interrupt return debug event. a critical interrupt return debug event occurs when dbcr0[cret] = 1 and a return from critical interrupt (an rfci instruction is executed) occurs. 0 critical interrupt return debug events are disabled. 1 critical interrupt return debug events are enabled. 59 vles vle status. (vle apu). undefined for irpt, cirpt, devt[1,2], dcnt[1,2], and ude events. 0 cret debug events are disabled. 1 an icmp, brt, trap, ret, cret, iac, or dac debug event occurred on a vle instruction. 60?62 ? reserved 63 ft freeze timers on debug event 0 enable clocking of timers. 1 disable clocking of timers if any dbsr bit is set (except mrr). table 45. dbcr0 field d escriptions (continued) bits name description spr 309 access: supervisor read/write 32 33 34 35 36 37 38 39 40 41 42 47 48 49 50 51 52 53 54 55 56 57 58 63 r iac1us iac1er iac2us iac2er iac12m ? iac3us iac3er iac4us iac4er iac34m ? w reset all zeros table 46. dbcr1 field descriptions bits name description 32?33 iac1us instruction address compar e 1 user/supervisor mode 00 iac1 debug events can occur. 01 reserved 10 iac1 debug events can occur only if msr[pr]=0. 11 iac1 debug events can occur only if msr[pr]=1. register model RM0004 111/1176 34?35 iac1er instruction address compar e 1 effective/real mode 00 iac1 debug events are based on effective addresses. 01 iac1 debug events are based on real addresses. 10 iac1 debug events are based on effective addresses and can occur only if msr[is]=0. 11 iac1 debug events are based on effective addresses and can occur only if msr[is]=1. 36?37 iac2us instruction address compar e 2 user/supervisor mode 00 iac2 debug events can occur. 01 reserved 10 iac2 debug events can occur only if msr[pr]=0. 11 iac2 debug events can occur only if msr[pr]=1. 38?39 iac2er instruction address compar e 2 effective/real mode 00 iac2 debug events are based on effective addresses. 01 iac2 debug events are based on real addresses. 10 iac2 debug events are based on effective addresses and can occur only if msr[is]=0. 11 iac2 debug events are based on effective addresses and can occur only if msr[is]=1. 40?41 iac12m instruction address compare 1/2 mode 00 exact address compare. iac1 debug ev ents can occur only if the instruction fetch address equals the value in iac1. iac2 debug events can occur only if the instruction fetch address equals the value in iac2. 01 address bit match. iac1 and iac2 debug events can occur only if the instruction fetch address, anded with the contents of iac2, equals the value in iac1, also anded with the contents of iac2. if iac1us iac2us or iac1er iac2er, results are boundedly undefined. 10 inclusive address range compare. iac1 and iac2 debug events can occur only if the instruction fetch address lies between the values specified in iac1 and iac2. if iac1us iac2us or iac1er iac2er, results are boundedly undefined. 11 exclusive address range compare. iac1 and iac2 debug events can occur only if the instruction fetch address lies between the values specified in iac1 and iac2. if iac1us iac2us or iac1er iac2er, results are boundedly undefined. 42?47 ? reserved, should be cleared. 48?49 iac3us instruction address compar e 3 user/supervisor mode 00 iac3 debug events can occur. 01 reserved 10 iac3 debug events can occur only if msr[pr]=0. 11 iac3 debug events can occur only if msr[pr]=1. table 46. dbcr1 field d escriptions (continued) bits name description RM0004 register model 112/1176 50?51 iac3er instruction address compar e 3 effective/real mode 00 iac3 debug events are based on effective addresses. 01 iac3 debug events are based on real addresses. 10 iac3 debug events are based on effective addresses and can occur only if msr[is]=0. 11 iac3 debug events are based on effective addresses and can occur only if msr[is]=1. 52?53 iac4us instruction address compar e 4 user/supervisor mode 00 iac4 debug events can occur. 01 reserved 10 iac4 debug events can occur only if msr[pr]=0. 11 iac4 debug events can occur only if msr[pr]=1. 54?55 iac4er instruction address compar e 4 effective/real mode 00 iac4 debug events are based on effective addresses. 01 iac4 debug events are based on real addresses. 10 iac4 debug events are based on effective addresses and can occur only if msr[is]=0. 11 iac4 debug events are based on effective addresses and can occur only if msr[is]=1. 56?57 iac34m instruction address compare 3/4 mode 00 exact address compare. iac3 debug ev ents can occur only if the instruction fetch address equals the value in iac3. iac4 debug events can occur only if the instruction fetch address equals the value in iac4. 01 address bit match. iac3 and iac4 debug events can occur only if the data storage access address, anded with t he contents of iac4, equals the value in iac3, also anded with the contents of iac4. if iac3us iac4us or iac3er iac4er, results are boundedly undefined. 10 inclusive address range compare. iac3 and iac4 debug events can occur only if the instruction fetch address lies between the values specified in iac3 and iac4. if iac3us iac4us or iac3er iac4er, results are boundedly undefined. 11 exclusive address range compare. iac3 and iac4 debug events can occur only if the instruction fetch address lies between the values specified in iac3 and iac4. if iac3us iac4us or iac3er iac4er, results are boundedly undefined. 58?63 ? reserved, should be cleared. table 46. dbcr1 field d escriptions (continued) bits name description register model RM0004 113/1176 debug control register 2 (dbcr2) dbcr2 is shown below. debug control register 2 (dbcr2) spr 310 access: supervisor read/write 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 55 56 63 r dac1usd?ac1erdac2usdac2erdac12m dac1lnk dac2lnk dvc1m dvc2m dvc1be dvc2be w reset all zeros table 47. dbcr2 field descriptions bits name description 32?33 dac1us data address compare 1 user/supervisor mode 00 dac1 debug events can occur. 01 reserved 10 dac1 debug events can occur only if msr[pr]=0. 11 dac1 debug events can occur only if msr[pr]=1. 34?35 dac1er data address compare 1 effective/real mode 00 dac1 debug events are based on effective addresses. 01 dac1 debug events are based on real addresses. 10 dac1 debug events are based on effective addresses and can occur only if msr[ds]=0. 11 dac1 debug events are based on effective addresses and can occur only if msr[ds]=1. 36?37 dac2us data address compare 2 user/supervisor mode 00 dac2 debug events can occur. 01 reserved 10 dac2 debug events can occur only if msr[pr]=0. 11 dac2 debug events can occur only if msr[pr]=1. 38?39 dac2er data address compare 2 effective/real mode 00 dac2 debug events are based on effective addresses. 01 dac2 debug events are based on real addresses. 10 dac2 debug events are based on effective addresses and can occur only if msr[ds]=0. 11 dac2 debug events are based on effective addresses and can occur only if msr[ds]=1. RM0004 register model 114/1176 40?41 dac12m data address compare 1/2 mode 00 exact address compare. dac1 debug events can occur only if the data access address equals the value in dac1. dac2 debug events can occur only if the data access address equals the value in dac2. 01 address bit match. dac1 and dac2 debug events can occur only if the data access address, anded with the contents of dac2, equals the value in dac1, also anded with the dac2 contents. if dac1us dac2us or dac1er dac2er, results are boundedly undefined. 10 inclusive address range compare. dac1 and dac2 debug events can occur only if the data access address lies between the values specified in dac1 and dac2. if dac1us dac2us or dac1er dac2er, results are boundedly undefined. 11 exclusive address range compare. dac1 and dac2 debug events can occur only if the data access address li es between the values specified in dac1 and dac2. if dac1us dac2us or dac1er dac2er, results are boundedly undefined. 42 dac1lnk data address compare 1 linked 0 no effect 1 dac1 debug events are linked to iac1 debug events. iac1 debug events do not affect dbsr. when linked to iac1, dac1 debug events are conditioned based on whether the instruction also generated an iac1 debug event. 43 dac2lnk data address compare 2 linked 0 no effect 1 dac 2 debug events are linked to iac3 debug events. iac3 debug events do not affect dbsr. when linked to iac3, dac2 debug events are conditioned based on whether the instruction also generate d an iac3 debug event. dac2 can only be linked if dac12m specifies ex act address compare because dac2 debug events are not generated in the other compare modes. 44?45 dvc1m data value compare 1 mode 00 dac1 debug events can occur. 01 dac1 debug events can occur only when all bytes in dbcr2[dvc1be] in the data value of the data storage access match their corresponding bytes in dvc1. 10 dac1 debug events can occur only when at least one of the bytes in dbcr2[dvc1be] in the data value of th e data storage access matches its corresponding byte in dvc1. 11 dac1 debug events can occur only when all bytes in dbcr2[dvc1be] within at least one of the half words of the data value of the data storage access match their corresponding bytes in dvc1. table 47. dbcr2 field desc riptions (continued) bits name description register model RM0004 115/1176 debug control register 3 (dbcr3) the debug apu defines the dbcr3, however its contents are implementation specific. debug control register 2 (dbcr2) 46?47 dvc2m data value compare 2 mode 00 dac2 debug events can occur. 01 dac2 debug events can occur only when all bytes in dbcr2[dvc2be] in the data value of the data storage access match their corresponding bytes in dvc2. 10 dac2 debug events can occur only when at least one of the bytes in dbcr2[dvc2be] in the data value of th e data storage access matches its corresponding byte in dvc2. 11 dac2 debug events can occur only when all bytes in dbcr2[dvc2be] within at least one of the half words of the data value of the data storage access match their corresponding bytes in dvc2. 48?55 dvc1be data value compare 1 byte enables. specifies which bytes in the aligned data value being read or written by the storage access are compared to the corresponding bytes in dvc1. 56?63 dvc2be data value compare 2 byte enables. specifies which bytes in the aligned data value being read or written by the storage access are compared to the corresponding bytes in dvc2. spr 561 access: supervisor-only 32 63 r implementation-specific fields w reset implementation-specific table 47. dbcr2 field desc riptions (continued) bits name description RM0004 register model 116/1176 2.13.2 de bug status register (dbsr) the dbsr, provides status debug events information for the most recent processor reset. debug status register (dbsr) the dbsr is set through hardware, but is read through software using mfspr and cleared by writing ones to them; writing zeros has no effect. spr: 304 access: supervisor: w1c 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 r ide ude mrr icmp brt irpt trap iac1 iac2 iac3 iac3 dac1rdac1wdac2rdac2w w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 undefined 0 0 0 0 0 0 0 0 0 0 0 0 debug apu 48 49 56 57 58 59 63 rret ? cirpt cret ? ww1c w1c w1c reset000000000 0 00 0 0 0 0 table 48. dbsr field descriptions bits name description 32 ide imprecise debug event. set if msr[de] = 0 and a debug event causes its respective dbsr bit to be set. 33 ude unconditional debug event. set if an un conditional debug event occurred. if the ude signal (level sensitive, active low) is asserted, dbsr[ude] is affected as follows: msr[de] dbcr0[idm] action x 0 no action. 0 1 dbsr[ude] is set. 1 1 dbsr[ude] is set and a debug interrupt is taken. 34?35 mrr most recent reset. set when a reset occurs. undefined at power-up. see the implementation documentation. 36 icmp instruction complete debug event. set if an instruction completion debug event occurred and dbcr0[icmp] = 1. 37 brt branch taken debug event. set if a branch taken debug event occurred (dbcr0[brt]=1). 38 irpt interrupt taken debug event. set if an interrupt taken debug event occurred (dbcr0[irpt]=1). 39 trap trap instruction debug event. set if a trap instruction debug event occurred (dbcr0[trap]=1). 40 iac1 instruction address compare 1 debug event. set if an iac1 debug event occurred (dbcr0[iac1]=1). 41 iac2 instruction address compare 2 debug event. set if an iac2 debug event occurred (dbcr0[iac2]=1). register model RM0004 117/1176 2.13.3 instruction address co mpare registers (iac1?iac4) the instruction address compare registers (iac1?iac4) are each 64 bits, with bits 62?63 being reserved. instruction address compare registers (iac1?iac4) a debug event may be enabled to occur upon an attempt to execute an instruction from an address specified in an iac, inside or outside a range specified by iac1 and iac2 or, inside or outside a range specified by iac3 and iac4, or to blocks of addresses specified by the 42 iac3 instruction address compare 3 debug event. set if an iac3 debug event occurred (dbcr0[iac3]=1). 43 iac4 instruction address compare 4 debug event. set if an iac4 debug event occurred (dbcr0[iac4]=1). 44 dac1r data address compare 1 read debug event. set if a read-type dac1 debug event occurred (dbcr0[dac1]=10 or 11). 45 dac1w data address compare 1 write debug event. set if a write-type dac1 debug event occurred (dbcr0[dac1]=01 or 11). 46 dac2r data address compare 2 read debug even t.set if a read-type dac2 debug event occurred (dbcr0[dac2]=10 or 11). 47 dac2w data address compare 2 write debug event. set if a write-type dac2 debug event occurred (dbcr0[dac2] =01 or 11). 48 ret return debug event. set if a return debug event occurred (dbcr0[ret]=1). 49?56 ? reserved, should be cleared. 57 cirpt debug apu. critical interrupt taken debug event. a critical interrupt taken debug event occurs when dbcr0[cirpt] = 1 and a critical interrupt (any interrupt that uses the critical class, that is, uses csrr0 and csrr1) occurs. 0 no critical interrupt taken debug event has occurred. 1 a critical interrupt taken debug event occurred. 58 cret debug apu. critical interrupt return debug event. a critical interrupt return debug event occurs when dbcr0[cret] = 1 and a return from critical interrupt (an rfci instruction is executed) occurs. 0 no critical interrupt return debug event has occurred. 1 a critical interrupt return debug event occurred. 59?63 ? reserved, should be cleared. table 48. dbsr field descriptions (continued) bits name description spr 312 (iac1) 313 (iac2) 314 (iac3) 315 (iac4) access: supervisor read/write 32 61 62 63 r instruction address ? w reset all zeros RM0004 register model 118/1176 combination of the iac1 and iac2, or to blocks of addresses specified by the combination of the iac3 and iac4. because all instruction addresses are required to be word-aligned, the two low-order bits of the iacs are reserved and do not participate in the comparison to the instruction address. 2.13.4 data address compare registers (dac1?dac2) the data address compare registers (dac1 and dac2), are each 32 bits. a debug event may be enabled to occur upon loads, stores, or cache operations to an address specified in either dac1 or dac2, inside or outside a range specified by the dac1 and dac2, or to blocks of addresses specified by the combination of the dac1 and dac2. data address compare registers (dac1?dac2) the contents of dac1 or dac2 are compared to the address generated by a data storage access instruction. 2.13.5 data value compare registers (dvc1 and dvc2) the data value compare registers (dvc1 and dvc2) are shown below. a dac1r, dac1w, dac2r, or dac2w debug event may be enabled to occur upon loads or stores of a specific data value specified in either or both of dvc1 and dvc2. dbcr2[dvc1m] and dbcr2[dvc1be] control how the contents of dvc1 is compared with the value and dbcr2[dvc2m] and dbcr2[dvc2be] control how the contents of dvc2 is compared with the value. ta bl e 4 7 describes the modes provided. data value compare registers (dvc1?dvc2) 2.14 spe and spfp apu registers the spe and spfp include the si gnal processing and embedded floating-point status and control register (spefscr) , which is described in chapter 2.14.1 on page 119 .? , and the spe implements a 64-bit a ccumulator, described in chapter 2.14.2 on page 122 .? spr 316 (dac1) 317 (dac2) access: supervisor read/write 32 63 r data address w reset all zeros spr 318 (dvc1) 319 (dvc2) access: supervisor read/write 32 63 r data value w reset all zeros register model RM0004 119/1176 2.14.1 signal processing, em bedded floating-point stat us, control register (spefscr) spefscr, is used by the spe and by the emb edded floating-point apus. vector floating- point instructions affect both the high element (bits 34-39) and low element floating-point status flags (bits 50?55). double- and single-precision floating-point instructions affect only the low-element floating-point status flags and leave the high-element floating-point status flags undefined. signal processing , embedded floating-point stat us and control register (spefscr) spr: 512 access: supervisor-only 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 r sovh ovh fgh fxh finvh fdbzh funfh fovfh ? finxs finvs fdbzs funfs fovfs mode w reset 0 0 undefined 0 0 0 0 0 0 0 0 0 0 0 0 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 r sov ov fg fx finv fdbz funf fovf ? finxe finve fdbze funfe fovfe frmc w reset0000000000000000 high-word error bits status bits enable bits table 49. spefscr field descriptions bits name description 32 sovh (spe apu) summary integer overflow hi gh. set when an spe instruction sets ovh. this is a sticky bit that re mains set until it is cleared by an mtspr instruction. 33 ovh (spe apu) integer overflow high. set when an overflow or underflow occurs in the upper word of the result of an spe instruction. 34 fgh (fp apus) embedded floating-point guard bit high. used by the floating-point round interrupt handler. fgh is an extensio n of the low-order bits of the fractional result produced from a floating-point operation on the high word. fgh is zeroed if an overflow, underflow, or invalid input error is detected on the high element of a vector floating-point instruction. execution of a scalar floating-point instruction leaves fgh undefined. 35 fxh (spfp apu) embedded floating-point inexact bit high. used by the floating-point round interrupt handler. fxh is an extension of the low-order bits of the fractional result produced from a floating-point operation on the high word. fxh represents the logical or of all of the bits shifted right from the guard bit when the fractional result is normalized. fxh is zeroed if an overflow, underflow, or invalid input error is detected on the high element of a vector floating-point instruction. execution of a scalar floating-point instruction leaves fxh undefined. RM0004 register model 120/1176 36 finvh (fp apus) embedded floating-point invalid operation/input error high. set under any of the following conditions: any operand of a high word vector floatin g-point instruction is infinity, nan, or denorm the operation is a divide and the dividend and divisor are both 0 a conversion to integer or fractional value overflows. execution of a scalar floating-point instruction leaves finvh undefined. 37 fdbzh (fp apus) embedded floating-point divide by zero high. set when a vector floating-point divide instruction is executed with a divisor of 0 in the high word operand and the dividend is a finite non-zero number. execution of a scalar floating-point instruction leaves fdbzh undefined. 38 funfh (fp apus) embedded floating-point underflow high. set when the execution of a vector floating-point instruction results in an underflow on the high word operation. execution of a scalar floating-point instruction leaves funfh undefined. 39 fovfh (fp apus) embedded floating-point overflow high. set when the execution of a vector floating-point instruction results in an overflow on the high word operation. execution of a scalar floating-point instruction leaves fovfh undefined. 40?41 ? reserved, should be cleared. 42 finxs (fp apus) embedded floating-point inexact sticky flag. set under the following conditions: ? execution of any scalar or vector floating-point instruction delivers an inexact result for either the low or high element and no floating-point data interrupt is taken for either element ? a floating-point instruction results in overflow (fovf=1 or fovfh=1), but floating-point overflow exceptions are disabled (fovfe=0). ? a floating-point instruction results in underflow (funf=1 or funfh=1), but floating-point underflow exceptions are disabled (funfe=0), and no floating- point data interrupt occurs. finxs remains set until it is cleared by software. 43 finvs (fp apus) embedded floating-point invalid o peration sticky flag. the sticky result of any floating-point instruction that ca uses finvh or finv to be set. that is, finvs <- finvs | finv | finvh. this action may optionally be performed by hardware. to ensure proper operation, software should set this bit on the detection of finv or finvh set to one. fi nvs remains set until it is cleared by software. (1) 44 fdbzs (fp apus) embedded floating-point divide by zero sticky flag. set when a floating-point divide instruction sets fd bzh or fdbz. that is, fdbzs <- fdbzs | fdbzh | fdbz. fdbzs remains set un til it is cleared by software. 45 funfs (fp apus) embedded floating-point underflow sticky flag. defined to be the sticky result of any floating-point instruction that causes funfh or funf to be set. that is, funfs <- funfs | funf | funfh. th is action may optionally be performed by hardware. to ensure proper operation, software should set this bit on the detection of funf or funfh being set. fu nfs remains set until it is cleared by software. 1 table 49. spefscr field d escriptions (continued) bits name description register model RM0004 121/1176 46 fovfs (fp apus) embedded floating-point overflow sticky flag. defined to be the sticky result of any floating-point instruction th at causes fovh or fovf to be set. that is, fovfs <- fovfs | fovf | fovfh. th is action may optionally be performed by hardware. to ensure proper operation, software should set this bit on the detection of fovf or fovfh being set. fovfs remains set until it is cleared by software. 1 47 mode (fp apus) embedded floating-point operating mode. controls the operating mode of the embedded floating-point oper ations defined in the spe, and the embedded floating-point apus. 0 default hardware results operating mode 1 reserved. 48 sov (spe apu) summary integer overflow low. set when an spe instruction sets ov. this sticky bit rema ins set until an mtspr writes a 0 to this bit. 49 ov (spe apu) integer overflow low. ov is set when an overflow or underflow occurs in the lower word of the re sult of an spe instruction. 50 fg (fp apus) embedded floating-point guard bit (low/scalar) used by the floating- point round interrupt handler. fg is an extension of the low-order bits of the fractional result produced from a floating- point operation on the low word or any scalar floating-point operation. fg is clea red if an overflow, underflow, or invalid input error is detected on either the low element of a vector floating-point instruction or any scalar fl oating-point instruction. 51 fx (fp apus) embedded floating-point inexact bit (low/scalar). used by the floating- point round interrupt handler. fx is an extension of the low-order bits of the fractional result produced from a floating- point operation on the low word or any scalar floating-point instruction. fx repres ents the logical or of all of the bits shifted right from the guard bit when the fractional result is normalized. fx is zeroed if an overflow, underflow, or invalid input error is detected on either the low element of a vector floating-point instruction or any scalar floating-point instruction. 52 finv (fp apus) embedded floating-point invalid operation/input error (low/scalar). set by the following conditions: ? any operand of a low-word vector or scalar floating-point operation is infinity, nan, or denorm ? the operation is a divide and the dividend and divisor are both 0 ? a conversion to integer or fractional value overflows 53 fdbz (fp apus) embedded floating-point divide by zero (low/scalar). set when a scalar or vector floating-point divide instruction is executed with a divisor of 0 in the low word operand and the dividend is a finite non-zero number. 54 funf (fp apus) embedded floating-point underflow (low/scalar). set when execution of a scalar or vector floating-point inst ruction results in an underflow on the low word operation. 55 fovf (fp apus) embedded floating-point overflow (low/scalar). set when the execution of a scalar or vector floating-poi nt instruction results in an overflow on the low word operation. 56 ? reserved, should be cleared. table 49. spefscr field d escriptions (continued) bits name description RM0004 register model 122/1176 2.14.2 accumulator (acc) the 64-bit architectural accumulator register holds the results of th e multiply accumulate (mac) forms of spe integer inst ructions. the accumulator allo ws back-to-back execution of dependent mac instructions, something that is found in the inner loops of dsp code such as finite impulse response (fir) filters. the accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use them. instead, they are always copied into a 64-bit destination gpr specified as part of the instruction. the 57 finxe (fp apus) embedded floating-point round (inexact) exception enable 0 exception disabled 1 exception enabled. a floating-point round interrupt is taken if no other interrupt is taken, and if fg | fgh | fx | fxh (signifying an inexact result) is set as a result of a floating-point operation. if a floating-point instruction operation results in overflow or underflow and the corresponding underflow or overflow exception is disabled, a floating-point round interrupt is taken. 58 finve (fp apus) embedded floating-point invalid operation/input error exception enable 0 exception disabled 1 exception enabled. a floating-point data interrupt is taken if a floating-point instruction sets finv or finvh. 59 fdbze (fp apus) embedded floating-point divide by zero exception enable 0 exception disabled 1 exception enabled. a floating-point data interrupt is taken if a floating-point instruction sets fdbz or fdbzh. 60 funfe (fp apus) embedded floating-point underflow exception enable 0 exception disabled 1 exception enabled. a floating-point data interrupt is taken if a floating-point instruction sets funf or funfh. 61 fovfe (fp apus) embedded floating-point overflow exception enable 0 exception disabled 1 exception enabled. a floating-point data interrupt is taken if a floating-point instruction sets fovf or fovfh. 62?63 frmc (fp apus) embedded floating-point rounding mode control 00 round to nearest 01 round toward zero 10 round toward +infinity. if this mode is not implemented, embedded floating- point round interrupts are generated for every floating-point instruction for which rounding is indicated. 11 round toward -infinity. if this mode is not implemented, embedded floating- point round interrupts are generated for every floating-point instruction for which rounding is indicated. 1. software note: software can detect hardware that manages this sticky bit by performing an operation on a nan and observing whether hardware sets this sticky bit. in the absence of doing this, if it desired that software written will work on al l processors that support embedded fl oating-point, software should check the appropriate status bits and set the sticky bit itself (if hardware also performs this operation, the action is redundant). table 49. spefscr field d escriptions (continued) bits name description register model RM0004 123/1176 accumulator, however, has to be explicitly cleared when starting a new mac loop. based upon the type of instruction, an accumulator can hold either a single 64-bit value or a vector of two 32-bit elements. the initialize accumulator instruction ( evmra ) is provided to initialize the accumulator. this instruction is described in chapter 6 on page 330 .? 2.15 alternate time base registers (atbl and atbu) the alternate time base counter (atb), is formed by concatenating the upper and lower alternate time base registers (atbu and atbl). atbl (spr 526) provides read-only access to the 64-bit alternate time base counter, which is incremented at an implementation-defined frequency. atb registers are accessible in both user and supervisor mode. like the tb implementation, atbl is an aliased name for atb. alternate time base register lower (atbl) the atbu register, provides read-only access to the upper 32 bits of the alternate time base counter. it is accessible in both user and supervisor mode. alternate time base register upper (atbu) spr 526 access: user read-only 32 63 ratbcl w reset all zeros table 50. atbl field descriptions bits name description 32?63 atbcl alternate time base counter lower. lower 32 bits of the alternate time base counter spr 527 access: user read-only 32 63 r at b c u w reset all zeros table 51. atbu field descriptions bits name description 32?63 atbcu alternate time base counter upper. upper 32 bits of the alternate time base counter RM0004 register model 124/1176 2.16 performance monitor registers (pmrs) the eis defines a set of register resources used exclusively by the performance monitor. pmrs are similar to the sprs defined in the book e architecture and are accessed by mtpmr and mfpmr , which are also defined by the eis. ta b l e 5 2 lists supervisor-level pmrs. user-level software that attempts to read or write supervisor-level pmrs causes a privilege exception. user-level pmrs in ta bl e 5 3 are read-only and are accessed with mfpmr . attempting to write user-level registers in supervisor or user mode causes an illegal instruction exception. table 52. performance monitor registers?supervisor level abbreviation register name pmr number pmr[0?4] pmr[5?9] section/page pmgc0 performance monitor global co ntrol register 0 400 01100 10000 chapter 2.16.1 pmlca0 performance monitor local control a0 144 00100 10000 chapter 2.16.3 pmlca1 performance monitor local control a1 145 00100 10001 pmlca2 performance monitor local control a2 146 00100 10010 pmlca3 performance monitor local control a3 147 00100 10011 pmlcb0 performance monitor local control b0 272 01000 10000 chapter 2.16.5 pmlcb1 performance monitor local control b1 273 01000 10001 pmlcb2 performance monitor local control b2 274 01000 10010 pmlcb3 performance monitor local control b3 275 01000 10011 pmc0 performance monitor counter 0 16 00000 10000 chapter 2.16.7 pmc1 performance monitor counter 1 17 00000 10001 pmc2 performance monitor counter 2 18 00000 10010 pmc3 performance monitor counter 3 19 00000 10011 table 53. performance monitor registers?user level (read-only) abbreviation register name pmr number pmr[0?4] pmr[5?9] section/page upmgc0 user performance monitor global control register 0 384 01100 00000 chapter 2.16.3 upmlca0 user performance monitor local control a0 128 00100 00000 chapter 2.16.4 upmlca1 user performance monitor local control a1 129 00100 00001 upmlca2 user performance monitor local control a2 130 00100 00010 upmlca3 user performance monitor local control a3 131 00100 00011 upmlcb0 user performance monitor local control b0 256 01000 00000 chapter 2.16.6 upmlcb1 user performance monitor local control b1 257 01000 00001 upmlcb2 user performance monitor local control b2 258 01000 00010 upmlcb3 user performance monitor local control b3 259 01000 00011 register model RM0004 125/1176 2.16.1 global control register 0 (pmgc0) the performance monitor global control register (pmgc0), controls all performance monitor counters. performance monitor global control register 0 (pmgc0)/ user performance monitor global control register 0 (upmgc0) pmgc0 is cleared by a hard reset. reading this register does not change its contents. upmc0 user performance monitor counter 0 0 00000 00000 chapter 2.16.7 upmc1 user performance monitor counter 1 1 00000 00001 upmc2 user performance monitor counter 2 2 00000 00010 upmc3 user performance monitor counter 3 3 00000 00011 table 53. performance monitor registers?user level (read-only) (continued) abbreviation register name pmr number pmr[0?4] pmr[5?9] section/page pmr pmgc0 (pmr400) upmgc0 (pmr384) access: pmgc0: supervisor-only upmgc0: supervisor/user read-only 32 33 34 35 50 51 52 53 54 55 56 63 r fac pmie fcece ? tbsel ? tbee ? w reset all zeros table 54. pmgc0 field descriptions bits name description 32 fac freeze all counters. when fac is set by hardware or software, pmlcx[fc] maintains its current value until it is changed by software. 0 the pmcs are incremented (if permitt ed by other pm control bits). 1 the pmcs are not incremented. 33 pmie performance monitor interrupt enable 0 performance monitor interrupts are disabled. 1 performance monitor interrupts are enabled and occur when an enabled condition or event occurs. 34 fcece freeze counters on enabled condition or event 0 the pmcs can be incremented (if permitted by other pm control bits). 1 the pmcs can be incremented (if permitted by other pm control bits) only until an enabled condition or event occurs. when an enabled condition or event occurs, pmgc0[fac] is set. it is up to software to clear fac. 35?50 ? reserved, should be cleared. RM0004 register model 126/1176 2.16.2 user global control register 0 (upmgc0) the contents of pmgc0 are reflected to upmg c0, which is read by user-level software. upmgc0 is read with the mfpmr instruction using pmr384. 51?52 tbsel time base selector. selects the time base bit that can cause a time base transition event (the event occurs when the selected bit changes from 0 to 1). 00 tb[63] (tbl[31]) 01 tb[55] (tbl[23]) 10 tb[51] (tbl[19]) 11 tb[47] (tbl[15]) time base transition events can be used to periodically collect information about processor activity. in multiprocessor systems in which tb registers are synchronized among processors, time base transition events can be used to correlate the performance monitor data obtained by the several processors. for this use, software must specify the same tbsel value for all processors in the system. because the time-base frequency is implementation-dependent, software should invoke a system service program to obtain the frequency before choosing a value for tbsel. 53?54 ? reserved, should be cleared. 55 tbee time base transition event exception enable 0 exceptions from time base transition events are disabled. 1 exceptions from time base transition events are enabled. a time base transition is signalled to the performance monitor if the tb bit specified in pmgc0[tbsel] changes from 0 to 1. time base transition events can be used to freeze the counters (pmgc0[fcece]) or signal an exception (pmgc0[pmie]). changing pmgc0[tbsel] while pmgc0[t bee] is enabled may cause a false 0 to 1 transition that signals the specif ied action (freeze, exception) to occur immediately. although the interrupt signal condition may occur with msr[ee] = 0, the interrupt cannot be taken until msr[ee] = 1. 55?63 ? reserved, should be cleared. table 54. pmgc0 field descriptions (continued) bits name description register model RM0004 127/1176 2.16.3 local control a registers (pmlca0?pmlca3) the local control a registers 0?3 (pmlca0?pmlca3), function as event selectors and give local control for the corresponding performance monitor counters. pmlca works with the corresponding pmlcb register. local control a registers (pmlca0?pmlca3)/ user local control a registers (upmlca0?upmlca3) pmlca0 (pmr144) pmlca1 (pmr145) pmlca2 (pmr146) pmlca3 (pmr147) upmlca0 (pmr128) upmlca1 (pmr129) upmlca2 (pmr130) upmlca3 (pmr131) access: pmlca0?pmlca3: supervisor-only upmlca0?upmlca3: supervisor/user read-only 32 33 34 35 36 37 38 40 41 47 48 63 r fc fcs fcu fcm1 fcm0 ce ?event ? w reset all zeros table 55. pmlca0?pmlca3 field descriptions bits name description 32 fc freeze counter 0 the pmc is incremented (if perm itted by other pm control bits). 1 the pmc is not incremented. 33 fcs freeze counter in supervisor state 0 the pmc is incremented (if perm itted by other pm control bits). 1 the pmc is not incremented if msr[pr] = 0. 34 fcu freeze counter in user state 0 the pmc is incremented (if perm itted by other pm control bits). 1 the pmc is not incremented if msr[pr] = 1. 35 fcm1 freeze counter while mark = 1 0 the pmc is incremented (if perm itted by other pm control bits). 1 the pmc is not incremented if msr[pmm] = 1. 36 fcm0 freeze counter while mark = 0 0 the pmc is incremented (if perm itted by other pm control bits). 1 the pmc is not incremented if msr[pmm] = 0. 37 ce condition enable 0pmc x overflow conditions cannot occur. (pmc x cannot cause interrupts, cannot freeze counters.) 1 overflow conditions occur when the most-significant-bit of pmc x is equal to one. it is recommended that ce be cleared when counter pmc x is selected for chaining. 38?40 ? reserved, should be cleared. 41?47 event event selector. up to 128 events selectable. 48?63 ? reserved, should be cleared. RM0004 register model 128/1176 2.16.4 user local control a registers (upmlca0?upmlca3) the contents of pmlca0?pmlca3 are reflected to upmlca0?upmlca3, which are read by user-level software with mfpmr using pmr numbers in ta b l e 5 3 . 2.16.5 local control b registers (pmlcb0?pmlcb3) local control b registers (pmlcb0?pmlcb3), specify a threshold value and a multiple to apply to a threshold event selected for the corresponding performance monitor counter. pmlcb works with the corresponding pmlca. local control b registers (pml cb0?pmlcb3)/user local control b registers (upm lcb0?upmlcb3) pmr pmr272 (pmlcb0) pmr273 (pmlcb1) pmr274 (pmlcb2) pmr275 (pmlcb3) pmr256 (upmlcb0) pmr257 (upmlcb1) pmr258 (upmlcb2) pmr259 (upmlcb3) access: pmlcb0?pmlcb3 supervisor read/write upmlcb0?upmlcb3 user read-only 32 52 53 55 56 57 58 63 r ? threshmu l ? threshold w reset all zeros table 56. pmlcb0 ?pmlcb3 field descriptions bits name description 32?52 ? reserved, should be cleared. 53?55 threshmul threshold multiple 000 threshold field is multiplied by 1 (pmlcb n [threshold] * 1) 001 threshold field is multiplied by 2 (pmlcb n [threshold] * 2) 010 threshold field is multiplied by 4 (pmlcb n [threshold] * 4) 011 threshold field is multiplied by 8 (pmlcb n [threshold] * 8) 100 threshold field is multiplied by 16 (pmlcb n [threshold] * 16) 101 threshold field is multiplied by 32 (pmlcb n [threshold] * 32) 110 threshold field is multiplied by 64 (pmlcb n [threshold] * 64) 111 threshold field is multiplied by 128 (pmlcb n [threshold] * 128) 56?57 ? reserved, should be cleared. 58?63 threshold threshold. only events that exceed th is value are counted. events to which a threshold value applies are implementation-dependent as are the dimension (for example duration in cycles) and the granularity with which the threshold value is interpreted. by varying the threshold value, software can profile event characteristics. for example, if pmc1 is configured to count cache misses that last longer than the threshold value, software can obtain the distribution of cache miss durations for a given program by moni toring the program repeatedly using a different threshold value each time. register model RM0004 129/1176 2.16.6 user local control b registers (upmlcb0?upmlcb3) the contents of pmlcb0?pmlcb3 are reflected to upmlcb0?upmlcb3, which are read by user-level software with mfpmr using the pmr numbers in ta bl e 5 3 . 2.16.7 performance monitor counter registers (pmc0?pmc3) the performance monitor counter registers pmc0?pmc3, are 32-bit counters that can be programmed to generate interrupt signals when they overflow. each counter is enabled to count 128 events. performance monitor counter register s (pmc0?pmc3)/user performance monitor counter registers (upmc0?upmc3) counters overflow when the high-order bit (the sign bit) becomes set; that is, they reach the value 2,147,483,648 (0x8000_0000). however, an exception is not signaled unless pmgc0[pmie] and pmlcax[ce] are also set as appropriate. the interrupts are masked by clearing msr[ee]. an interrupt that is signaled while msr[ee] is zero is not taken until msr[ee] is set. setting pmgc0[fcece] forces counters to stop counting when an enabled condition or event occurs. software is expected to use mtpmr to explicitly set pmcs to non-overflowed values. setting an overflowed value may cause an erroneous exception. for example, if both pmgc0[pmie] and pmlca x [ce] are set and the mtpmr loads an overflowed value into pmc x , an interrupt may be generated without an event counting having taken place. pmc registers are accessed with mtpmr and mfpmr using the pmr numbers in ta bl e 5 2 . 2.16.8 user performance monitor count er registers (upmc0?upmc3) the contents of pmc0?pmc3 are reflected to upmc0?upmc3, which are read by user- level software with the mfpmr instruction using the pmr numbers in ta b l e 5 3 . pmc0 (pmr16) pmc1 (pmr17) pmc2 (pmr18) pmc3 (pmr19) upmc0 (pmr0) upmc1 (pmr1) upmc2 (pmr2) upmc3 (pmr3) access: pmc0?pmc3: supervisor-only upmc0?upmc3: supervisor/user read-only 32 33 63 r ov counter value w reset all zeros table 57. pmc0?pmc3 field descriptions bits name description 32 ov overflow. when this bit is set, it indicates this counter reaches its maximum value. 33?63 counter value indicates the number of occurrences of the specified event. RM0004 register model 130/1176 2.17 device control registers (dcrs) book e defines the existence of a dcr address space and the instructions to access them, but does not define particular dcrs. the on-c hip dcrs exist architecturally outside the processor core and thus are not part of book e. dcrs may control the use of on-chip peripherals, such as memory controllers (specific dcr definitions would be provided in the implementation?s user?s manual). the contents of dcr dcrn ca n be read into a gpr using mfdcr r d , dcrn. gpr contents can be written into dcr dcrn using mtdcr dcrn ,r s. if dcrs are implemented, they are described as part of the implementation documentation. 2.18 book e spr model this section describes spr invalid references, synchronization requirements, and preserved, reserved, and allocated registers. 2.18.1 invalid spr references system behavior when an invalid spr is referenced depends on the privilege level. if the invalid spr is accessible in user mode (spr[5] = 0), an illegal instruction exception is taken. if the invalid spr is accessible only in supervisor mode (spr[5] = 1) and the core complex is in supervisor mode (msr[pr] = 0), the results of the attempted access are boundedly undefined. if the invalid spr address is accessible on ly in supervisor mode (bit 5 of an spr number = 1) and the core complex is not in supervisor mode (msr[pr] = 1), a privilege exception is taken. these results are summarized in ta bl e 5 8 . 2.18.2 synchronization requirements for sprs synchronization requirements for accessing certain sprs are shown in ta b l e 5 9 . except for these sprs, there are no synchronization requirements for accessing sprs beyond those stated in book e. (note that requirements may be different for different implementations.) table 58. system response to an invalid spr reference spr address bit 5 msr[pr] response 0 (user) x illegal exception 1 (supervisor) 0 (supervisor) boundedly undefined 1 (user) privilege exception table 59. synchronization requirements for sprs registers instruction instruction required before instruction required after dbcr0 mtspr dbcr0 none isync dbcr1 mtspr dbcr1 none isync register model RM0004 131/1176 2.18.3 reserved sprs an undefined spr number in the range 0x000?0x1ff (0?511) that is not preserved is reserved. 2.18.4 allocated sprs spr numbers allocated for implementation-dependent use are 0x200?0x3ff (512?1023). hid0 mtspr hid0 none isync hid1 mtspr hid1 none isync l1csr0 mtspr l1csr0 msync , isync isync l1csr1 mtspr l1csr1 none isync mas n mtspr mas n none isync mmucsr0 mtspr mmucsr0 none isync pid n mtspr pid n none isync spefscr mtspr spefscr none isync table 59. synchronization requirements for sprs (continued) registers instruction instruction required before instruction required after table 60. allocated sprs defined by the eis spr mnemonic register 48 pid0 (1) process id register 0. this is not truly an allocated spr; however, book e defines only this pid register and refers to it as pid rather than pid0. 512 spefscr signal processing and embedded float ing-point status and control register 515 l1cfg0 l1 cache configuration register 0 516 l1cfg1 l1 cache configuration register 1 528 ivor32 spe apu unavailable exception 529 ivor33 embedded floating-point data exception 530 ivor34 embedded floating-point round exception 531 ivor35 performance monitor inte rrupt vector offset register 570 mcsrr0 machine-check save/restore register 0 571 mcsrr1 machine-check save/restore register 1 572 mcsr machine check syndrome register 573 mcar machine check address register 624 mas0 mmu assist register 0 625 mas1 mmu assist register 1 626 mas2 mmu assist register 2 627 mas3 mmu assist register 3 RM0004 register model 132/1176 628 mas4 mmu assist register 4 629 mas5 mmu assist register 5 630 mas6 mmu assist register 6 633 pid1 process id register 1 634 pid2 process id register 2 ?pid n additional pid registers may be defined in this space 688 tlb0cfg tlb configuration register 0 689 tlb1cfg tlb configuration register 1 944 mas7 mmu assist register 7 1008 hid0 hardware implementation dependent register 0 1009 hid1 hardware implementation dependent register 1 1010 l1csr0 l1 cache control and status register 0 1011 l1csr1 l1 cache control and status register 1012 mmucsr0 mmu control and status register 0 1015 mmucfg mmu configuration register 1023 svr system version register 1. an update to a pid register must always be followed by an isync . table 60. allocated sprs defined by the eis (continued) spr mnemonic register instruction model RM0004 133/1176 3 instruction model the architecture specifications allow for different processor implementations, which may provide extensions to or deviations from the architectural descriptions. this chapter provides information about the book e architecture and the book e implementation standards (eis), which defines auxiliary processing units (apu s) and other architectural extensions that define additional instructions, registers, and interrupts. for more information, see chapter 7: auxiliary processi ng units (apus) on page 823 .? 3.1 operand conventions this section describes operand conventions as they are represented in the book e architecture. these conventions follow the basic descriptions in the classic powerpc architecture with some changes in terminology. for example, distinctions between user and supervisor-level instructions are maintained, but the designations?uisa, vea, and oea? do not apply. detailed descriptions are provided of conventions used for storing values in registers and memory, accessing processor r egisters, and representing data in these registers. 3.1.1 data organization in memory and data transfers bytes in memory are numbered consecutively starting with 0. each number is the address of the corresponding byte. memory operands can be bytes, half words, words, or double words or, for the load/store multiple instruction type and load/store string instructions, a sequence of bytes or words. the address of a memory operand is the address of its first byte (that is, of its lowest- numbered byte). operand length is implicit for each instruction. 3.1.2 alignment and misaligned accesses the operand of a single-register memory access instruction has an alignment boundary equal to its length. an operand?s address is mi saligned if it is not a multiple of its width. the concept of alignment is also applied more generally to data in memory. for example, a 12-byte data item is said to be word-aligne d if its address is a multiple of four. some instructions require their memory operands to have certain alignment. in addition, alignment can affect performance. for single-r egister memory access instructions, the best performance is obtained when memory operands are aligned. instructions are 32 bits (one word) long and must be word-aligned. note, however, that the vle extension provides both 16- and 32-bit instructions. see vle instruction alignment and byte ordering on page 217 .? ta bl e 6 1 lists characteristics for memory operands for single-register memory access instructions. RM0004 instruction model 134/1176 note that lmw , stmw , lwarx , and stwcx. instructions that are not word aligned cause an alignment exception. 3.2 instruction set summary instructions are divided into the following functional categories: integer instructions?these include arit hmetic and logical instructions. see integer instructions on page 146 .? floating-point instructions?these include floating-point vector and scalar arithmetic instructions. see embedded vector and scalar floating-point apu instructions .? note that some implementations do not support book e?defined floating-point instructions or registers. load and store instructions?see load and store instructions on page 156 .? flow control instructions?these incl ude branching instructions, cr logical instructions, trap instructions, and other instructions that affect the instruction flow. see branch and flow control instructions on page 163 .? processor control instructions?these instructions are used for synchronizing memory accesses. see processor control instructions on page 201 .? memory synchronization instructions?these instructions are used for memory synchronizing. see memory synchronization instructions on page 175 .? memory control instructions?these instructions provide control of caches and tlbs. see memory control instructions ,? and supervisor-level memory control instructions .? signal processing instructions?these inclu de a set of vector arithmetic and logic instructions optimized for signal processing. see chapter 3.6.1 on page 186 . note: instruction groupings used here do not indicate the execution unit that processes a particular instruction or group of instructions. this information, which is useful for scheduling instructions most effectively, is provided in the execution chapter for the implementation.? integer instructions operate on word operands. book e floating-point instructions operate on single-precision and double-precision floating-point operands. the powerpc architecture uses instructions that are 4 bytes long and word-aligned. it provides for byte, half-word, and word operand loads and stores between memory and a set of 32 general-purpose registers (gprs). it provides for word and double-word operand loads and stores between memory and a set of 32 floating-point registers (fprs). arithmetic and logical instructions do not read or modify memory. to use the contents of a memory location in a computation and then modify the same or another location, the memory contents must be loaded into a register, modified, and then written to the target location using load and store instructions. table 61. address characteristics of aligned operands operand operand length addr[60?63] if aligned byte (or string) 8 bits xxxx (1) 1. an x in an address bit position indicates that the bi t can be 0 or 1 independent of the state of other bits in the address. half word 2 bytes xxx0 word 4 bytes xx00 double word 8 bytes x000 instruction model RM0004 135/1176 the description of each instruction includes the mnemonic and a formatted list of operands. to simplify assembly language programming, a set of simplified mnemonics and symbols is provided for some of the frequently used instructions; see appendix b: simplified mnemonics for powerpc instructions on page 1110 ,? for a complete list of simplified mnemonics. programs written to be portable across the various assemblers for the powerpc architecture should not assume the existence of mnemonics not described in that document. 3.2.1 classes of instructions instructions belong to one of the following four classes: defined instructions (see defined instruction class on page 135 . ) allocated instructions (see allocated instruction class on page 136 . ) preserved instructions (see preserved instruction class on page 137 . ) reserved (illegal or no-o p) instructions (see reserved instruction class on page 138 . ) the class is determined by examining the primary opcode and any extended opcode. if the opcode, or combination of opcode and extended opcode, is not that of a defined, allocated, preserved, or reserv ed instruction, the instruction is illegal. definition of boundedly undefined if instructions are encoded with incorrectly set bits in reserved fields, the results on execution can be said to be boundedly undefi ned. if a user-level program executes the incorrectly coded instruction, the resulting undefined results are bounded in that a spurious change from user to supervisor state is not allowed, and the level of privilege exercised by the program in relation to memory access and other system resources cannot be exceeded. boundedly undefined results for a given instruction can vary between implementations and between execution attempts in the same implementation. defined instruction class this class of instructions consists of all the instructions defined in book e. in general, defined instructions are guaranteed to be supported within a book e system as specified by the architecture, either within the processor implementation itself or within emulation software supported by the system operating software. for implementations that only provide the 32-bit subset of book e, emulation of the 64-bit behavior of the defined instructions is not supported. see appendix d: guide lines for 32-bit book e on page 1154 . RM0004 instruction model 136/1176 any attempt to execute a defined instruction results in one of the following events: an illegal instruction exceptio n-type program interrupt, if an implementation does not recognize the instruction an unimplemented instruction exception-type program interrupt, if the instruction is recognized but not supported by the implementation and is not a floating-point instruction an unimplemented instruction exception-type program interrupt, if the instruction is recognized but not supported by the implementation, and is a floating-point instruction and floating-point processing is enabled the floating-point unavailable interrupt if the instruction is recognized but is not supported by the implementation or is a floating-point instruction and floating-point processing is disabled the floating-point unavailable interrupt when floating-point processing is disabled and a floating-point instruction is recognized and is not supported by the implementation if an instruction is recognized and supported by the implementation, the processor performs the actions described in the rest of this document. the architected behavior may cause other exceptions. a defined instruction may be retained by future versions of book e as a defined instruction, or may be reclassified as a preserved instruction (process of removal from the architecture) and eventually classified as reserved-illegal. allocated instruction class this class of instructions contains the set of instructions (a set of primary opcodes, as well as a set of extended opcodes for certain primary opcodes) used for implementation-specific instructions. ta bl e 6 2 lists blocks of opcodes allocated for implementation-dependent use. . allocated instructions are allocated to purposes that are outside the scope of book e for implementation-dependent and application-specific use. any attempt to execute an allocated inst ruction results in one of the following: an illegal instruction exceptio n-type program interrupt, if the instruction is not recognized by the implementation an unimplemented instruction exception-type program interrupt, if the instruction is recognized and enabled for execution but the implementation does not support direct table 62. allocated instructions primary opcode extended opcodes 0 all instruction encodings (bits 6?31) except 0x0000_0000 (1) . 1. instruction encoding 0x0000_0000 is and always will be reserved-illegal. 4 all instruction encodings (bits 6?31) spe and embedded floating-point instructions 19 extended opcodes (bits 21?30) 0buuuuu_0u11u 31 extended opcodes (bits 21?30) uuuuu_0u11u 59 extended opcodes (bits 21?30) uuuuu_0u10u 63 extended opcodes (bits 21?30) uuuuu_0u10u (except 00000_01100 frsp ) instruction model RM0004 137/1176 execution of the instruction. this option may be used to allow emulation for unsupported allocated instructions. a floating-point unavailable interrupt, if an allocated instruction that extends the floating-point capabilities is recognized and floating-point processing is disabled if an allocated instruction is implemented, the processor performs the actions described in the user?s manual. implementation-dependent behavior may cause other exceptions. an allocated instruction is guarant eed by book e to remain allocated. note: some allocated instructions may have associated new process state, and, therefore, may provide an associated enable bit, similar in function to msr[fp] for floating-point instructions. for such instructions, being enabled for execution implies that any associated enable bit is set to allow, or enable, instruction execution. for such instructions, the architecture provides an auxiliary processor unavailable interrupt vector in case execution of such an instruction is attempted when execution is disabled. for example, msr[spe] enables the spe unavaila ble interrupt. other a llocated instructions may not have any associated new state and therefore may not require an associated enable bit. if supported by an implementation, such instructions are assumed to be always enabled for execution. preserved instruction class the preserved instruction class supports backward com patibility with the powerpc architecture. an attempt to execute a preserved instruction results in one of the following: if the implementation does not recognize the instruction, an illegal instruction exception-type program interrupt occurs. if the instruction is recognized and supported by the implementation, the processor performs the actions defined in the previous version of the architecture. future versions of book e may retain a preserved instruction as a preserved instruction, may reclassify it as an allocated instruction, or may adopt it as part of book e. preserved opcodes are listed in ta b l e 6 3 . table 63. preserved instructions primary opcode extended opcodes 0 no preserved extended opcodes 4 no preserved extended opcodes 19 no preserved extended opcodes 31 extended opcodes (bits 21?30) 210 0b00110_10010 ( mtsr ) 242 0b00111_10010 ( mtsrin ) 370 0b01011_10010 ( tlbia ) 306 0b01001_10010 ( tlbie ) 371 0b01011_10011 ( mftb ) 595 0b10010_10011 ( mfsr ) 659 0b10100_10011 ( mfsrin ) 310 0b01001_10110 ( eciwx ) 438 0b01101_10110 ( ecowx ) 59 no preserved extended opcodes 63 no preserved extended opcodes RM0004 instruction model 138/1176 reserved instruction class this class of instructions consists of all instruction primary opcodes (and associated extended opcodes, if applicable) that do not belong to either the defined, allocated, or preserved instruction classes. reserved instructions are available for future extensions of book e. that is, some future version of book e may define any of these instructions to perform new functions or make them available for implementation-dependent use as allocated instructions. there are two types of reserved instructions, reserved-illegal and reserved-nop. attempts to execute a reserved- illegal instruction cause an illegal instruction exception-type program interrupt (see chapter 4.7.6: alignment interrupt on page 263 ) on implementations conforming to the current version of book e. reserved-illegal instructi ons are, therefore, available for future extensions to book e that would affect architected state. such extensions might include new forms of integer or floating-point arithmetic or new forms of load or store instructions that write their result in an architected register. attempts to execute a reserved-nop instruction either do not affect implementations conforming to the current version of book e (that is, treated as a no-operation instruction), or cause an illegal instruction exception-type program interrupt (see chapter 4.7.7: program interrupt on page 265 ? ). reserved-nop instructions are available for future architecture extensions that do not affect architected state. such extensions might include performance- enhancing hints such as new forms of cache touch instructions and could be added while remaining functionally compatible with implementations of previous versions of book e a reserved-illegal instruction may be retained by future versions of book e as a reserved- illegal instruction, may be subseq uently reclassified as an allo cated instruction, or may even be employed in the role of a subsequently defined instruction. a reserved-nop instruction may be retained by future versions of book e as a reserved-nop instruction, may be subsequently reclassified as an allocated instruction, or may even be employed in the role of a subsequently defined instruction that has no effect on architected state. 3.2.2 instruction forms this section describes preferred instruction forms, addressing modes, and synchronization. preferred instruction forms (no-op) the or immediate ( ori ) instruction has the following preferred form for expressing a no-op: ori 0,0,0 invalid instruction forms some of the defined instructions have invalid form s. an instruction form is invalid if one or more fields of the instruction, excluding the opcode field(s), are coded incorrectly in a manner that can be deduced by examining only the instruction encoding. attempts to execute an invalid form of an instruction either causes an illegal instruction type program interrupt or yields boundedly undefined results. any exceptions to this rule are stated in the instruction descriptions. instruction model RM0004 139/1176 some kinds of invalid form instructions can be deduced just from examining the instruction layout. these are listed below. field shown as reserved but coded as nonzero field shown as containing a particular value but coded as some other value these invalid forms are not discussed further. other invalid instruction forms can be deduced by detecting an invalid encoding of one or more of the instruction operand fields. these kinds of invalid form are identified in the instruction descriptions. branch conditional and branch conditional extended instructions (undefined encoding of bo field) load with update instructions ( r d= r a or r a=0) store with update instructions ( r a=0) load multiple instruction ( r a or r b in range of registers to be loaded) load string immediate instructions ( r a in range of registers to be loaded) load string indexed instructions ( r d= r a or r d= r b) load/store floating-point with update instructions ( r a=0) 3.2.3 addressing modes this section describes conventions for addressing memory and for calculating effective addresses (eas) as defined by the book e architecture for 32-bit implementations. memory addressing a program references memory using the effective address computed by the processor when it executes a memory access or branch instruction (or other instructions as described in chapter : user-level cache instructions on page 180 ,? and chapter : supervisor-level cache instruction on page 183 ,? or when it fetches the ne xt sequential instruction. memory operands bytes in memory are numbered consecutively starting with 0. each number is the address of the corresponding byte. memory operands may be bytes, half words, words or, for the load/store multiple and load/store string instructions, a sequence of words or bytes. the address of a memory operand is the address of its first byte (that is, of its lowest-numbered byte). byte ordering can be either big endian or little endian (see chapter : byte ordering on page 141 ? ). the default byte and bit ordering is big endian. operand length is imp licit for each instruction with re spect to memory alignment. the operand of a scalar memory access instruction has a natural alignment boundary equal to the operand length. in other words, the natural address of an operand is an integral multiple of the operand length. a memory operand is said to be aligned if it is aligned at its natural boundary; otherwise it is said to be misaligned. for more information about alignment, see chapter 3.1.2: alignment and misaligned accesses on page 133 .? effective address calculation the 32-bit address computed by the processor when executing a memory access or branch instruction (or certain other instructions described in user-level cache instructions on page 180 ,? supervisor-level cache instruction ,? and supervisor-level tlb management RM0004 instruction model 140/1176 instructions on page 183 ? ), or when fetching the next sequential instruction, is called the effective address (ea) and specifies a byte in memory. for a memory a ccess instruction, if the sum of the ea and the operand length exceeds the maximum ea, the memory access is considered to be undefined. effective address arithmetic, except for next sequential instruction address computations, wraps around from the maximum address, 2 32 ? 1, to address 0. data memory addressing modes book e supports the following data memory addressing modes: base+displacement addressing mode?the 16-bit d field is sign-extended and added to the contents of the gpr designated by r a or to zero if r a = 0. instructions that use this addressing mode are of the d instruction format. base+index addressing mode?the contents of the gpr designated by r b (or the value 0 for lswi and stswi ) are added to the contents of the gpr designated by r a or to zero if r a = 0. instructions that use this addressing mode are of the x instruction format. base+displacement extended addressing mode?the 12-bit de field is sign-extended and added to the contents of the gpr designated by r a or to zero if r a = 0 to produce the 32-bit ea. instructions that use this addressing mode are of the de instruction format. base+displacement extended scaled addr essing mode?the 12-bit des field is concatenated on the right with zeros, sign-extended, and added to the contents of the gpr designated by r a or to zero if r a = 0 to produce the 32-bit ea. instructions that use this addressing mode are of the des instruction format. in addition, apus may provide additional addressing modes. instruction memory addressing modes instruction memory addressing modes correspond with instructions forms, as follows: i-form branch instructions?the 24-bit li field is concatenated on the right with 0b00, sign-extended, and then added to either the address of the branch instruction if aa = 0, or to 0 if aa = 1. taken b-form branch instructions?the 14-bit bd field is concatenated on the right with 0b00, sign-extended, and then added to either the address of the branch instruction if aa = 0, or to 0 if aa = 1. taken xl-form branch instructions?the contents of bits lr[32?61] or cr[32?61] are concatenated on the right with 0b00. sequential instruction fetching (or non-taken branch instructions)?the value 4 is added to the address of the current instruction to form the 32-bit ea of the next instruction. if the address of the current in struction is 0xffff_fffc, the address of the next sequential instruction is undefined. any branch instruction with lk = 1?the value 4 is added to the address of the current instruction and the 32-bit result is placed into the lr. if the address of the current instruction is 0xffff_fffc, the result placed into the lr is undefined. although some implementations may support next sequential instruction address computations wrapping from the highest ad dress 0xffff_fffc to 0x0000_0000 as part of the instruction flow, users are strongly encouraged not to depend on this behavior. doing so can reduce the portability of their software. if code must span this bou ndary, software should place a non-linking branch at address 0xffff_fffc, which always branches to address instruction model RM0004 141/1176 0x0000_0000 (either absolute or relative branches work). see also appendix d: guidelines for 32-bit book e on page 1154 .? byte order i ng if scalars (individual data items and instructions) were indivisible, there would be no such concept as byte ordering. it is meaningless to consider the order of bits or groups of bits within the smallest addressable unit of memory, because nothing can be observed about such order. only when scalars, which the pr ogrammer and processor regard as indivisible quantities, can comprise more than one addressable unit of memory does the question of order arise. for a machine in which the smallest addressable unit of memory is the 64-bit double word, there is no question of the ordering of bytes within double words. all transfers of individual scalars between registers and memory are of double words, and the address of the byte containing the high-order 8 bits of a scalar is no different from the address of a byte containing any other part of the scalar. for book e, as for most computer architectures currently implemented, the smallest addressable unit of memory is the 8-bit byte. many scalars are half words and words (double words in 64-bit implementations) which consist of groups of bytes. when a word-length scalar is moved from a register to memory, the scalar occupies four consecutive byte addresses. it thus becomes meaningful to discuss the order of the byte addresses with respect to the value of the scalar: which byte contains the highest-order eight bits of the scalar, which byte contains the next-highest-order 8 bits, and so on. given a scalar that contains multiple bytes, the choice of byte ordering is essentially arbitrary. there are 4! = 24 ways to specify the ordering of 4 bytes within a word but only two of these orderings are sensible: the ordering that assigns the lowest address to the highest-order (left-most) 8 bits of the scalar, the next sequential address to the next-highest-order eight bits, and so on. this ordering is called big endian because th e big (most-significant) end of the scalar, considered as a binary number, comes first in memory. the 68000 is an example of a processor using this byte ordering. the ordering that assigns the lowest address to the lowest-order (right-most) 8 bits of the scalar, the next sequential address to the next-lowest-order eight bits, and so on. this ordering is called little endian because the little (least-significant) end of the scalar, considered as a binary number, comes first in memory. the intel 8086 is an example of a processor using this byte ordering. book e provides support for both big- and little-endian byte ordering in the form of a memory attribute. see chapter 5.4.8: permission attributes on page 315 ,? and chapter 5.2.1: memory/cache access attributes on page 283 .? synchronization requirements this section describes synchronization requ irements for special registers and tlbs. changing the value in certain system registers and invalidating tlb entries can have the side effect of altering the context in which data addresses and instruction addresses are interpreted, and in which instructions are executed. for example, changing msr[is] = 0 to and msr[is] = 1 has the side effect of changing address space. such effects need not occur in program order (program order refers to the execution of instructions in the strict order in which they occur in the program), and therefore may require explicit synchronization by software. RM0004 instruction model 142/1176 an instruction that alters the context in which data addresses or instruction addresses are interpreted, or in which instructions are executed, is called context altering. this section covers all such context-altering instructions. the required software synchronization for each is shown in ta bl e 6 4 . the notation ?csi? in the tables means any context-synchronizing instruction (such as, sc , isync , rfci , or rfi ). a context-synchronizing interrupt (that is, any interrupt except non- recoverable machine check) can be used instead of a context-synchronizing instruction. if it is, phrases like ?the synchronizing instruction,? below, should be interpreted as meaning the instruction at which the interrupt occurs. if no software synchronization is required before (after) a context-altering instruction, ?the synchronizing instruction before (after) the context- altering instruction? should be interpreted as meaning the context-altering instruction itself. the synchronizing instruction before the context-altering instruction ensures that all instructions up to and including that synchronizing instruction are fetched and executed in the context that existed before the alteration. the synchronizing instruction after the context- altering instruction ensures that all instructions after that synchronizing instruction are fetched and executed in the context established by the alteration. instructions after the first synchronizing instruction, up to and including the second synchronizing instruction, may be fetched or executed in either context. if a sequence of instructions contains context-altering instructions and contains no instructions that are affected by any of the context alterations, no software synchronization is required within the sequence. note: sometimes advantage can be taken of the fact that certain instructions that occur naturally in the program, such as the rfi / rfci at the end of an interrupt handler, provide the required synchronization. no software synchronization is required before altering the msr (except perhaps when altering the we bit: see the tables), because mtmsr is execution synchronizing. no software synchronization is required before most of the other alterations shown in the ? instruction fetch and/or execution ? section in ta b l e 6 4 , because all instructions before the context- altering instruction are fetched and decoded before the context-altering instruction executes (the processor must determine whether any of the preceding instructions are context synchronizing) ta bl e 6 4 identifies the software synchronization requirements for data access for all context- altering instructions. table 64. synchronization requirements context altering instruction or event required before required after notes data accesses interrupt none none mtmsr (ds) none csi mtmsr (me) none csi (1) mtmsr (pr) none csi mtspr (dac1, dac2, dvc1, dvc2) ? ? (2) mtspr (dbcr0, dbcr2) ? ? 2 mtspr (dbsr) ? ? 2 instruction model RM0004 143/1176 mtspr (pid n )csicsi rfci none none rfi none none sc none none tlbivax csi csi or msync (3),(4) tlbwe csi csi or msync 3,4 instruction fetch and/or execution interrupt none none mtmsr (ce) none none (5) mtmsr (de) none csi mtmsr (ee) none none 3 mtmsr (fe0) none csi mtmsr (fe1) none csi mtmsr (fp) none csi mtmsr (is) none csi (6) mtmsr (me) none csi 1 mtmsr (pr) none csi mtmsr (we) ? ? (7) mtspr (dbcr0, dbcr1) ? ? 2 mtspr (dbsr) ? ? 2 mtspr (dec) none none (8) mtspr (iac1, iac2, iac3, iac4) ? ? 2 mtspr (ivori) none none mtspr (ivpr) none none mtspr (pid) none csi 6 mtspr (tcr) none none 8 mtspr (tsr) none none 8 rfci none none rfi none none sc none none tlbivax none csi or msync 3,4 tlbwe none csi or msync 3,4 wrtee none none 5 wrteei none none 5 table 64. synchronization requirements (continued) context altering instruction or event required before required after notes RM0004 instruction model 144/1176 context synchronization an instruction or event is context synchronizing if it satisfies the requirements listed below. context-synchronizing operations include instructions isync , sc , rfi , rfci , rfdi , and rfmci , and most interrupts. 1. the operation is not initiated or, in the case of isync , does not complete until all instructions already in execution have completed to a point at which they have reported all exceptions they cause. 2. the instructions that precede the operation complete execution in the context (including such parameters as privilege leve l, address space, and memory protection) in which they were initiated. 3. if the operation directly causes an interrupt (for example, sc directly causes a system call interrupt) or is an interrupt, the operatio n is not initiated unt il no interrupt-causing 1. a context synchronizing instruction is required after altering msr[me] to ensure that the alteration takes effect for subsequent machine check interrupts, wh ich may not be recoverable and therefore may not be context synchronizing. 2. synchronization requirements fo r changing any of the debug register s are implementation-dependent and are specified in the user?s manual for the implementation. 3. for data accesses, the context sy nchronizing instruction before the tlbwe or tlbivax instruction ensures that all storage accesses due to preceding instructio ns have completed to a point at which they have reported all exceptions they cause. the context synchronizing instruction after the tlbwe or tlbivax ensures that subsequent storage accesses (data and instruction) use the updated value in any affected tlb entries. it does not ensure that all storage accesses previously tr anslated by the tlb entries being updated have completed with respect to storage; if these completions must be ensured, the tlbwe or tlbiva x must be followed by an msync instruction as well as by a context synchronizing instruction. the following sequence shows why it is necessary for data accesses to ensure that all storage accesses due to instructions before a tlbwe or tlbivax have co mpleted to a point at wh ich they have reported all exceptions they will cause. assume that valid tl b entries exist for the target storage location when the sequence starts. 1. a program issues a l oad or store to a page. 2. the same program executes a tlbwe or tlbivax that invalidates the corresponding tlb entry. 3. the load or store instruction finally executes, and gets a tlb miss exception. the tlb miss exception is semantically incorrect. in order to prevent it, a c ontext synchronizing instruction must be executed between steps 1 and 2. 4. multiprocessor systems have other requirements to synch ronize what is called tlb shoot down? (that is, to invalidate one or more tlb entries on all processors in the multiprocessor system and to be able to determine that the invalidations have completed and that all side effects of the invalidations have taken effect). 5. the effect of changing msr[ee] or msr[ce] is immediate. if an mtmsr , wrtee , or wrteei clears msr[ee], an external input, de crementer, or fixed-interval timer interrupt does not occur afte r the instruction executes. if an mtmsr , wrtee , or wrteei changes msr[ee] from 0 to 1 when an external input, decrementer, fixed- interval timer, or higher priority enabled exception exists, the corresponding interrupt occurs immediately after the mtmsr , wrtee , or wrteei executes and before the next instruct ion is executed in the program that sets msr[ee]. if an mtmsr clears msr[ce], a critical input, or watchdog timer interrupt does not occur after the instruction is executed. if an mtmsr changes msr[ce] from 0 to 1 when a critical input, watchdog timer, or higher priority enabled exception exists, the corresponding inte rrupt occurs immediately after mt msr executes, and before the next instruction is executed in the program that set msr[ce]. 6. the alteration must not cause an implicit branch in real address space. thus the real address of the context-altering instruction and of each subsequent instruction, up to and including the next context synchronizing instruction, must be independent of whether the alteration has taken effect. 7. synchronization requirements for changing the wait state enable are implementation-dependent, and are specified in the user?s manual for the implementation. 8. the elapsed time between the decrementer reaching zero, or the transition of the selected time base bit for the fixed-interval timer or the watchdog timer, and the signalling of the decrementer, fixed-interval timer or the watchdog timer exception is not defined. instruction model RM0004 145/1176 exception exists having higher priority than the exception associated with the interrupt. see chapter 4.11: exception priorities on page 278 .? 4. the instructions that follow the operation are fetched and executed in the context established by the operation as required by the sequential execution model. (this requirement dictates that any prefetched instructions be discarded and that any effects and side effects of executing them speculat ively may also be discarded, except as described in memory access ordering on page 290 .? a context-synchronizing operation is necessarily execution synchronizing. unlike msync and mbar , such operations do not affect the order of memory accesses with respect to other mechanisms. execution synchronization an instruction is execution synchronizing if it satisfies items 1 and 2 of the definition of context synchronization . msync is treated like isync with respect to item 1 (that is, the conditions described in item 1 apply to completion of msync ). execution synchronizing instructions include msync , mtmsr , wrtee , and wrteei . all context-synchronizing instructions are execution synchronizing. unlike a context-synchronizing operation, an execution synchronizing instruction need not ensure that the instructions following it execute in the context established by that execution synchronizing instruction. this new context becomes effective sometime after the execution synchronizing instruction completes and before or at a subsequent context-synchronizing operation. instruction-related interrupts interrupts are caused either directly by the execution of an instruction or by an asynchronous event. in either case, an exception may cause one of several types of interrupts to be invoked. examples of interrupts that can be caused directly by the execution of an instruction include but are not limited to the following: an attempt to execute a reserved-illegal inst ruction (illegal instruction exception-type program interrupt) an attempt by an application program to execute a privileged instruction (privileged instruction exception-type program interrupt) an attempt by an application program to access a privileged spr (privileged instruction exception-type program interrupt) an attempt by an application program to access an spr that does not exist (unimplemented operation instruction exception-type program interrupt) an attempt by a system program to access an spr that does not exist (boundedly undefined) execution of a defined instru ction using an invalid form (illegal instruction exception- type program interrupt, unimplemented operation exception-type program interrupt, or privileged instruction exception-type program interrupt) an attempt to access a memory location that is either unavailable (instruction tlb error interrupt or data tlb error interrupt) or not permitted (instruction storage interrupt or data storage interrupt) an attempt to access memory with an ea alignment not supported by the implementation (alignment interrupt) execution of a system call instruction (system call interrupt) RM0004 instruction model 146/1176 execution of a trap instruction whose trap condition is met (trap type program interrupt) execution of a floating-point instruction when floating-point instructions are unavailable (floating-point unav ailable interrupt) execution of a floating-point instruction that causes a floating-point enabled exception to exist (floating-point enabled exception-type program interrupt) execution of a defined instruction that is no t implemented by the im plementation (illegal instruction exception or unimplemented operation exception-type program interrupt) execution of an allocated instruction that is not implemented by the implementation (illegal instruction excepti on or unimplemented operation exception-type program interrupt) execution of an allocated instruction when the auxiliary instruction is unavailable (auxiliary processor unavailable interrupt). execution of an allocated instruction th at causes an auxiliary enabled exception (enabled exception-type program interrupt). apus, such as the spe, may defi ne additional instruct ion-caused excepti ons and interrupts. the invocation of an interrupt is precise, except that if one of the imprecise modes for invoking the floating-point enabled exception-type program interrupt is in effect the invocation of the floating-point enabled exception-type program interrupt may be imprecise. when the interrupt is invoked imprecisely, the excepting instruction does not appear to complete before the next instruction starts (because one of the effects of the excepting instruction, namely the invocation of the interrupt, has not yet occurred). chapter 4: interrupts and exceptions on page 244 describes interrupt conditions in detail. 3.3 instruction set overview this section provides a brief overview of the book e and book e instructions. note: some instructions have the following optional features: cr update?the dot ( . ) suffix on the mnemonic enables the update of the cr. overflow option?the o suffix indicates that the overflow bit in the xer is enabled. 3.3.1 book e user-l evel instructions this section discusses the user-level instructions defined in the book e architecture. integer instructions this section describes the integer instructions. these consist of the following: integer arithmetic instructions integer compare instructions integer logical instructions integer rotate and shift instructions integer instructions use the content of the gprs as source operands and place results into gprs and the xer and cr fields. integer arithmetic instructions ta bl e 6 5 lists the integer arithmetic instructions for the powerpc processors. instruction model RM0004 147/1176 although there is no subtract immediate instruction, its effect can be achieved by using an addi instruction with the immediate operand negated. simplified mnemonics are provided that include this negation. subtract instructions subtract the second operand ( r a) from the third operand ( r b). simplified mnemonics are provided in which the third operand is subtracted from the second. see appendix b: simplified mnemonics for powerpc instructions on page 1110 ,? for examples. according to book e, an implementation that executes instructions with the overflow exception enable bit (oe) set or that sets the carry bit (ca) can either execute these instructions slowly or prevent execution of the subsequent instruction until the operation completes. the summary overflow (so) and overflow (ov) bits in the xer are set to reflect an overflow condition of a 32-bit result only if the instruction?s oe bit is set. integer compare instructions the integer compare instructions algebraically or logically compare the contents of register r a with either the zero-extended value of the uimm operand, the sign-extended value of the simm operand, or the contents of r b. the comparison is signed for cmpi and cmp and table 65. integer arithmetic instructions name mnemonic syntax add add ( add. addo addo. ) r d ,r a ,r b add carrying addc ( addc. addco addco. ) r d ,r a ,r b add extended adde ( adde. addeo addeo. ) r d ,r a ,r b add immediate addi r d ,r a,simm add immediate carrying addic r d ,r a,simm add immediate carrying and record addic. r d ,r a,simm add immediate shifted addis r d ,r a,simm add to minus one extended addme ( addme. addmeo addmeo. ) r d ,r a add to zero extended addze ( addze. addzeo addzeo. ) r d ,r a divide word divw ( divw. divwo divwo. ) r d ,r a ,r b divide word unsigned divwu divwu. divwuo divwuo. r d ,r a ,r b multiply high word mulhw ( mulhw. ) r d ,r a ,r b multiply high word unsigned mulhwu ( mulhwu. ) r d ,r a ,r b multiply low immediate mulli r d ,r a,simm multiply low word mullw ( mullw. mullwo mullwo. ) r d ,r a ,r b negate neg ( neg. nego nego. ) r d ,r a subtract from subf ( subf. subfo subfo. ) r d ,r a ,r b subtract from carrying subfc ( subfc. subfco subfco. ) r d ,r a ,r b subtract from extended subfe ( subfe. subfeo subfeo. ) r d ,r a ,r b subtract from immediate carrying subfic r d ,r a,simm subtract from minus one extended subfme ( subfme. subfmeo subfmeo. ) r d ,r a subtract from zero extended subfze ( subfze. subfzeo subfzeo. ) r d ,r a RM0004 instruction model 148/1176 unsigned for cmpli and cmpl . ta bl e 6 6 lists integer compare instructions. note that the l bit must be 0 for 32-bit implementations. the cr d operand can be omitted if the result of the comparison is to be placed in cr0. otherwise the target cr field must be specified in cr d by using an explicit field number. for information on simplified mnemonics for the integer compare instructions see appendix b: simplified mnemonics for powe rpc instructions on page 1110 .? integer logical instructions the logical instructions shown in ta b l e 6 7 perform bit-parallel operations on the specified operands. logical instructions with the cr updating enabled (uses dot suffix) and instructions andi. and andis. set cr field cr0 to characterize the result of the logical operation. logical instructions do not affect xer[so], xer[ov], or xer[ca]. see appendix b ,? for simplified mnemonic examples for integer logical operations. table 66. integer 32-bit compare instructions (l = 0) name mnemonic syntax compare cmp cr d,l, r a, r b compare immediate cmpi cr d,l, r a,simm compare logical cmpl cr d,l, r a, r b compare logical immediate cmpli cr d,l, r a,uimm table 67. integer logical instructions name mnemonic syntax implementation notes and and ( and. ) r a ,r s ,r b? and immediate andi .r a ,r s , uim m ? and immediate shifted andis .r a ,r s , uim m ? and with complement andc ( andc. ) r a ,r s ,r b? count leading zeros word cntlzw (cntlzw. ) r a ,r s? equivalent eqv ( eqv. ) r a ,r s ,r b? extend sign byte extsb ( extsb. ) r a ,r s? extend sign half word extsh ( extsh. ) r a ,r s? nand nand ( nand. ) r a ,r s ,r b? nor nor ( nor. ) r a ,r s ,r b? or or ( or. ) r a ,r s ,r b? or immediate ori r a ,r s , uim m book e defines ori r0,r0,0 as the preferred form for a no-op. the dispatcher may discard this instruction and dispatch it only to the completion queue but not to any execution unit. instruction model RM0004 149/1176 integer rotate and shift instructions rotation operations are performed on data from a gpr, and the result, or a portion of the result, is returned to a gpr. integer rotate instructions, summarized in ta bl e 6 8 , rotate the contents of a register. the result is either inserted into the target register under control of a mask (if a mask bit is set the associated bit of the rotated data is placed into the target register, and if the mask bit is cleared the asso ciated bit in the target register is unchanged) or anded with a mask before being placed into the target register. appendix b: simplified mnemonics for powerpc instructions on page 1110 ,? lists simplified mnemonics that allow simpler coding of often used functions such as clearing the left- or right-most bits of a register, left or right justifying an arbitrary field, and simple rotates and shifts. the integer shift instructions ( ta bl e 6 9 ) perform left and right shifts. immediate-form logical (unsigned) shift operations are obtained by specifying masks and shift values for certain rotate instructions. simpli fied mnemonics (shown in appendix b: simplified mnemonics for powerpc instructions ? ) are provided to simplify coding of such shifts. multiple-precision shifts can be programmed as shown in c.2: multiple-precision shifts on page 1148 .? the integer shift instruct ions are summarized in ta b l e 6 9 . floating-point instructions this section describes the floating-point instructions as they are defined by book e. or immediate shifted oris r a ,r s , uim m ? or with complement orc ( orc. ) r a ,r s ,r b? xor xor ( xor. ) r a ,r s ,r b? xor immediate xori r a ,r s , uim m ? xor immediate shifted xoris r a ,r s , uim m ? table 68. integer rotate instructions name mnemonic syntax rotate left word immediate then and with mask rlwinm ( rlwinm. ) r a ,r s , sh , mb , me rotate left word then and with mask rlwnm ( rlwnm. ) r a ,r s ,r b , mb , me rotate left word imme diate then mask insert rlwimi ( rlwimi. ) r a ,r s , sh , mb , me table 69. integer shift instructions name mnemonic syntax shift left word slw ( slw. ) r a ,r s ,r b shift right word srw ( srw. ) r a ,r s ,r b shift right algebraic word immediate srawi ( srawi. ) r a ,r s , sh shift right algebraic word sraw ( sraw. ) r a ,r s ,r b table 67. integer logical instructions (continued) name mnemonic syntax implementation notes RM0004 instruction model 150/1176 the rules followed in assigning new primary and extended opcodes. primary opcode 63 is used for the double-precision arithmetic instructions as well as miscellaneous instructions (for example, f pscr manipulation instructions). primary opcode 59 is used for the single-precision arithmetic instructions. the single-precision instructio ns for which there is a corresponding double-precision instruction have the same format and extended opcode as that double-precision instruction. in assigning new extended opcodes for primary opcode 63, the following regularities are maintained. in addition, all new x-form instructions in primary opcode 63 have bits 21?22 = 11. ? bit 26 = 1 if and only if the instruction is a-form. ? bits 26?29 = 0b0000 if and only if the instruction is a comparison or mcrfs (if and only if the instruction sets an explicitly designated cr field). ? bits 26?28 = 0b001 if and only if the instruction explicitly refers to or sets the fpscr (that is, is an fpsc r instruction) and is not mcrfs . ? bits 26?30 = 0b01000 if and only if the instruction is a move register instruction, or any other instruction that does not refer to or set the fpscr. in assigning extended opcodes for primary opcode 59, the following regularities have been maintained. they are based on those rules for primary opcode 63 that apply to the instructions having primary opcode 59. in particular, primary opcode 59 has no fpscr instructions, so the corresponding rule does not apply. ? if there is a corresponding instruction with primary opcode 63, its extended opcode is used. ? bit 26 = 1 if and only if the instruction is a form. ? bits 26?30 = 0b01000 if and only if the instruction is a move register instruction, or any other instruction that does not refer to or set the fpscr. floating-point load instructions there are two basic forms of load instruction: single-precision and double-precision. because the fprs support only floating-point double format, single-precision load floating- point instructions convert single-precision data to double format prior to loading the operand into the target fpr. the conversion and loading steps are as follows. let word 0:31 be the floating-point single-precision operand accessed from memory. normalized operand if word 1:8 > 0 and word 1:8 < 255 then fpr( fr d) 0:1 word 0:1 fpr( fr d) 2 ? word 1 fpr( fr d) 3 ? word 1 fpr( fr d) 4 ? word 1 fpr( fr d) 5:63 word 2:31 || 29 0 denormalized operand if word 1:8 = 0 and word 9:31 0 then sign word 0 exp -126 frac 0:52 0b0 || word 9:31 || 29 0 normalize the operand do while frac 0 = 0 frac frac 1:52 || 0b0 instruction model RM0004 151/1176 exp exp - 1 fpr( fr d) 0 sign fpr( fr d) 1:11 exp + 1023 fpr( fr d) 12:63 frac 1:52 zero/infinity/nan if word 1:8 = 255 or word 1:31 = 0 then fpr( fr d) 0:1 word 0:1 fpr( fr d) 2 word 1 fpr( fr d) 3 word 1 fpr( fr d) 4 word 1 fpr( fr d) 5:63 word 2:31 || 29 0 for double-precision load floating-point instru ctions, conversion is not required because the data from memory is copied directly into the fpr. many floating-point load instructions have an update form, in which gpr( r a) is updated with the ea. for these forms, if r a 0 and r a r d, the ea is placed into gpr( r a) and the memory element (byte, half word, word, or double word) addressed by ea is loaded into fpr( r d). if r a=0 or r a= r d, the instruction form is invalid. floating-point load accesses cause a data storage interrupt if the program is not allowed to read the location. floating-point load memory accesses cause a data tlb error interrupt if the program attempts to access memory that is unavailable. the floating-point load instruction set is shown in ta b l e 7 0 . floating-point store instructions table 70. floating-point load instruction set instruction mne monic syntax load floating-point double lfd fr d , d( r a) load floating-point double with update lfdu fr d , d( r a) load floating-point double extended lfde fr d , des( r a) load floating-point double with update extended lfdue fr d , des( r a) load floating-point double indexed lfdx fr d ,r a ,r b load floating-point double with update indexed lfdux fr d ,r a ,r b load floating-point double indexed extended lfdxe fr d ,r a ,r b load floating-point double with update indexed extended lfduxe fr d ,r a ,r b load floating-point single lfs fr d , d( r a) load floating-point single with update lfsu fr d , d( r a) load floating-point single extended lfse fr d , des( r a) load floating-point single with update extended lfsue fr d , des( r a) load floating-point single indexed lfsx fr d ,r a ,r b load floating-point single with update indexed lfsux fr d ,r a ,r b load floating-point single indexed extended lfsxe fr d ,r a ,r b load floating-point single with update indexed extended lfsuxe fr d ,r a ,r b RM0004 instruction model 152/1176 there are three basic forms of store instruction: single-precision, double-precision, and integer. the integer form is provided by the optional store floating-point as integer word instruction ( stfiwx ), described in chapter 6: instruction set on page 330 .? because the fprs support only floating-point double format for floating-point data, single-precision store floating-point instructions convert double-precision data to single-precision format before storing the operand. the conversion steps are as follows. let word 0:31 be the word in memory written to. no denormalization required (includes zero / infinity / nan) if fpr(frs) 1:11 > 896 or fpr(frs) 1:63 = 0 then word 0:1 fpr(frs) 0:1 word 2:31 fpr(frs) 5:34 denormalization required if 874 frs 1:11 896 then sign fpr(frs) 0 exp fpr(frs) 1:11 ? 1023 frac 0b1 || fpr(frs) 12:63 denormalize operand do while exp < ?126 frac 0b0 || frac 0:62 exp exp + 1 word 0 sign word 1:8 0x00 word 9:31 frac 1:23 else word undefined note that if the value to be stored by a single-precision store floating-point instruction exceeds the maximum number representable in single-precision format, the first case above (no denormalization required) applies. the result stored in word is then a well-defined value, but is not numerically equal to the value in the source register (that is, the result of a single-precision load floating-point from word does not compare equal to the contents of the original source register). for double-precision store floating-point instructions and for the store floating-point as integer word instruction, no conversion is required, as the data from the fpr is copied directly into memory. many floating-point store instructions have an update form, in which gpr( r a) is updated with the ea. for these forms, if r a 0, the ea is placed into gpr( r a). floating-point store accesses cause a data storage interrupt if the program is not allowed to write to the location. integer store accesses cause a data tlb error interrupt if the program attempts to access memory that is unavailable. store instructions are shown in ta bl e 7 1 . book e supports both big-endian and little-endian byte ordering. table 71. floating-point store instructions instruction mnemonic syntax store floating-point double stfd fr s , d( r a) store floating-point double with update stfdu fr s , d( r a) store floating-point double extended stfde fr s , des( r a) store floating-point double with update extended stfdue fr s , des( r a) instruction model RM0004 153/1176 floating-point move instructions described in ta bl e 7 2 , these instructions copy data from one fpr to another, altering the sign bit (bit 0) as described below for fneg , fabs , and fnabs . these instructions treat nans just like any other kind of value (for example, the sign bit of a nan may be altered by fneg , fabs , and fnabs ). these instructions do not alter the fpscr. store floating-point double indexed stfdx fr s ,r a ,r b store floating-point double with update indexed stfdux fr s ,r a ,r b store floating-point double indexed extended stfdxe fr s ,r a ,r b store floating-point double with update indexed extended stfduxe fr s ,r a ,r b store floating-point as integer word indexed stfiwx fr s ,r a ,r b store floating-point as integer word indexed extended stfiwxe fr s ,r a ,r b store floating-point single stfs fr s , d( r a) store floating-point single with update stfsu fr s , d( r a) store floating-point single extended stfse fr s , des( r a) store floating-point single with update extended stfsue fr s , des( r a) store floating-point single indexed stfsx fr s ,r a ,r b store floating-point single with update indexed stfsux fr s ,r a ,r b store floating-point single indexed extended stfsxe fr s ,r a ,r b store floating-point single with update indexed extended stfsuxe fr s ,r a ,r b table 72. floating-point move instructions instruction mnemonic syntax floating absolute value fabs [.] fr d ,fr b floating move register fmr [ . ] fr d ,fr b floating negative absolute value fnabs [ . ] fr d ,fr b floating negate fneg [ . ] fr d ,fr b table 71. floating-point store instructions (continued) instruction mnemonic syntax RM0004 instruction model 154/1176 floating-point arithmetic instructions the following sections describe elementary arithmetic, multiply-add, rounding/conversion, compare, and status/control instructions. floating-point elementary arithmetic instructions ta bl e 7 3 lists mnemonics and syntax of floating-point elementary arithmetic instructions. floating-point multiply-add instructions these instructions combine a multiply and an add operation without an intermediate rounding operation. fpscr status bits, described in ta bl e 7 4 are set as follows: overflow, underflow, and inexact exception bits, the fr, fi, and fprf fields are set based on the final result of the operation, not on the result of the multiplication. invalid operation exception bits are set as if the multiplication and the addition were performed using two separate instructions ( fmul [ s ], followed by fadd [ s ] or fsub [ s ]). that is, any of the following actions will ca use appropriate exception bits to be set: ? multiplication of infinity by 0 ? multiplication of anything by an snan ? addition of anything with an snan table 73. floating-point elementary arithmetic instructions instruction mnemonic syntax floating add fadd [ . ] fr d ,fr a ,fr b floating add single fadds [ . ] fr d ,fr a ,fr b floating divide fdiv [ . ] fr d ,fr a ,fr b floating divide single fdivs [ . ] fr d ,fr a ,fr b floating multiply fmul [ . ] fr d ,fr a ,fr c floating multiply single fmuls [ . ] fr d ,fr a ,fr c floating reciprocal estimate single fres [ . ] fr d ,fr b floating reciprocal square root estimate frsqrte [ . ] fr d ,fr b floating square root fsqrt [ . ] fr d ,fr b floating square root single fsqrts [ . ] fr d ,fr b floating subtract fsub [ . ] fr d ,fr a ,fr b floating subtract single fsubs [ . ] fr d ,fr a ,fr b table 74. floating-point multiply-add instructions instruction mnemonic instruction floating multiply-add fmadd [ . ] fr d ,fr a ,fr b ,fr c floating multiply-add single fmadds [ . ] fr d ,fr a ,fr b ,fr c floating multiply-subtract fmsub [ . ] fr d ,fr a ,fr b ,fr c floating multiply-subtract single fmsubs [ . ] fr d ,fr a ,fr b ,fr c floating negative multiply-add fnmadd [ . ] fr d ,fr a ,fr b ,fr c instruction model RM0004 155/1176 floating-point rounding and conversion instructions floating-point compare instructions the floating-point compare instructions compare the contents of two fprs. comparison ignores the sign of zero (that is, regards +0 as equal to ?0). the comparison result can be ordered or unordered. the comparison sets one bit in the designated cr field and clears the other three. the floating-point condition code, fpscr[fpcc], is set in the same way. the cr field and the fpcc are set as described in ta bl e 7 6 . the floating-point compare and select instruction set is shown in ta bl e 7 7 . floating negative multiply-add single fnmadds [ . ] fr d ,fr a ,fr b ,fr c floating negative multiply-subtract fnmsub [ . ] fr d ,fr a ,fr b ,fr c floating negative multiply-subtract single fnmsubs [ . ] fr d ,fr a ,fr b ,fr c table 75. floating-point rounding and conversion instructions instruction mnemonic syntax floating convert from integer double word fcfid fr d ,fr b floating convert to integer double word fctid fr d ,fr b floating convert to integer double word and round to zero fctidz fr d ,fr b floating convert to integer word fctiw [ . ] fr d ,fr b floating convert to integer word and round to zero fctiwz [ . ] fr d ,fr b floating round to single-precision frsp [ . ] fr d ,fr b table 76. cr field settings bit name description 0fl ( fr a) < ( fr b) 1fg ( fr a) > ( fr b) 2fe ( fr a) = ( fr b) 3fu ( fr a) ? ( fr b) (unordered) table 77. floating-point compare and select instructions instruction mnemonic syntax floating compare ordered fcmpo cr d ,fr a ,fr b floating compare unordered fcmpu cr d ,fr a ,fr b floating select fsel fsel. fr d ,fr a ,fr b ,fr c fr d ,fr a ,fr b ,fr c table 74. floating-point multiply-add instructions (continued) instruction mnemonic instruction RM0004 instruction model 156/1176 floating-point status and control register instructions every fpscr instruction synchronizes the effects of all floating-point instructions executed by a given processor. executing a fpscr instruction ensures that all floating-point instructions previously initiated by the give n processor have completed before the fpscr instruction is initiated, and that no subsequent floating-point instructio ns are initiated by the given processor until the fpscr instruction completes. in particular: all exceptions caused by the previously in itiated instructions are recorded in the fpscr before the fpscr in struction is initiated. all invocations of floating-point enabled exception-type program interrupt that will be caused by the previously initiated instru ctions have occurred before the fpscr instruction is initiated. no subsequent floating-point instruction that depends on or alters the settings of any fpscr bits is initiated until the fpscr instruction has completed. floating-point load and floating-point store instructions ( ta b l e 7 8 ) are not affected. load and store instructions load and store instructions are issued and translated in program order; however, the accesses can occur out of order. synchronizing instructions are provided to enforce strict ordering. the following load and store instructions are defined: integer load instructions integer store instructions integer load and store with byte-reverse instructions integer load and store multiple instructions memory synchronization instructions spe apu load and store instru ctions for reading and writ ing 64-bit gprs. some of these instructions are also implemented by processors that support the embedded vector single-precision and embedded scalar double-precision floating-point apus, which use the extended 64-bit gprs. see chapter 3.6.1 on page 186 .? self-modifying code when a processor modifies any memory location that can contain an instruction, software must ensure that the instruction cache is made consistent with data memory and that the table 78. floating-point status and control register instructions instruction mnemonic syntax move from fpscr mffs mffs. fr d fr d move to fpscr bit 0 mtfsb0 mtfsb0. crb d crb d move to fpscr bit 1 mtfsb1 mtfsb1. crb d crb d move to fpscr fields mtfsf mtfsf. fm ,fr b fm ,fr b move to fpscr field immediate mtfsfi mtfsfi. cr d,imm cr d,imm instruction model RM0004 157/1176 modifications are made visible to the instruction fetching mechanism. this must be done even if the cache is disabled or if the page is marked caching-inhibited. the following instruction sequence can be used to accomplish this when the instructions being modified are in memory that is memory-coherence required and one processor both modifies the instructions and executes them. (additional synchronization is needed when one processor modifies instructions that another processor will execute.) the following sequence synchronizes the instruction stream (using either dcbst or dcbf ): dcbst (or dcbf )|update memory msync |wait for update icbi |remove (invalidate) copy in instruction cache msync |ensure the icbi invalidate is complete isync |remove copy in own instruction buffer these operations are required because the da ta cache is a write-back cache. because instruction fetching bypasses the data cache, changes to items in the data cache cannot be reflected in memory until the fetch operations complete. the msync after the icbi is required to ensure that the icbi invalidation has completed in the instruction cache. special care must be taken to avoid coherency paradoxes in systems that implement unified secondary caches, and designers should carefully follow the guidelines for maintaining cache coherency discussed in the user?s manual. integer load and store address generation integer load and store operations generate eas using register indirect with immediate index mode, register indirect with index mode, or register indirect mode, which are described as follows: register indirect with immediate index addressing for integer loads and stores. instructions using this addressing mode contain a signed 16-bit immediate index (d operand), which is sign extended and added to the contents of a general-purpose register specified in the instruction ( r a operand), to generate the ea. if r0 is specified, a value of zero is added to the immediate index (d operand) in place of the contents of r0 . the option to specify r a or 0 is shown in the instruction descriptions as ( r a|0). figure 6 shows how an ea is generated using this mode. RM0004 instruction model 158/1176 figure 6. register indirect with immediate index addressing for integer loads/stores register indirect with index addressing for integer loads and stores. instructions using this mode cause the contents of two gprs (specified as operands r a and r b) to be added in the ea generation. a zero in place of the r a operand causes a zero to be added to the gpr contents specified in operand r b. the option to specify r a or 0 is shown in the instruction descriptions as ( r a|0). figure 7 shows how an ea is generated using this mode. figure 7. register indirect with index addressing for integer loads/stores register indirect addressing for integer loads and stores. instructions using this addressing mode use the contents of the gpr specified by the r a operand as the ea. no 0 15 16 31 sign extension d 32 63 gpr ( r a) 0 32 63 gpr ( r d/ r s) store load ye s instruction encoding: 05610111516 31 opcode r d/ r s r ad + 0 31 effective address r a=0? memory interface no 32 63 gpr ( r a) 0 + 32 63 gpr ( r d/ r s) memory interface store load ye s 0 31 gpr ( r b) instruction encoding: r a=0? 0 31 effective address 056101115162021 3031 opcode r d/ r s r a r b subopcode 0 reserved instruction model RM0004 159/1176 a zero in the r a operand generates an ea of zero. the option to specify r a or 0 is shown in the instruction descriptions as ( r a|0). figure 8 shows how an ea is generated using this mode. figure 8. register indirect addressing for integer loads/stores see effective address calculation on page 139 ,? for information about calculating eas. note that in some implementations, operations that are not naturally aligned can suffer performance degradation. chapter 4.7.6: alignment interrupt on page 263 , for additional information about load and store address alignment interrupts. register indirect integer load instructions for integer load instructions, the byte, half word, or word addressed by the ea is loaded into r d. many integer load instructions have an update form, in which r a is updated with the generated ea. for these forms, if r a 0 and r a r d (otherwise invalid), the ea is placed into r a and the memory element (byte, half word, or word) addressed by the ea is loaded into r d. note that the book e architecture defines load with update instructions with operand r a = 0 or r a= r d as invalid forms. integer load instructions table 79. integer load instructions name mnemonic syntax load byte and zero lbz r d ,d(r a ) load byte and zero indexed lbzx r d ,r a ,r b load byte and zero with update lbzu r d ,d(r a ) load byte and zero with update indexed lbzux r d ,r a ,r b load half word and zero lhz r d ,d(r a ) load half word and zero indexed lhzx r d ,r a ,r b no store load ye s 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 instruction encoding: 0561011151620213031 r a=0? 32 63 gpr ( r a) 031 effective address opcode r d/ r s r a nb subopcode 0 32 63 gpr ( r d/ r s) memory interface reserved RM0004 instruction model 160/1176 integer store instructions for integer store instructions, the r s contents are stored into the byte, half word, word or double word in memory addressed by the ea. many store instructions have an update form in which r a is updated with the ea. for these forms, the following rules apply: if r a 0, the ea is placed into r a. if r s= r a, the contents of register r s are copied to the target memory element and the generated ea is placed into r a ( r s). the book e architecture defines store with update instructions with r a = 0 as an invalid form. in addition, it defines integer store instructions with the cr update option enabled (rc field, bit 31, in the instruction encoding = 1) to be an invalid form. ta bl e 8 0 summarizes integer store instructions. integer load and store with byte-reverse instructions load half word and zero with update lhzu r d ,d(r a ) load half word and zero with update indexed lhzux r d ,r a ,r b load half word algebraic lha r d ,d(r a ) load half word algebraic indexed lhax r d ,r a ,r b load half word algebraic with update lhau r d ,d(r a ) load half word algebraic with update indexed lhaux r d ,r a ,r b load word and zero lwz r d ,d(r a ) load word and zero indexed lwzx r d ,r a ,r b load word and zero with update lwzu r d ,d(r a ) load word and zero with update indexed lwzux r d ,r a ,r b table 80. integer store instructions name mnemonic syntax store byte stb r s ,d(r a ) store byte indexed stbx r s ,r a ,r b store byte with update stbu r s ,d(r a ) store byte with update indexed stbux r s ,r a ,r b store half word sth r s ,d(r a ) store half word indexed sthx r s ,r a ,r b store half word with update sthu r s ,d(r a ) store half word with update indexed sthux r s ,r a ,r b store word stw r s ,d(r a ) store word indexed stwx r s ,r a ,r b store word with update stwu r s ,d(r a ) store word with update indexed stwux r s ,r a ,r b table 79. integer load instructions (continued) name mnemonic syntax instruction model RM0004 161/1176 ta bl e 8 1 describes integer load and store with byte-reverse instructions. these books were defined in part to support the original powerpc definition of little-endian byte ordering. note that book e supports true little endian on a per-page basis. for more information, see byte ordering on page 141 .? integer load and store multiple instructions the load/store multiple instructions are used to move blocks of data to and from the gprs. the load multiple and store multiple instructions can have operands that require memory accesses crossing a 4-kbyte page boundary. as a result, these instructions can be interrupted by a data storage interrupt associated with the address translation of the second page. note: if one of these instructions is interrupted, it may be restarted, r equiring multiple memory accesses. the book e architecture defines the load multiple word ( lmw ) instruction ( ta b l e 8 2 ) with r a in the range of registers to be loaded as an invalid form. load and store multiple accesses must be word aligned; otherwise, they cause an alignment exception. integer load and store string instructions the integer load and store string instructions allow movement of data from memory to registers or from registers to memory without concern for alignment. these instructions can be used for a short move between arbitrary memory locations or to initiate a long move between misaligned memory fields. however, in some implementations, these instructions are likely to have greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. ta bl e 8 3 summarizes the integer load and store string instructions. table 81. integer load and store with byte-reverse instructions name mnemonic syntax load half word byte-reverse indexed lhbrx r d ,r a ,r b load word byte-reverse indexed lwbrx r d ,r a ,r b store half word byte-reverse indexed sthbrx r s ,r a ,r b store word byte-reverse indexed stwbrx r s ,r a ,r b table 82. integer load and store multiple instructions name mnemonic syntax load multiple word lmw r d ,d(r a ) store multip le word stmw r s ,d(r a ) table 83. integer load and store string instructions name mnemonic syntax load string word immediate lswi r d ,r a , nb load string word indexed lswx r d ,r a ,r b store string word immediate stswi r s ,r a , nb store string word indexed stswx r s ,r a ,r b RM0004 instruction model 162/1176 load string and store string instructions can involve operands that are not word-aligned. floating-point load and store address generation floating-point load and store operations, listed in ta bl e 8 4 , generate eas using the register indirect with immediate index addressing mode and register indirect with index addressing mode. floating-point loads and stores are not supported for direct-store accesses. the use of floating-point loads and stores for direct-store accesses results in an alignment interrupt. there are two forms of the floating-point load instruction?single-precision and double- precision operand formats. because the fprs support only the floating-point double- precision format, single-precision floating-point load instructions convert single-precision data to double-precision format before loading an operand into an fpr. the floating-point load and store indexed instructions ( lfsx , lfsux , lfdx , lfdux , stfsx , stfsux , stfdx , and stfdux ) are invalid when the rc bit is one. the powerpc architecture defines load with update with r a = 0 as an invalid form. floating-point store instructions this section describes floating-point store instructions. there are three basic forms of the store instruction?single-precision, double-precision, and integer. the integer form is supported by the optional stfiwx instruction. because the fprs support only double- precision format for floating-point data, single-precision floating-point store instructions convert double-precision data to single-precision format before storing the operands. ta bl e 8 5 summarizes the floating-point store instructions. table 84. floating-point load instructions name mnemonic syntax load floating-point single lfs fr d ,d(r a ) load floating-point single indexed lfsx fr d ,r a ,r b load floating-point single with update lfsu fr d ,d(r a ) load floating-point single with update indexed lfsux fr d ,r a ,r b load floating-point double lfd fr d ,d(r a ) load floating-point double indexed lfdx fr d ,r a ,r b load floating-point double with update lfdu fr d ,d(r a ) load floating-point double with update indexed lfdux fr d ,r a ,r b table 85. floating-point store instructions name mnemonic syntax store floating-point single stfs fr s ,d(r a ) store floating-point single indexed stfsx fr s ,r b store floating-point single with update stfsu fr s ,d( ra ) store floating-point single with update indexed stfsux fr s ,r b store floating-point double stfd fr s ,d(r a ) store floating-point double indexed stfdx fr s ,r b instruction model RM0004 163/1176 some floating-point store instructions require conversions in the lsu. ta b l e 8 6 shows conversions the lsu makes when executing a store floating-point single instruction. ta bl e 8 7 shows the conversions made when performing a store floating-point double instruction. most entries in the table indicate that the floating-point value is simply stored. only in a few cases are any other actions taken. branch and flow control instructions some branch instructions can redirect instruction execution conditionally based on the value of bits in the cr. store floating-point double with update stfdu fr s ,d( ra ) store floating-point double with update indexed stfdux fr s ,r b store floating-point as integer word indexed (1) stfiwx fr s ,r b 1. the stfiwx instruction is optional to the book e architecture. table 86. store floating-point single behavior fpr precision data type action single normalized store single denormalized store single zero, infinity, qnan store single snan store double normalized if (exp 896) then denormalize and store, else store double denormalized store zero double zero, infinity, qnan store double snan store table 87. store floating-point double behavior fpr precision data type action single normalized store single denormalized normalize and store single zero, infinity, qnan store single snan store double normalized store double denormalized store double zero, infinity, qnan store double snan store table 85. floating-point store instructions (continued) name mnemonic syntax RM0004 instruction model 164/1176 branch instruction address calculation branch instructions can alter the sequence of instruction execution. instruction addresses are always assumed to be word aligned; the book e processors ignore the two low-order bits of the generated branch target address. branch instructions compute the ea of the next instruction address using the following addressing modes: branch relative branch conditional to relative address branch to absolute address branch conditional to absolute address branch conditional to link register (lr) branch conditional to count register (ctr) branch relative addressing mode instructions that use branch relative addressing generate the next instruction address by sign extending and appending 0b00 to the immediate displacement operand li, and adding the resultant value to the current instruction address. branches using this mode have the absolute addressing option disabled (aa field, bit 30, in the instruction encoding = 0). the lr update option can be enabled (lk field, bit 31, in the instruction encoding = 1). this causes the ea of the instruction following the branch instruction to be placed in the lr. figure 9 shows how the branch target address is generated using this mode. figure 9. branch relative addressing branch conditional to relative addressing mode if branch conditions are met, instructions that use the branch conditional to relative addressing mode generate the next instruction address by sign extending and appending results to the immediate displacement operand (bd) and adding the resultant value to the current instruction address. branches using this mode have the absolute addressing option disabled (aa field, bit 30, in the instruction encoding = 0). the lr update option can be enabled (lk field, bit 31, in the instruction encoding = 1). this option causes the ea of the instruction following the branch inst ruction to be placed in the lr. figure 10 shows how the branch target address is generated using this mode. 056 293031 18 li aa lk 0 31 branch target address instruction + 0 31 current instruction address 056 293031 li 0 0 sign extension reserved encoding: instruction model RM0004 165/1176 figure 10. branch conditional relative addressing branch to absolute addressing mode instructions that use branch to absolute addressing mode generate the next instruction address by sign extending and appending 0b00 to the li operand. branches using this addressing mode have the absolute addressing option enabled (aa field, bit 30, in the instruction encoding = 1). the lr update option can be enabled (lk field, bit 31, in the instruction encoding = 1). this option causes the ea of the instruction following the branch instruction to be placed in the lr. figure 11 shows how the branch target address is generated using this mode. figure 11. branch to absolute addressing 0 5 6 1011 15 16 30 31 16 bo bi bd aa lk ye s 031 branch target address instruction no + 0 31 current instruction address 0 31 next sequential instruction address 01516293031 sign extension bd 0 0 condition met? reserved encoding: 056 293031 18 li aa lk 056 293031 0 29 30 31 branch target address instruction li 0 0 sign extension 00 encoding: RM0004 instruction model 166/1176 branch conditional to absolute addressing mode if the branch conditions are met, instructions that use the branch conditional to absolute addressing mode generate the next instruction address by sign extending and appending 0b00 to the bd operand. branches using this addressing mode have the absolute addressing option enabled (aa field, bit 30, in the instruction encoding = 1). the lr update option can be enabled (bit 31 (lk) in the instruction encoding = 1). this option causes the ea of the instruction following the branch instruction to be placed in the lr. figure 12 shows how the branch target address is generated using this mode. figure 12. branch conditional to absolute addressing branch conditional to link register addressing mode if the branch conditions are met, the branch conditional to lr instruction generates the next instruction address by fetching the contents of the lr and clearing the two low-order bits to zero. the lr update option can be enabled (lk field, bit 31, in the instruction encoding = 1). this option causes the ea of the instruction following the branch instruction to be placed in the lr. figure 13 shows how the branch target address is generated using this mode. figure 13. branch conditional to link register addressing 05610111516 293031 16 bo bi bd aa lk 01516293031 0293031 branch target address instruction no 0 31 next sequential instruction address sign extension bd 0 0 condition met? ye s 00 encoding: 0 56 1011 1516 2021 3031 condition met? 00 30 31 lr 0 29 031 branch target address instruction no 0 31 next sequential instruction address ye s 19 bo bi 0 0 0 0 0 16 lk || reserved encoding: instruction model RM0004 167/1176 branch conditional to count register addressing mode if the branch conditions are met, the branch conditional to count register instruction generates the next instruction address by fetching the contents of the count register (ctr) and clearing the two low-order bits to zero. the lr update option can be enabled (lk field, bit 31, in the instruction encoding = 1). this option causes the ea of the instruction following the branch instruction to be placed in the lr. figure 14 shows how the branch target address is generated when using this mode. figure 14. branch conditional to count register addressing conditional branch control note: some processors do not implement the static branch prediction defined in book e and described here. for those processors, the bo operand is ignored for branch prediction. for branch conditional instructions, the bo operand specifies the conditions under which the branch is taken. the first four bits of the bo operand specify how the branch is affected by or affects the condition and count registers. the fifth bit, shown in ta b l e 8 9 as having the value y , is used by some implementations for branch prediction as described below. the encodings for the bo operands are shown in ta b l e 8 9 . 00 30 31 ctr 029 031 branch target address instruction condition met? no ye s 0 31 next sequential instruction address 0 5 6 1011 15 16 20 21 30 31 19 bo bi 00000 528 lk || reserved encoding: table 88. bo bit descriptions bo bits description 0 setting this bit causes the cr bit to be ignored. 1 bit value to test against 2 setting this causes the decrement to not be decremented. 3 setting this bit reverses the sense of the ctr test. 4 used for the y bit, which provides a hint about whether a conditional branch is likely to be taken and may be used by some implementations to improve performance. RM0004 instruction model 168/1176 the branch always encoding of the bo operand does not have a y bit. clearing the y bit indicates a predicted behavior for the branch instruction as follows: for bc x with a negative value in the displacement operand, the branch is taken. in all other cases ( bc x with a non-negative value in the displacement operand, bclr x , or bcctr x ), the branch is not taken. setting the y bit reverses the preceding indications. the sign of the displacement operand is used as described above even if the target is an absolute address. the default value for the y bit should be 0 and should be set to 1 only if software has determined that the prediction corresponding to y = 1 is more likely to be correct than the prediction corresponding to y = 0. software that does not compute branch predictions should clear the y bit. in most cases, the branch should be predicted to be taken if the value of the following expression is 1, and predicted to fall through if the value is 0. ((bo[0] & bo[2]) | s) bo[4] in the expression above, s (bit 16 of the branch conditional instruction coding) is the sign bit of the displacement operand if the instruction has a displacement operand and is 0 if the operand is reserved. bo[4] is the y bit, or 0 for the branch always encoding of the bo operand. (advantage is taken of the fact that, for bclr x and bcctr x , bit 16 of the instruction is part of a reserved operand and therefore must be 0.) the 5-bit bi operand in branch conditional instru ctions specifies which cr bit represents the condition to test. the cr bit selected is bi +32, as shown in ta b l e 1 7 . if the branch instructions contain immediate addressing operands, the target addresses can be computed sufficiently ahead of the branch instruction that instructions can be fetched along the target path. if the branch instructions use the link and count registers, instructions along the target path can be fetched if the link or count register is loaded sufficiently ahead of the branch instruction. table 89. bo operand encodings bo description 0000 y decrement the ctr, then branch if the decremented ctr 0 and the condition is false. 0001 y decrement the ctr, then branch if the decr emented ctr = 0 and the condition is false. 001 zy branch if the condition is false. 0100 y decrement the ctr, then branch if the decremented ctr 0 and the condition is true. 0101 y decrement the ctr, then branch if the dec remented ctr = 0 and the condition is true. 011 zy branch if the condition is true. 1 z 00 y decrement the ctr, then branch if the decremented ctr 0. 1 z 01 y decrement the ctr, then branch if the decremented ctr = 0. 1 z 1 zz branch always. in this table, z indicates a bit that is ignored. note that the z bits should be cleared, as they may be assigned a meaning in some future version of the architecture. the y bit provides a hint about wh ether a conditional branch is like ly to be taken and may be used by some implementations to improve performance. instruction model RM0004 169/1176 branching can be conditional or unconditional, and optionally a branch return address is created by storing the ea of the instruction fo llowing the branch instru ction in the lr after the branch target address has been computed. this is done regardless of whether the branch is taken. branch instructions ta bl e 9 0 lists branch instructions provided by the book e processors. a set of simplified mnemonics and symbols is provided for the most frequently used forms of branch conditional, compare, trap, rotate and shift, and certain other instructions. see appendix b: simplified mnemonics for powerpc instructions on page 1110 .? note that the eis defines the integer select instruction, isel , which can be used to more efficiently handle sequences with multiple conditional branches. its syntax is given in chapter 3.6.2 .? a detailed description including an example of how isel can be used can be found in chapter 7.1.2 on page 824 .? condition register (cr) logical instructions cr logical instructions, shown in ta bl e 9 1 , and the move condition register field ( mcrf ) instruction are also defined as flow control instructions. note that if the lr update option is enabled for any of these instructions, the book e architecture defines these forms of the instructions as invalid. table 90. branch instructions name mnemonic syntax branch b ( ba bl bla ) target_addr branch conditional bc ( bca bcl bcla ) bo , bi,target_addr branch conditional to link register bclr ( bclrl ) bo , bi branch conditional to count register bcctr ( bcctrl ) bo , bi table 91. condition register logical instructions name mnemonic syntax condition register and crand crb d ,crb a ,crb b condition register or cror crb d ,crb a ,crb b condition register xor crxor crb d ,crb a ,crb b condition register nand crnand crb d ,crb a ,crb b condition register nor crnor crb d ,crb a ,crb b condition register equivalent creqv crb d ,crb a ,crb b condition register and with complement crandc crb d ,crb a ,crb b condition register or with complement crorc crb d ,crb a ,crb b move condition register field mcrf crf d ,crf s RM0004 instruction model 170/1176 trap instructions the trap instructions shown in ta bl e 9 2 test for a specified set of conditions. if any of the conditions tested by a trap instruction are met, the system trap type program interrupt is taken. for more information, see chapter 4.7.7: program interrupt on page 265 .? if the tested conditions are not met, instruction execution continues normally. see appendix b: simplified mnemonics for powerpc instructions on page 1110 .? system linkage instruction the system call ( sc ) instruction permits a program to call on the system to perform a service; see ta bl e 9 3 and system linkage instructions on page 182 .? executing this instruction causes the system call interrupt handler to be invoked. for more information, see chapter 4.7.9 .? processor control instructions processor control instructions are used to read from and write to the cr, machine state register (msr), and special-purpose registers (sprs). move to/from condition register instructions ta bl e 9 4 summarizes the instructions for reading from or writing to the cr. move to/from special-purpose register instructions ta bl e 9 5 lists the mtspr and mfspr instructions. table 92. trap instructions name mnemonic syntax trap word immediate twi to ,r a , simm tr a p wo r d tw to ,r a ,r b table 93. system linkage instruction name mnemonic syntax system call sc ? table 94. move to/from condition register instructions name mnemonic syntax move to condition register fields mtcrf crm ,r s move to condition register from xer mcrxr cr d move from condition register mfcr r d table 95. move to/from special-purpose register instructions name mnemonic syntax move to special-purpose register mtspr spr ,r s move from special-purpose register mfspr r d , spr instruction model RM0004 171/1176 ta bl e 9 6 summarizes all sprs defined in book e, indicating which are user-level access. the spr number column lists register numbers used in the instruction mnemonics. table 96. book e special-purpose registers (by spr abbreviation) spr name defined spr number access supervisor only section/ page decimal binary csrr0 critical save/restore register 0 58 00001 11010 read/write yes on page 82 csrr1 critical save/restore register 1 59 00001 11011 read/write yes on page 82 ctr count register 9 00000 01001 read/write no on page 68 dac1 data address compare 1 316 01001 11100 read/write yes chapter 2.13.4 dac2 data address compare 2 317 01001 11101 read/write yes chapter 2.13.4 dbcr0 debug control register 0 308 01001 10100 read/write yes on page 108 dbcr1 debug control register 1 309 01001 10101 read/write yes on page 110 dbcr2 debug control register 2 310 01001 10110 read/write yes on page 113 dbsr debug status register 304 01001 10000 read/clear (1) ye s chapter 2.13.2 dear data exception address register 61 00001 11101 read/write yes on page 82 dec decrementer 22 00000 10110 read/write yes chapter 2.8.4 decar decrementer auto-reload 54 00001 10110 write-only yes chapter 2.8.5 dvc1 data value compare 1 318 01001 11110 read/write yes chapter 2.13.5 dvc2 data value compare 2 319 01001 11111 esr exception syndrome register 62 00001 11110 read/write yes on page 84 iac1 instruction address compare 1 312 01001 11000 read/write yes chapter 2.13.3 iac2 instruction address compare 2 313 01001 11001 read/write yes chapter 2.13.3 iac3 instruction address compare 3 314 01001 11010 read/write yes chapter 2.13.3 iac4 instruction address compare 4 315 01001 11011 read/write yes chapter 2.13.3 ivor0 critical input 400 01100 10000 read/write yes on page 83 ivor1 critical input interrupt offset 401 01100 10001 read/write yes on page 83 ivor2 data storage interrupt offset 402 01100 10010 read/write yes on page 83 ivor3 instruction storage interrupt offset 403 01100 10011 read/write yes on page 83 ivor4 external input interrupt offset 404 01100 10100 read/write yes on page 83 ivor5 alignment interrupt offset 405 01100 10101 read/write yes on page 83 RM0004 instruction model 172/1176 ivor6 program interrupt offset 406 01100 10110 read/write yes on page 83 ivor7 floating-point unavailable interrupt offset 407 01100 10111 read/write yes on page 83 ivor8 system call interrupt offset 408 01100 11000 read/write yes on page 83 ivor9 auxiliary processor unavailable interrupt offset 409 01100 11001 read/write yes on page 83 ivor10 decrementer interrupt offset 410 01100 11010 read/write yes on page 83 ivor11 fixed-interval timer interrupt offset 411 01100 11011 read/write yes on page 83 ivor12 watchdog timer interrupt offset 412 01100 11100 read/write yes on page 83 ivor13 data tlb error interrupt offset 413 01100 11101 read/write yes on page 83 ivor14 instruction tlb error interrupt offset 414 01100 11110 read/write yes on page 83 ivor15 debug interrupt offset 415 01100 11111 read/write yes on page 83 ivpr interrupt vector 63 00001 11111 read/write yes chapter 2.13.3 lr link register 8 00000 01000 read/write no chapter 2.5.2 pid process id register (2) 48 00001 10000 read/write yes chapter 2.12.1 pir processor id register 286 01000 11110 read only yes chapter 2.7.3 pvr processor version register 287 01000 11111 read only yes chapter 2.7.4 sprg0 spr general 0 272 01000 10000 read/write yes chapter 2.10 sprg1 spr general 1 273 01000 10001 read/write yes chapter 2.10 sprg2 spr general 2 274 01000 10010 read/write yes chapter 2.10 sprg3 spr general 3 259 01000 00011 read only no (3) chapter 2.10 275 01000 10011 read/write yes chapter 2.10 sprg4 spr general 4 260 01000 00100 read only no chapter 2.10 276 01000 10100 read/write yes chapter 2.10 sprg5 spr general 5 261 01000 00101 read only no chapter 2.10 277 01000 10101 read/write yes chapter 2.10 sprg6 spr general 6 262 01000 00110 read only no chapter 2.10 278 01000 10110 read/write yes chapter 2.10 sprg7 spr general 7 263 01000 00111 read only no chapter 2.10 279 01000 10111 read/write yes chapter 2.10 srr0 save/restore register 0 26 00000 11010 read/write yes on page 81 srr1 save/restore register 1 27 00000 11011 read/write yes on page 81 table 96. book e special-purpose registers (by spr abbreviation) (continued) spr name defined spr number access supervisor only section/ page decimal binary instruction model RM0004 173/1176 ta bl e 9 7 lists eis-specific sprs, indicating which can be accessed by user-level software. compilers should reco gnize spr names when parsing instructions. tbl time base lower 268 01000 01100 read only no chapter 2.8.3 284 01000 11100 write-only yes chapter 2.8.3 tbu time base upper 269 01000 01101 read only no chapter 2.8.3 285 01000 11101 write-only yes chapter 2.8.3 tcr timer control register 340 01010 10100 read/write yes chapter 2.8.1 tsr timer status register 336 01010 10000 read/clear (4) ye s chapter 2.8.2 usprg 0 user spr general 0 (5) 256 01000 00000 read/write no chapter 2.10 xer integer exception register 1 00000 00001 read/write no chapter 2.3.2 1. the dbsr is read using mfspr . it cannot be directly written to. instead, dbsr bits corresponding to 1 bits in the gpr can be cleared using mtspr . 2. implementations may support more than one pid. if mult iple pids are implemented, the book e?defined pid is implemented as pid0. 3. user-mode read access to sprg3 is implementation-dependent. 4. the tsr is read using mfspr . it cannot be directly written to. instead, ts r bits corresponding to 1 bits in the gpr can be cleared using mtspr. 5. usprg0 is a separate physi cal register from sprg0. table 96. book e special-purpose registers (by spr abbreviation) (continued) spr name defined spr number access supervisor only section/ page decimal binary table 97. implementation-specific sprs (by spr abbreviation) spr name spr number access supervisor only section/page atbl alternate time base lower 526 read-only no chapter 2.15 atbu alternate time base upper 527 read-only no chapter 2.15 dsrr0 debug save/restore register 0 574 r/w yes on page 86 dsrr1 debug save/restore register 1 575 r/w yes on page 86 ivor32 spe/embedded floating-point apu unavailable interrupt offset 528 read/write yes on page 83 ivor33 embedded floating-point data exception interrupt offset 529 read/write yes on page 83 ivor34 embedded floating-point round exception interrupt offset 530 read/write yes on page 83 ivor35 performance monitor 531 read/write yes on page 83 l1cfg0 l1 cache configuration register 0 515 read-only no chapter 2.11.3 l1cfg1 l1 cache configuration register 1 516 read-only no chapter 2.11.3 l1csr0 l1 cache control and stat us register 0 1010 read/write yes chapter 2.11.1 l1csr1 l1 cache control and stat us register 1 1011 read/write yes chapter 2.11.2 RM0004 instruction model 174/1176 l1finv0 l1 flush and invalidate cont rol register 0 1016 read/write yes chapter 2.11.5 mas0 mmu assist register 0 624 read/write yes on page 101 mas1 mmu assist register 1 625 read/write yes on page 101 mas2 mmu assist register 2 626 read/write yes on page 101 mas3 mmu assist register 3 627 read/write yes on page 104 mas4 mmu assist register 4 628 read/write yes on page 104 mas5 mmu assist register 5. 629 read/write yes on page 104 mas6 mmu assist register 6 630 read/write yes on page 104 mas7 mmu assist register 7 944 read/write yes on page 107 mcar machine check address register 573 read-only yes on page 107 mcsr machine check syndrome register 572 read/write yes on page 88 mcsrr0 machine-check save/restore register 0 570 read/write yes on page 88 mcsrr1 machine-check save/restore register 1 571 read/write yes on page 88 mmucfg mmu configuration register 1015 read-only yes chapter 2.12.3 mmucsr0 mmu control and status register 0 1012 read/write yes chapter 2.12.2 pid0 process id register 0. book e defines only this pid register and refers to as pid, not pid0. 48 read/write yes chapter 2.12.1 pid1 process id register 1 633 read/write yes chapter 2.12.1 pid2 process id register 2 634 read/write yes chapter 2.12.1 spefscr signal processing and embedded floating- point status and control register 512 read/write no chapter 2.14.1 svr system version register 1023 read-only yes chapter 2.7.5 tlb0cfg tlb configuration register 0 688 read-only yes chapter 2.12.4 tlb1cfg tlb configuration register 1 689 read-only yes chapter 2.12.4 table 97. implementation-specific sprs (by spr abbreviation) (continued) spr name spr number access supervisor only section/page instruction model RM0004 175/1176 memory synchronization instructions memory synchronization instructions control the order in which memory operations complete with respect to asynchronous events and the order in which memory operations are seen by other mechanisms that access memory. see ta bl e 9 8 for a summary. table 98. memory synchronization instructions name mnemonic syntax eis notes instruction synchronize isync ? refetch serializing. an isync waits for previous instructions (including any interrupts they generate) to complete before isync executes, which purges all instructions from the processor and refetches the next instruction. isync does not wait for pending stores in the store queue to complete. any subsequent instruction sees all ef fects of instructions before the isync . because it prevents execution of subsequent instructions until preceding instructions complete, if an isync follows a conditional branch that depends on the value returned by a preceding load, the load on which the branch depends is performed before any loads caused by instructions after the isync even if the effects of the dependency are independent of the value loaded (for example, the value is compared to itself and the branch tests selected, cr n [eq]), and even if the branch target is the next sequent ial instruction to be executed. load word and reserve indexed lwarx r d ,r a ,r b lwarx with stwcx. can emulate semaphore operations such as test and set, compare and swap, exchange memory, and fetch and add. both instructions must use the same ea. reservation granularity is implementation-dependent. executing lwarx and stwcx. to a page marked write-through (wimg = 10 xx ) or when the data cache is locked may cause a data storage interrupt. if the location is not word-aligned, an alignment interrupt occurs. memory barrier mbar mo mbar provides a pipelined memory barrier. (note that mbar uses the same opcode as eieio , which is not defined by book e.) the behavior of mbar is affected by the mo field (bits 6? 10) of the instruction. mo = 0? mbar behaves identically to msync . mo = 1? mbar is a weaker, faster memory barrier; see the user?s manual for implementation-specific behavior. RM0004 instruction model 176/1176 atomic update primitives using lwarx and stwcx. the lwarx and stwcx. instructions together permit atomic update of a memory location. book e provides word and double word forms of each of these instructions. described here is the operation of lwarx and stwcx. a specified memory location that may be modi fied by other processors or mechanisms requires memory coherence. if the location is in write-through required or caching inhibited memory, the implementation determines whether these instructions function correctly or cause the system data storage error handler to be invoked. note the following: the memory coherence required attribute on other processors and mechanisms ensures that their stores to the specified location will caus e the reservation created by the lwarx to be cancelled. warning: support for load and reserve and store conditional instructions for which the specified location is in caching-inhibited me mory is being phased out of book e. it is likely not to be provided on future implementations. new programs should not use these instructions to access caching inhibited memory. a lwarx instruction is a load from a word-aligned location with the following side effects. a reservation for a subsequent stwcx. instruction is created. the memory coherence mechanism is notified that a reservation exists for the location accessed by the lwarx . memory synchronize msync ? provides an ordering function for the effects of all instructions executed by the processor executing the msync . executing an msync ensures that all previous instructions complete before it completes and that no subsequent instructions are initiated until after it comple tes. it also creates a memory barrier, which orders the storage accesses associated with these instructions. msync cannot complete before storage accesses associated with previous instructions are performed. msync is execution synchronizing. note the following: msync is used to ensure that all stores into a data structure caused by store instructions execut ed in a critical section of a program are performed with respect to another processor before the store that releases the lock is performed with respect to that processor. mbar is preferable in many cases. on st book e devices: unlike a context-synchronizing operations, msync does not discard prefetched instructions. store word conditional indexed stwcx. r s ,r a ,r b lwarx with stwcx. can emulate semaphore operations such as test and set, compare and swap, exchange memory, and fetch and add. both instructions must use the same ea. reservation granularity is implementation-dependent. executing lwarx and stwcx. to a page marked write-through (wimg = 10 xx ) or cache-inhibited (wimg = 01 xx ) when the data cache is locked may cause a data storage interrupt. if the location is not word-aligned, an alignment interrupt occurs. table 98. memory synchronization instructions (continued) name mnemonic syntax eis notes instruction model RM0004 177/1176 the stwcx. is a store to a word-aligned location that is conditioned on the existence of the reservation created by the lwarx and on whether both instructions specify the same location. to emulate an atomic operation, both lwarx and stwcx. must access the same location. lwarx and stwcx. are ordered by a dependence on the reservation, and the program is not required to insert other instructions to maintain the order of memory accesses caused by these two instructions. a stwcx. performs a store to the target location only if the location accessed by the lwarx that established the reservation has not been stored into by another processor or mechanism between supplying a value for the lwarx and storing the value supplied by the stwcx. . if the instructions specify different locations, the store is not necessarily performed. cr0 is modified to indicate whether the store was performed, as follows: cr0[lt,gt,eq,so] = 0b00 || store_performed || xer[so] if a stwcx. completes but does not perform the store because a reservation no longer exists, cr0 is modified to indicate that the stwcx. completed without altering memory. a stwcx. that performs its store is said to succeed. examples using lwarx and stwcx. are given in appendix c: programming examples on page 1143 .? a successful stwcx. to a given location may complete before its store has been performed with respect to other processors and mechanisms. as a result, a subsequent load or lwarx from the given location on another processor may return a stale value. however, a subsequent lwarx from the given location on the other processor followed by a successful stwcx. on that processor is guaranteed to have returned the value stored by the first processor?s stwcx . (in the absence of other stores to the given location). reservations the ability to emulate an atomic operation using lwarx and stwcx. is based on the conditional behavior of stwcx. , the reservation set by lwarx , and the clearing of that reservation if the target location is modified by another processor or mechanism before the stwcx. performs its store. a reservation is held on an aligned unit of real memory called a reservation granule. the size of the reservation granule is implementation-dependent, but is a multiple of 4 bytes for lwarx . the reservation granule associated with ea contains the real address to which the ea maps. (?real_addr(ea)? in the rtl for the load and reserve and store conditional instructions stands for ?real address to which ea maps.?) when one processor holds a reservation and another processor performs a store, the first processor?s reservation is cleared if the store affects any bytes in the reservation granule. note: one use of lwarx and stwcx. is to emulate a compare and swap primitive like that provided by the ibm system/370 compare and swap instruction, which checks only that the old and current values of the word being tested are equal, with the result that programs that use such a compare and swap to control a shared resource can err if the word has been modified and the old value is subsequently restored. the use of lwarx and stwcx. improves on such a compare and swap, because the reservation reliably binds lwarx and stwcx. together. the reservation is always lost if the word is modified by another processor or mechanism between the lwarx and stwcx. , so the stwcx. never succeeds unless the word has not been stored into (by another processor or mechanism) since the lwarx . RM0004 instruction model 178/1176 a processor has at most one reservation at any time. book e states that a reservation is established by executing a lwarx and is lost (or may be lost, in the case of the fourth and fifth bullets) if any of the following occurs. the processor holding the reservation executes another lwarx ; this clears the first reservation and establishes a new one. the processor holding the reservation executes any stwcx. , regardless of whether the specified address matches that of the lwarx . another processor executes a store or dcbz to the same reservation granule. another processor executes a dcbtst , dcbst , or dcbf to the same reservation granule; whether the reservation is lost is undefined. another processor executes a dcba to the reservation granule. the reservation is lost if the instruction causes the target block to be newly established in the data cache or to be modified; otherwise, whether the reservation is lost is undefined. some other mechanism modifies a location in the same reservation granule. other implementation-specific conditions may also cause the reservation to be cleared, see the core reference manual. interrupts are not guaranteed to clear reservations. (however, system software invoked by interrupts may clear reservations.) in general, programming conventions must ensure that lwarx and stwcx. specify addresses that match; a stwcx. should be paired with a specific lwarx to the same location. situations in which a stwcx. may erroneously be issued after some lwarx other than that with which it is intended to be paired must be scrupulously avoided. for example, there must not be a context switch in which the processor holds a reservation in behalf of the old context, and the new context resumes after a lwarx and before the paired stwcx. . the stwcx. in the new context might succeed, which is not what was intended by the programmer. such a situation must be prevented by issuing a stwcx. to a dummy writable word-aligned location as part of the context switch, thereby clearing any reservation established by the old context. executing stwcx. to a word-aligned location is enough to clear the reservation, regardless of whether it was set by lwarx . forward progress forward progress in loops that use lwarx and stwcx. is achieved by a cooperative effort among hardware, operating system software, and application software. book e guarantees one of the following when a processor executes a lwarx to obtain a reservation for location x and then a stwcx. to store a value to location x: 1. the stwcx. succeeds and the value is written to location x. 2. the stwcx. fails because some other processor or mechanism modified location x. 3. the stwcx. fails because the processor?s reservation was lost for some other reason. in cases 1 and 2, the system as a whole makes progress in the sense that some processor successfully modifies location x. case 3 covers reservation loss required for correct operation of the rest of the system. this includes cancellation caused by some other processor writing elsewhere in the reservation granule for x, as well as cancellation caused by the operating system in managing certain limited resources such as real memory or context switches. it may also include implementation-dependent causes of reservation loss. an implementation may make a forward progress guarantee, defining the conditions under which the system as a whole makes progress. such a guarantee must specify the possible causes of reservation loss in case 3. although book e alone cannot provide such a instruction model RM0004 179/1176 guarantee, the conditions in cases 1 and 2 are necessary for a guarantee. an implementation and operating system can build on them to provide such a guarantee. note that book e does not guarantee fairness. in competing for a reservation, two processors can indefinitely lock out a third. reservation loss due to granularity lock words should be allocated such that contention for the locks and updates to nearby data structures do not cause excessive reservation losses due to false indications of sharing that can occur due to the reservation granularity. a processor holding a reservation on any word in a reservation granule loses its reservation if some other processor stores anywhere in that granule. such problems can be avoided only by ensuring that few such stores occu r. this can most easily be accomplished by allocating an entire granule for a lock and wasting all but one word. reservation granularity may vary for each implementation. there are no architectural restrictions bounding the granularity implementations must support, so reasonably portable code must dynamically allocate aligned and padded memory for locks to guarantee absence of granularity-induced reservation loss. memory control instructions memory control instructions can be classified as follows: user- and supervisor-level cache management instructions. supervisor-level?only translation lookas ide buffer management instructions this section describes the user-level cache management instructions. see supervisor-level memory control instructions on page 183 ,? for information about supervisor-level cache and translation lookaside buffer management instructions. this section does not describe the cache-locking apu instructions, which are described in chapter 3.6.4: cache locking apu on page 200 .? cache management instructions cache management instructions obey the sequential execution model except as described in the example in this section of managing coherence between the instruction and data caches. in the instruction descriptions the statements. ?this instruction is treated as a load? and ?this instruction is treated as a store,? mean that the instruction is treated as a load from or a store to the addressed byte with respect to address translation, memory protection, and the memory access ordering done by msync , mbar , and the other means described in memory access ordering on page 290 .? if caches are combined, the same value should be given for an instruction cache attribute and the corresponding data cache attribute. each implementation provides an efficient way for software to ensure that all blocks that are considered to be modified in the data cache have been copied to main memory before the processor enters any power-saving mode in which data cache contents are not maintained. the means are described in the reference manual for the implementation. it is permissible for an implementation to treat any or all of the cache touch instructions ( icbt , dcbt , or dcbtst ) as no-operations, even if a cache is implemented. RM0004 instruction model 180/1176 the instruction cache is not necessarily kept consistent with the data cache or with main memory. when instructions are modified, software must ensure that the instruction cache is made consistent with data memory and that the modifications are made visible to the instruction fetching mechanism. the following instruction sequence can be used to accomplish this when the instructions being modified are in memory that is memory coherence required and one program both modifies the instructions and executes them. (additional synchronization is needed when one program modifies instructions that another program will execute.) in this sequence, loca tion ?instr? is assumed to contain modified instructions. dcbst instr # update block in main memory msync # order update before invalidation icbi instr # invalidate copy in instr cache msync # order invalidation before discarding prefetched instructions isync # discard prefetched instructions note: because the optimal instruction sequence may vary between systems, many operating systems provide a system service to perform the function described above. as stated above, the ea is translated using tr anslation resources used for data accesses, even though the block being invalidated was copied into the instruction cache based on translation resources used for instruction fetches. user-level cache instructions the instructions listed in ta bl e 9 9 help user-level programs manage on-chip caches if they are implemented. the following sections describe how these operations are treated with respect to the caches. the eis supports the following ct values, defined by the eis: ct = 0 indicates the l1 cache. ct = 1 indicates the i/o cache. (note that some versions of the e500 documentation refer to the i/o cache as a frontside l2 cache.) ct = 2 indicates a backside l2 cache. as with other memory-related instructions, the effects of cache management instructions on memory are weakly-ordered. if the programmer must ensure that cache or other instructions have been performed with respect to all other processors and system mechanisms, an msync must be placed after those instructions. chapter 3.6.4 ,? describes cache-locking apu instructions. table 99. user-level cache instructions name mnemonic syntax descriptions data cache block allocate dcba r a ,r b this instruction is treated as a store with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. a no-op occurs if the cache is disabled or locked, if the page is marked write-through or cache-inhi bited, or if a tlb protection violation occurs. an implementation may chose to no-op the instruction. data cache block flush dcbf r a ,r b this instruction is treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. instruction model RM0004 181/1176 data cache block set to zero dcbz r a ,r b this instruction is treated as a store with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. if the block containing the byte addressed by ea is in the data cache, all bytes of the block are cleared. if the block containing the byte addressed by ea is not in the data cache and is in storage that is not caching inhibited, the block is established in the data cache without fetching the block from main storage and all bytes of the block are cleared. if the block containing the byte addressed by ea is not in the data cache and is in storage that is no t caching inhibited and cannot be established in the cache, then one of the following occurs: all bytes of the area of main storage that corresponds to the addressed block are set to zero an alignment interrupt is taken if the block containing the byte addressed by ea is in storage that is caching inhibited or write through required, one of the following occurs: all bytes of the area of main storage that corresponds to the addressed block are set to zero an alignment interrupt is taken. data cache block store dcbst r a ,r b this instruction is treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. data cache block touch (1) dcbt ct ,r a ,r b this instruction is treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. a no-op occurs if the cache is disabled or locked, if the page is marked write-through or cache-inhi bited, or if a tlb protection violation occurs. an implementation may chose to no-op the instruction. data cache block touch for store 1 dcbtst ct ,r a ,r b depending on the implementation, this instruction is treated as a load or store with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. a no-op occurs if the cache is disabled or locked, if the page is marked write-through or cache-inhi bited, or if a tlb protection violation occurs. an implementation may chose to no-op the instruction. table 99. user-level cache instructions (continued) name mnemonic syntax descriptions RM0004 instruction model 182/1176 3.3.2 supervisor level instructions the book e architecture includes the structure of the memory management model, supervisor-level registers, and the interrupt model. this section describes the supervisor- level instructions defined by the eis. system linkage instructions this section describes the syst em linkage instructions (see table 100 ). the user-level sc instruction lets a user program call on the system to perform a service and causes the processor to take a system call interrupt. the supervisor-level rfi instruction is used for returning from an interrupt handler. the rfci instruction is used for critical interrupts. the eis defines the rfmci for machine check interrupts and rfdi for debug apu interrupts. table 101 lists instructions for accessing the msr. instruction cache block invalidate icbi r a ,r b this instruction is treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. instruction cache block touch icbt ct ,r a ,r b this instruction is treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. a no-op occurs if the cache is disabled or locked, if the page is marked write-through or cache-inhi bited, or if a tlb protection violation occurs. an implementation may chose to no-op the instruction. 1. a program that uses dcbt and dcbtst improperly is less efficient. to improv e performance, hid0[nopti] can be set, which causes dcbt and dcbtst to be no-oped at the cache. they do not cause bus activity and cause onl y a 1-clock execution latency. the default state of this bit is zero , which enables the use of these instructions. table 99. user-level cache instructions (continued) name mnemonic syntax descriptions table 100. system linkage instructions?supervisor-level name mnemonic syntax implementation notes return from interrupt rfi ? rfi is context-synchronizing return from debug interrupt rfdi ? debug interrupt apu. when rfdi is executed, the values in the debug save and restore registers (dsrr0 and dsrr1) are restored. rfdi is context-synchronizing. return from machine check interrupt rfmci ? machine check interrupt apu. when rfmci is executed, the values in the machine check interrupt save and restore registers (mcsrr0 and mcsrr1) are restored. rfmci is context-synchronizing. return from critical interrupt rfci ? when rfci executes, the values in the critical interrupt save and restore registers (csrr0 and csrr1) are restored. rfci is context-synchronizing. system call sc ? the sc instruction is context-synchronizing. instruction model RM0004 183/1176 certain encodings of the spr field of mtspr and mfspr instructions (shown in ta bl e 9 5 ) provide access to supervisor-level sprs. ta b l e 9 6 lists encodings for architecture-defined sprs. encodings for eis-defined, supervisor-level sprs are listed in ta b l e 1 0 2 . simplified mnemonics are provided for mtspr and mfspr . appendix c: programming examples on page 1143, ? describes context synchronization requ irements when altering certain sprs. supervisor-level memory control instructions memory control instructions include the following: cache management instructions (supervisor-level and user-level) translation lookaside buffer management instructions this section describes supervisor-le vel memory control instructions. memory control instructions on page 179 ,? describes user-level memory control instructions. supervisor-level cache instruction table 102 lists the only supervisor-level cache management instruction. see user-level cache instructions on page 180 ,? for cache instructions that provide user- level programs the ability to manage the on-chip caches. supervisor-level tlb management instructions the address translation mechanism is defined in terms of tlbs and page table entries (ptes) book e processors use to locate the logical-to-physical address mapping for a particular access. see chapter 5.4: storage model on page 301 ,? for more information about tlb operations. ta b l e 1 0 3 summarizes the operation of the tlb instructions. table 101. move to/from machine state register instructions name mnemonic syntax description move from machine state register mfmsr r d ? move to machine state register mtmsr r s ? write msr external enable wrtee r s bit 48 of the contents of r s is placed into msr[ee]. other msr bits are unaffected. write msr external enable immediate wrteei e the value of e is placed into msr[ee]. other msr bits are unaffected. table 102. supervisor-level cache management instruction name mnemonic syntax im plementation notes data cache block invalidate dcbi r a ,r b this instruction is treated as a store with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. an implementation may first perform a dcbst operation before invalidating the cache block if the memory is marked as coherency required (wimg = xx1x). RM0004 instruction model 184/1176 table 103. tlb management instructions name mnemonic syntax implementation notes tlb invalidate virtual address indexed tlbivax r a , r b a tlb invalidate operation is performed whenever tlbivax is executed. tlbivax invalidates any tlb entry that corresponds to the virtual address calculated by this instruction as long as iprot is not set; this includes invalidating tlb entries contained in tlbs on other processors and devices in addition to the processor executing tlbivax . thus an invalidate operation is broadcast throughout the c oherent domain of the processor executing tlbivax . see chapter 5.4 on page 301 .? tlb read entry tlbre ? tlbre causes the contents of a single tlb entry to be extracted from the mmu and be placed in the corresponding mas register fields. the entry extracted is specified by the tlbsel, esel and epn fields of mas0 and mas2. the contents extracted from the mmu are placed in mas0?mas3 and mas7. see chapter 5.4.9 on page 317 .? tlb search indexed tlbsx r a , r b tlbsx updates mas conditionally based on the success or failure of a lookup in the mmu. the lookup is controlled by the ea provided by gpr[ r b] specified in the instruction encoding and mas6[sas,spid]. the val ues placed into mas0?mas3 and mas7 differ, depending on whether a successful or unsuccessful search occurred. note that ra=0 is a preferred form for tlbsx and that some st implementations take an illega l instruction exception program interrupt if ra != 0. tlb synchronize tlbsync ? provides an ordering function for the effects of all tlbivax instructions executed by the processor executing the tlbsync instruction, with respect to the memory barrier created by a subsequent msync instruction execut ed by the same processor. executing a tlbsync inst ruction ensures that all of the following occurs: all tlb invalidations caused by tlbivax instructions preceding the tlbsync will have completed on any other processor before any storage accesses associated with data accesses caused by instructions following the msync instruction are performed with respect to that processor. all storage accesses by other processors for which the address was translated using the translati ons being invalidated, will have been performed with respect to the processor executing the msync instruction, to the exte nt required by the associated memory coherence required attributes, before the mbar or msync instruction?s memory barrier is created. see chapter 5.4.9 on page 317 .? tlb write entry tlbwe ? tlbwe causes the contents of certain fields of mas0, mas1, mas2, and mas3 to be written into a tlb entry specified by the tlbsel, esel, and epn fields of mas0 and mas2. if mas7 is implemented, execution of tlbwe causes any mas7[rpn] to be written to the selected tlb entry. see chapter 5.4.9 on page 317 .? instruction model RM0004 185/1176 3.3.3 recommended si mplified mnemonics the description of each instruction includes the mnemonic and a formatted list of operands. book e?compliant assemblers support the mnemonics and operand lists. to simplify assembly language programming, a set of simplified mnemonics and symbols is provided for some of the most frequently used instructions; refer to appendix b: simplified mnemonics for powerpc instructions on page 1110 , for a complete list. programs written to be portable across the various assemblers for the book e architecture should not assume the existence of mnemonics not described in this document. 3.3.4 book e instr uctions with implement ation-specific features book e defines several instructions in a general way, leaving the details of the execution up to the implementation. these are listed in ta bl e 1 0 4 . this section describes how the eis further defines those instructions. see the user documentation for additional implementation-specific behavior. a list of user-level instructions defined by both the classic powerpc architecture and book e can be found in chapter 3.7 .? 3.3.5 eis instructions the eis defines the instructions listed in ta bl e 1 0 5 (with cross references to more detailed descriptions) that extend the book e instruction set in accordance with book e. spe and embedded floating-point apu instructions are listed in ta bl e 1 0 8 and ta bl e 1 1 7 . table 104. implementation-specific instructions summary name mnemonic syntax category move from apid indirect mfapidi ? optional. if not implemented, attempted execution causes an illegal instruction exception type program interrupt. move from device control register mfdcr ? move to device control register mtdcr ? tlb invalidate virtual address indexed tlbivax ra, rb these are described generally in supervisor-level tlb management instructions on page 183 . tlb read entry tlbre ? tlb search indexed tlbsx ra, rb tlb write entry tlbwe ? table 105. eis-defined in structions (except spe and spfp instructions) name mnemonic syntax section #/page data cache block lock clear dcblc ct, r a, r b chapter 3.6.4 data cache block touch and lock set dcbtls ct, r a, r b data cache block touch for store and lock set dcbtstls ct, r a, r b instruction cache block lock clear icblc ct, r a, r b instruction cache block touch and lock set icbtls ct, r a, r b integer select isel r d, r a, r b, cr b chapter 3.6.2 RM0004 instruction model 186/1176 3.3.6 context synchronization context synchronization is achieved by post- and presynchronizing instructions. an instruction is presynchronized by completing all instructions before dispatching the presynchronized instruction. post-synchronizing is implemented by not dispatching any later instructions until the post-synchronize d instruction is completely finished. 3.4 instruction fetching in general, instructions are prefetched from the cache on a cache hit and from memory on a cache miss. prefetched instructions may not be executed if the instruction stream is redirected after instructions are fetched and before they are scheduled for execution. 3.5 memory synchronization the msync instruction provides a memory barrier throughout the memory hierarchy. it waits for preceding data memory accesses to reach the point of coherency (that is, visible to the entire memory hierarchy); then it is broadcast. no subsequent instructions in the stream are initiated until after msync completes. note that msync uses the same opcode as the sync instruction. the msync instruction is described in memory synchronization instructions on page 175 .? see memory access ordering on page 290 ,? for detailed information. 3.6 eis-specific instructions this section described eis-defined instructions that are part of apus or other extensions to the book e architecture. 3.6.1 spe and embedded floating-point apus the spe and the embedded vector single-pre cision and embedded sca lar double-precision apus provide an extended gpr file with 32, 64-bit registers. the 32-bit book e instructions operate on the lower (least si gnificant) 32 bits of the 64 -bit register. spe apu vector instructions and embedded vector spfp treat 64-bit registers as containing two 32-bit elements or four 16-bit elements as described in spe apu instructions on page 188 .? the embedded double-precision floating-point apu uses the extended gprs to hold single, ieee-compliant double -precision operands. move from performance monitor register mfpmr r d,pmrn chapter 3.6.3 move to performance monitor register mtpmr pmrn, r s return from machine check interrupt rfmci ? chapter 3.6.5 return from debug interrupt rfdi ? chapter 3.6.5 table 105. eis-defined instru ctions (except spe and spfp instructions) (continued) name mnemonic syntax section #/page instruction model RM0004 187/1176 however, like 32-bit book e instructions, scalar spfp apu floating-point instructions use bits 32?63 of the gprs to hold 32-bit single-precision operands, as described in embedded vector and scalar floating-point apu instructions on page 196 .? there is no record fo rm of spe or embedded floating-point instruct ions. vector compare instructions store the result of the comparison into the cr. the meaning of the cr bits is now overloaded for vector operations. vector compare instructions specify a cr field and two source registers as well as the type of compare: greater than, less than, or equal. two bits in the cr field are written with the result of the vector compare, one for each element. the two defined bits could be used either by a vector select instruction or by a uisa branch instruction. a partially visible accumulator register is architected for the integer and fractional multiply accumulate spe instructio ns. it is described in chapter 2.14.2 on page 122 .? full descriptions of these instructions can be found in chapter 13 on page 891 .? spe apu instruction architecture this section describes the in struction formats and instruct ions defined by the spe apu. signed fractions in signed fractional format, the n-bit operand is represented in a 1.[n?1] format (1 sign bit, n?1 fraction bits). signed fractional numbers are in the following range: the real value of the binary operand sf[0:n-1] is as follows: the most negative and positive numbers represen table in fractional format are as follows: the most negative number is represented by sf(0) = 1 and sf[1:n?1] = 0 (that is, n=32; 0x8000_0000 = ?1.0). the most positive number is represented by sf(0) = 0 and sf[1:n?1] = all 1s (that is, n=32; 0x7fff_ffff = 1.0 - 2 ?(n?1) ). spe apu?integer and fractional operations figure 15 shows data formats for signed integer and fractional multiplication. note that low word versions of signed saturate and signed modulo fractional instructions are not supported. attempting to execute an opcode corresponding to these instructions causes boundedly undefined results. 1.0 sf 1.0 2 n1 ? () ? ? ? ? sf 1.0 sf 0 () ? ? = sf i () 2 i ? ? i1 = n1 ? + RM0004 instruction model 188/1176 figure 15. integer and fractional operations spe apu instructions spe apu instructions treat 64-b it gprs as being composed of a vector of two 32-bit elements. (some instructions also read or write 16-bit elements.) the spe apu supports a number of forms of multiply and multiply-accumulate operations, and of add and subtract to accumulator operations. the spe supports signed and unsi gned forms, and optional fractional forms. for these instructions, the fractional form does not apply to unsigned forms because integer and fractional forms are identical for unsigned operands. table 106 shows how spe apu vector multiply in struction mnemonics are structured. table 107 defines mnemonic extensions for these instructions. s s s shp lp 2n bits (2n?1)?bit product signed multiplier sign extension s s 0 shp lp 2n bits (2n?1)?bit product signed multiplier zero fill integer fractional signed multiplication n n 2n ? 1 bits table 106. spe apu vector multiply instruction mnemonic structure prefix multiply element data type element accumulate element evm ho he hog heg wh wl wh g wlg w half odd (16x16->32) half even (16x16->32) half odd guarded (16x16- >32) half even guarded (16x16- >32) word high (32x32->32) word low (32x32->32) word high guarded (32x32- >32) word low guarded (32x32- >32) word (32x32->64) usi umi ssi ssf (1) smi smf 1 unsigned saturate integer unsigned modulo integer signed saturate integer signed saturate fractional signed modulo integer signed modulo fractional a aa an aa w an w write to acc write to acc & added acc write to acc & negate acc write to acc & acc in words write to acc & negate acc in words 1. low word versions of signed saturate and signed modulo fracti onal instructions are not supported. attempting to execute an opcode corresponding to these instructi ons causes boundedly undefined results. instruction model RM0004 189/1176 table 108 lists spe apu instructions. table 107. mnemonic extensions for multiply-accumulate instructions extension meaning comments multiply form he half word even 16 16 32 heg half word even guarded 16 16 32, 64-bit final accumulator result ho half word odd 16 16 32 hog half word odd guarded 16 16 32, 64-bit final accumulator result w word 32 32 64 wh word high 32 32 32, high-order 32 bits of product wl word low 32 32 32, low-order 32 bits of product data type smf signed modulo fractional (wrap, no saturate) smi signed modulo integer (wrap, no saturate) ssf signed saturate fractional ssi signed saturate integer umi unsigned modulo integer (wrap, no saturate) usi unsigned saturate integer accumulate options a update accumulator update accumulator (no add) aa add to accumulator add result to accumulator (64-bit sum) aaw add to accumulator (words) add word results to accumulator words (pair of 32-bit sums) an add negated add negated result to accumulator (64-bit sum) anw add negated to accumulator (words) add negated word results to accumulator words (pair of 32-bit sums) table 108. spe apu vector instructions instruction mnemonic syntax bit reversed increment brinc r d ,r a ,r b initialize accumulator evmra r d ,r a multiply half words, even, guar ded, signed, modulo, fractional and accumulate evmhegsmfaa r d ,r a ,r b multiply half words, even, guar ded, signed, modulo, fractional and accumulate negative evmhegsmfan r d ,r a ,r b multiply half words, even, guarded, signed, modulo, integer and accumulate evmhegsmiaa r d ,r a ,r b multiply half words, even, guarded, signed, modulo, integer and accumulate negative evmhegsmian r d ,r a ,r b RM0004 instruction model 190/1176 multiply half words, even, guard ed, unsigned, modulo, integer and accumulate evmhegumiaa r d ,r a ,r b multiply half words, even, guard ed, unsigned, modulo, integer and accumulate negative evmhegumian r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, fractional and accumulate evmhogsmfaa r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, fractional and accumulate negative evmhogsmfan r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, integer and accumulate evmhogsmiaa r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, integer and accumulate negative evmhogsmian r d ,r a ,r b multiply half words, odd, guarded, unsigned, modulo, integer and accumulate evmhogumiaa r d ,r a ,r b multiply half words, odd, guarded, unsigned, modulo, integer and accumulate negative evmhogumian r d ,r a ,r b vector absolute value evabs r d ,r a vector add immediate word evaddiw r d ,r b , uimm vector add signed, modulo, integer to accumulator word evaddsmiaaw r d ,r a ,r b vector add signed, saturate, integer to accumulator word evaddssiaaw r d ,r a vector add unsigned, modulo, integer to accumulator word evaddumiaaw r d ,r a vector add unsigned, saturate, integer to accumulator word evaddusiaaw r d ,r a vector add word evaddw r d ,r a ,r b vector and evand r d ,r a ,r b vector and with complement evandc r d ,r a ,r b vector compare equal evcmpeq cr d ,r a ,r b vector compare greater than signed evcmpgts cr d ,r a ,r b vector compare greater than unsigned evcmpgtu cr d ,r a ,r b vector compare less than signed evcmplts cr d ,r a ,r b vector compare less than unsigned evcmpltu cr d ,r a ,r b vector convert floating-point from signed fraction evfscfsf r d ,r b vector convert floating-point from signed integer evfscfsi r d ,r b vector convert floating-point from unsigned fraction evfscfuf r d ,r b vector convert floating-point from unsigned integer evfscfui r d ,r b vector convert floating-point to signed fraction evfsctsf r d ,r b vector convert floating-point to signed integer evfsctsi r d ,r b vector convert floating-point to signed integer with round toward zero evfsctsiz r d ,r b vector convert floating-point to unsigned fraction evfsctuf r d ,r b table 108. spe apu vector in structions (continued) instruction mnemonic syntax instruction model RM0004 191/1176 vector convert floating-point to unsigned integer evfsctui r d ,r b vector convert floating-point to unsigned integer with round toward zero evfsctuiz r d ,r b vector count leading sign bits word evcntlsw r d ,r a vector count leading zeros word evcntlzw r d ,r a vector divide word signed evdivws r d ,r a ,r b vector divide word unsigned evdivwu r d ,r a ,r b vector equivalent eveqv r d ,r a ,r b vector extend sign byte evextsb r d ,r a vector extend sign half word evextsh r d ,r a vector floating-point absolute value evfsabs r d ,r a vector floating-point add evfsadd r d ,r a ,r b vector floating-point compare equal evfscmpeq cr d ,r a ,r b vector floating-point compare greater than evfscmpgt cr d ,r a ,r b vector floating-point compare less than evfscmplt cr d ,r a ,r b vector floating-point divide evfsdiv r d ,r a ,r b vector floating-point multiply evfsmul r d ,r a ,r b vector floating-point negate evfsneg r d ,r a vector floating-point negative absolute value evfsnabs r d ,r a vector floating-point subtract evfssub r d ,r a ,r b vector floating-point test equal evfststeq cr d ,r a ,r b vector floating-point test greater than evfststgt cr d ,r a ,r b vector floating-point test less than evfststlt cr d ,r a ,r b vector load double into half words evldh r d ,d(r a ) vector load double into half words indexed evldhx r d ,r a ,r b vector load double into two words evldw r d ,d(r a ) vector load double into two words indexed evldwx r d ,r a ,r b vector load double word into double word evldd r d ,d(r a ) vector load double word into double word indexed evlddx r d ,r a ,r b vector load half word into half word odd signed and splat evlhhossplat r d ,d(r a ) vector load half word into half word odd signed and splat indexed evlhhossplatx r d ,r a ,r b vector load half word into ha lf word odd unsigned and splat evlhhousplat r d ,d(r a ) vector load half word into half word odd unsigned and splat indexed evlhhousplatx r d ,r a ,r b vector load half word into half words even and splat evlhhesplat r d ,d(r a ) vector load half word into half words even and splat indexed evlhhesplatx r d ,r a ,r b vector load word into half words and splat evlwhsplat r d ,d(r a ) table 108. spe apu vector in structions (continued) instruction mnemonic syntax RM0004 instruction model 192/1176 vector load word into half words and splat indexed evlwhsplatx r d ,r a ,r b vector load word into half word s odd signed (with sign extension) evlwhos r d ,d(r a ) vector load word into half words odd signed indexed (with sign extension) evlwhosx r d ,r a ,r b vector load word into two half words even evlwhe r d ,d(r a ) vector load word into two half words even indexed evlwhex r d ,r a ,r b vector load word into two half words odd unsigned (zero-extended) evlwhou r d ,d(r a ) vector load word into two half word s odd unsigned indexed (zero-extended) evlwhoux r d ,r a ,r b vector load word into word and splat evlwwsplat r d ,d(r a ) vector load word into word and splat indexed evlwwsplatx r d ,r a ,r b vector merge high evmergehi r d ,r a ,r b vector merge high/low evmergehilo r d ,r a ,r b vector merge low evmergelo r d ,r a ,r b vector merge low/high evmergelohi r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional evmhesmf r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional and accumulate into words evmhesmfaaw r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional and accumulate negative into words evmhesmfanw r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional, accumulate evmhesmfa r d ,r a ,r b vector multiply half words, even, signed, modulo, integer evmhesmi r d ,r a ,r b vector multiply half words, even, signe d, modulo, integer and accumulate into words evmhesmiaaw r d ,r a ,r b vector multiply half words, even, si gned, modulo, integer and accumulate negative into words evmhesmianw r d ,r a ,r b vector multiply half words, even, signed, modulo, integer, accumulate evmhesmia r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional evmhessf r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional and accumulate into words evmhessfaaw r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional and accumulate negative into words evmhessfanw r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional, accumulate evmhessfa r d ,r a ,r b vector multiply half words, even, signed, saturate, integer and accumulate into words evmhessiaaw r d ,r a ,r b vector multiply half words, even, signed, saturate, integer and accumulate negative into words evmhessianw r d ,r a ,r b vector multiply half words, even, unsigned, modulo, integer evmheumi r d ,r a ,r b vector multiply half words, even, unsigned, modulo, integer and accumulate into words evmheumiaaw r d ,r a ,r b table 108. spe apu vector in structions (continued) instruction mnemonic syntax instruction model RM0004 193/1176 vector multiply half words, even, unsigned, modulo, integer and accumulate negative into words evmheumianw r d ,r a ,r b vector multiply half words, even, unsigned, modulo, integer, accumulate evmheumia r d ,r a ,r b vector multiply half words, even, unsigned, saturate, integer and accumulate into words evmheusiaaw r d ,r a ,r b vector multiply half words, even, unsigned, saturate, integer and accumulate negative into words evmheusianw r d ,r a ,r b vector multiply half words, odd, signed, modulo, fractional evmhosmf r d ,r a ,r b vector multiply half words, odd, signed, modulo, fractional and accumulate into words evmhosmfaaw r d ,r a ,r b vector multiply half words, odd, signed, modulo, fractional and accumulate negative into words evmhosmfanw r d ,r a ,r b vector multiply half words, odd, signed, modulo, fractional, accumulate evmhosmfa r d ,r a ,r b vector multiply half words, odd, signed, modulo, integer evmhosmi r d ,r a ,r b vector multiply half words, odd, signed, modulo, integer and accumulate into words evmhosmiaaw r d ,r a ,r b vector multiply half words, odd, signed, modulo, integer and accumulate negative into words evmhosmianw r d ,r a ,r b vector multiply half words, odd, signed, modulo, integer, accumulate evmhosmia r d ,r a ,r b vector multiply half words, o dd, signed, saturate, fractional evmhossf r d ,r a ,r b vector multiply half words, odd, signed , saturate, fractional and accumulate into words evmhossfaaw r d ,r a ,r b vector multiply half words, odd, signed , saturate, fractional and accumulate negative into words evmhossfanw r d ,r a ,r b vector multiply half words, odd, si gned, saturate, fractional, accumulate evmhossfa r d ,r a ,r b vector multiply half words, odd, si gned, saturate, integer and accumulate into words evmhossiaaw r d ,r a ,r b vector multiply half words, odd, si gned, saturate, integer and accumulate negative into words evmhossianw r d ,r a ,r b vector multiply half words, odd, unsigned, modulo, integer evmhoumi r d ,r a ,r b vector multiply half words, odd, un signed, modulo, integer and accumulate into words evmhoumiaaw r d ,r a ,r b vector multiply half words, odd, un signed, modulo, integer and accumulate negative into words evmhoumianw r d ,r a ,r b vector multiply half words, odd, unsigned, modulo, integer, accumulate evmhoumia r d ,r a ,r b vector multiply half words, odd, unsi gned, saturate, integer and accumulate into words evmhousiaaw r d ,r a ,r b vector multiply half words, odd, unsi gned, saturate, integer and accumulate negative into words evmhousianw r d ,r a ,r b vector multiply word high signed, modulo, fractional evmwhsmf r d ,r a ,r b table 108. spe apu vector in structions (continued) instruction mnemonic syntax RM0004 instruction model 194/1176 vector multiply word high signed, modulo, fractional and accumulate evmwhsmfa r d ,r a ,r b vector multiply word high signed, modulo, integer evmwhsmi r d ,r a ,r b vector multiply word high signed, modulo, integer and accumulate evmwhsmia r d ,r a ,r b vector multiply word high signed, saturate, fractional evmwhssf r d ,r a ,r b vector multiply word high signed, saturate, fractional and accumulate evmwhssfa r d ,r a ,r b vector multiply word high unsigned, modulo, integer evmwhumi r d ,r a ,r b vector multiply word high unsigned, modulo, integer and accumulate evmwhumia r d ,r a ,r b vector multiply word low signed, modulo, integer and accumulate in words evmwlsmiaaw r d ,r a ,r b vector multiply word low signed, modulo, integer and accumulate negative in words evmwlsmianw r d ,r a ,r b vector multiply word low signed, saturate, integer and accumulate in words evmwlssiaaw r d ,r a ,r b vector multiply word low signed, saturate, integer and accumulate negative in words evmwlssianw r d ,r a ,r b vector multiply word low unsigned, modulo, integer evmwlumi r d ,r a ,r b vector multiply word low unsigned, modulo, integer and accumulate evmwlumia r d ,r a ,r b vector multiply word low unsigned, modulo, integer and accumulate in words evmwlumiaaw r d ,r a ,r b vector multiply word low unsigned, m odulo, integer and accumulate negative in words evmwlumianw r d ,r a ,r b vector multiply word low unsigned, saturate, integer and accumulate in words evmwlusiaaw r d ,r a ,r b vector multiply word low unsigned, saturate, integer and accumulate negative in words evmwlusianw r d ,r a ,r b vector multiply word signed, modulo, fractional evmwsmf r d ,r a ,r b vector multiply word signed, modulo, fractional and accumulate evmwsmfa r d ,r a ,r b vector multiply word signed, modulo, fractional and accumulate evmwsmfaa r d ,r a ,r b vector multiply word signed, modulo, fractional and accumulate negative evmwsmfan r d ,r a ,r b vector multiply word signed, modulo, integer evmwsmi r d ,r a ,r b vector multiply word signed, modulo, integer and accumulate evmwsmia r d ,r a ,r b vector multiply word signed, modulo, integer and accumulate evmwsmiaa r d ,r a ,r b vector multiply word signed, modulo, integer and accumulate negative evmwsmian r d ,r a ,r b vector multiply word signed, saturate, fractional evmwssf r d ,r a ,r b vector multiply word signed, saturate, fractional and accumulate evmwssfa r d ,r a ,r b vector multiply word signed, saturate, fractional and accumulate evmwssfaa r d ,r a ,r b vector multiply word signed, saturate, fractional and accumulate negative evmwssfan r d ,r a ,r b vector multiply word unsigned, modulo, integer evmwumi r d ,r a ,r b vector multiply word unsigned, modulo, integer and accumulate evmwumia r d ,r a ,r b table 108. spe apu vector in structions (continued) instruction mnemonic syntax instruction model RM0004 195/1176 vector multiply word unsigned, modulo, integer and accumulate evmwumiaa r d ,r a ,r b vector multiply word unsigned, modul o, integer and accumulate negative evmwumian r d ,r a ,r b vector nand evnand r d ,r a ,r b vector negate evneg r d ,r a vector nor evnor r d ,r a ,r b vector or evor r d ,r a ,r b vector or with complement evorc r d ,r a ,r b vector rotate left word evrlw r d ,r a ,r b vector rotate left word immediate evrlwi r d ,r a , uimm vector round word evrndw r d ,r a vector select evsel r d ,r a ,r b ,cr s vector shift left word evslw r d ,r a ,r b vector shift left word immediate evslwi r d ,r a , uimm vector shift right word immediate signed evsrwis r d ,r a , uimm vector shift right word immediate unsigned evsrwiu r d ,r a , uimm vector shift right word signed evsrws r d ,r a ,r b vector shift right word unsigned evsrwu r d ,r a ,r b vector splat fractional immediate evsplatfi r d , simm vector splat immediate evsplati r d , simm vector store double of double evstdd r s ,d(r a ) vector store double of double indexed evstddx r s ,r a ,r b vector store double of four half words evstdh r s ,d(r a ) vector store double of four half words indexed evstdhx r s ,r a ,r b vector store double of two words evstdw r s ,d(r a ) vector store double of two words indexed evstdwx r s ,r a ,r b vector store word of two half words from even evstwhe r s ,d(r a ) vector store word of two half words from even indexed evstwhex r s ,r a ,r b vector store word of two half words from odd evstwho r s ,d(r a ) vector store word of two half words from odd indexed evstwhox r s ,r a ,r b vector store word of word from even evstwwex r s ,d(r a ) vector store word of word from even indexed evstwwex r s ,r a ,r b vector store word of word from odd evstwwo r s ,d(r a ) vector store word of word from odd indexed evstwwox r s ,r a ,r b vector subtract from word evsubfw r d ,r a ,r b vector subtract immediate from word evsubifw r d , uimm ,r b table 108. spe apu vector in structions (continued) instruction mnemonic syntax RM0004 instruction model 196/1176 embedded vector and scalar floating-point apu instructions the embedded floating-point operations are ieee-compliant with software exception handlers and offer a simpler exception model than the floating-point instructions defined by the powerpc isa. instead of fprs, these instructions use gprs to offer improved performance for converting between floating-poi nt, integer, and fractional values. sharing gprs allows vector floating- point instructions to use spe load and store instructions. the spfp apus are described as follows: vector spfp instructions operate on a vector of two 32-bit, single-precision floating- point numbers that reside in the upper and lower halves of the 64-bit gprs. these instructions are listed in ta bl e 1 1 7 alongside their scalar equivalents. scalar spfp instructions operate on single 32-bit operands that reside in the lower 32- bits of the gprs. these instructions are listed in ta b l e 1 1 7 . scalar dpfp instructions operate on single 64-bit double-precision operands that reside in the 64-bit gprs. thes e instructions are listed in ta b l e 1 0 9 . note: note that the vector and scalar versions of the instructions have the same syntax. vector subtract signed, modulo, integer to accumulator word evsubfsmiaaw r d ,r a vector subtract signed, saturate, integer to accumulator word evsubfssiaaw r d ,r a vector subtract unsigned, modulo , integer to accumulator word evsubfumiaaw r d ,r a vector subtract unsigned, satura te, integer to accumulator word evsubfusiaaw r d ,r a vector xor evxor r d ,r a ,r b table 108. spe apu vector in structions (continued) instruction mnemonic syntax table 109. vector and scalar floating-point apu instructions instruction single-precision double- precision scalar syntax scalar vector convert floating-point double- from single-precision ? ? efdcfs r d ,r b convert floating-point from signed fraction efscfsf evfscfsf efdcfsf r d ,r b convert floating-point from signed integer efscfsi evfscfsi efdcfsi r d ,r b convert floating-point from unsigned fraction efscfuf evfscfuf efdcfuf r d ,r b convert floating-point from unsigned integer efscfui evfscfui efdcfui r d ,r b convert floating-point single- from double-precision ? ? efscfd r d ,r b convert floating-point to signed fraction efsctsf evfsctsf efdctsf r d ,r b convert floating-point to signed integer efsctsi evfsctsi efdctsi r d ,r b convert floating-point to signed integer with round toward zero efsctsiz evfsctsiz efdctsiz r d ,r b convert floating-point to unsigned fraction efsctuf evfsctuf efdctuf r d ,r b convert floating-point to unsigned integer efsctui evfsctui efdctui r d ,r b convert floating-point to unsigned integer with round toward zero efsctuiz evfsctuiz efdctuiz r d ,r b instruction model RM0004 197/1176 3.6.2 integer select (isel) apu the integer select apu consists of the isel instruction, a conditional register move that helps eliminate branches. section 7.1: integer select apu ,? describes the use of isel . 3.6.3 performanc e monitor apu the eis defines the performance monitor as an apu. software communication with the performance monitor apu is achieved through performance monitor registers (pmrs) rather floating-point absolute value efsabs (1) evfsabs efdabs r d ,r a floating-point add efsadd evfsadd efdadd r d ,r a ,r b floating-point compare equal efscmpeq evfscmpeq efdcmpeq cr d ,r a ,r b floating-point compare greater than efscmpgt evfscmpgt efdcmpgt cr d ,r a ,r b floating-point compare less than efscmplt evfscmplt efdcmplt cr d ,r a ,r b floating-point divide efsdiv evfsdiv efddiv r d ,r a ,r b floating-point multiply efsmul evfsmul efdmul r d ,r a ,r b floating-point negate efsneg 1 evfsneg efdneg r d ,r a floating-point negative absolute value efsnabs 1 evfsnabs efdnabs r d ,r a floating-point subtract efssub evfssub efdsub r d ,r a ,r b floating-point test equal efststeq evfststeq efdtsteq cr d ,r a ,r b floating-point test greater than efststgt evfststgt efdtstgt cr d ,r a ,r b floating-point test less than efststlt evfststlt efdtstlt cr d ,r a ,r b spe double word load/store instructions vector load double word into double word ? evldd evldd r d ,d(r a ) vector load double word into double word indexed ? evlddx evlddx r d ,r a ,r b vector merge high ? evmergehi evmergehi r d ,r a ,r b vector merge low ? evmergelo evmergelo r d ,r a ,r b vector store double of double ? evstdd evstdd r s ,d(r a ) vector store double of double indexed ? evstddx evstddx r s ,r a ,r b on some cores, floating-point operations that pr oduce a result of zero may generate an incorrect sign. 1. exception detection for these instruct ions is implementation dependent. on some devices, infinities, nans, and denorms are always be treated as norms. no exc eptions are taken if spefscr[finve] = 1. table 109. vector and scalar floating-point apu instructions (continued) instruction single-precision double- precision scalar syntax scalar vector table 110. integer select apu instruction name mnemonic syntax integer select isel r d ,r a ,r b ,cr b RM0004 instruction model 198/1176 than sprs. new instructions are provided to move to and from these pmrs. performance monitor apu instructions are described in ta bl e 1 1 1 . the book e implementation standards defines a set of register resources used exclusively by the performance monitor. pmrs are similar to the sprs defined in the book e architecture and are accessed by mtpmr and mfpmr , which are also defined by the eis. table 112 lists supervisor-level pmrs. user-level software that attempts to read or write supervisor-level pmrs causes a privilege exception. table 111. performance monitor apu instructions name mnemonic syntax move from performance monitor register mfpmr r d , pmrn move to performance monitor register mtpmr pmrn ,r s table 112. performance monitor registers?supervisor level abbreviation register name pmr nu mber pmr[0?4] pmr[5?9] section/page pmgc0 performance monitor global control register 0 400 01100 10000 chapter 2.16.1 pmlca0 performance monitor local control a0 144 00100 10000 chapter 2.16.3 pmlca1 performance monitor local control a1 145 00100 10001 pmlca2 performance monitor local control a2 146 00100 10010 pmlca3 performance monitor local control a3 147 00100 10011 pmlcb0 performance monitor local control b0 272 01000 10000 chapter 2.16.5 pmlcb1 performance monitor local control b1 273 01000 10001 pmlcb2 performance monitor local control b2 274 01000 10010 pmlcb3 performance monitor local control b3 275 01000 10011 instruction model RM0004 199/1176 user-level pmrs in ta bl e 1 1 3 are read-only and are accessed with mfpmr . attempting to write user-level registers in supervisor or us er mode causes an illega l instruction exception. pmc0 performance monitor counter 0 16 00000 10000 chapter 2.16.7 pmc1 performance monitor counter 1 17 00000 10001 pmc2 performance monitor counter 2 18 00000 10010 pmc3 performance monitor counter 3 19 00000 10011 table 113. performance monitor registers?user level (read-only) abbreviation register name pmr number pmr[0?4] pmr[5?9] section/page upmgc0 user performance monitor global control register 0 384 01100 00000 chapter 2.16.2 upmlca0 user performance monitor local control a0 128 00100 00000 chapter 2.16.4 upmlca1 user performance monitor local control a1 129 00100 00001 upmlca2 user performance monitor local control a2 130 00100 00010 upmlca3 user performance monitor local control a3 131 00100 00011 upmlcb0 user performance monitor local control b0 256 01000 00000 section 2.16.6 on page 129 upmlcb1 user performance monitor local control b1 257 01000 00001 upmlcb2 user performance monitor local control b2 258 01000 00010 upmlcb3 user performance monitor local control b3 259 01000 00011 upmc0 user performance monitor counter 0 0 00000 00000 section 2.16.8 on page 129 upmc1 user performance monitor counter 1 1 00000 00001 upmc2 user performance monitor counter 2 2 00000 00010 upmc3 user performance monitor counter 3 3 00000 00011 table 112. performance monitor registers?supervisor level (continued) abbreviation register name pmr nu mber pmr[0?4] pmr[5?9] section/page RM0004 instruction model 200/1176 3.6.4 cache locking apu this section describes the instructions in th e cache locking apu, which consists of the instructions described in table 114 . lines are locked into the cache by software using a series of touch and lock set instructions. the following instructions are provided to lock data items into the data and instruction cache: dcbtls ?data cache block touch and lock set dcbtstls ?data cache block touch for store and lock set icbtls ?instruction cache block touch and lock set the r a and r b operands to these instructions form a ea identifying the line to be locked. the ct field indicates which cache in the cache hier archy should be targeted. these instructions are similar to the dcbt , dcbtst , and icbt instructions, but lockin g instructions can not execute speculatively and may cause additional exceptions. for unified caches, both the instruction lock set and the data lock set target the same cache. similarly, lines are unlocked from the cache by software using a series of lock-clear instructions. the following instructions are provid ed to lock instructions into the instruction cache: dcblc ?data cache block lock clear icblc ?instruction cache block lock clear the r a and r b operands to these instructions form an ea identifying the line to be unlocked. the ct field indicates which cache in the cache hierarchy should be targeted. additionally, software may clear all the locks in the cache. for the primary cache, this is accomplished by setting the clfc (dcl fc, iclfc) bit in l1csr0 (l1csr1). cache lines can also be implicitly unlocked in the following ways: a locked line is invalidated if it is targeted by a dcbi , dcbf , or icbi instruction. a snoop hit on a locked line that requires the line to be invalidated. this can occur because the data the line contains has been modified external to the processor, or another processor has explicitly invalidated the line. the entire cache containing the locked line is flash invalidated. an implementation is not required to unlock lines if data is invalidated in the cache. although the data may be invalidated (and thus not in the cache), the cache can keep the lock associated with th at cache line present and fill the lin e from the memory subsystem when the next access occurs. if the implementation does not clear locks when the associated line is invalidated, the method of locking is said to be persistent. an implementation may choose to implement locks as persistent or not pers istent; the preferred method is persistent. table 114. cache locking apu instructions name mnemonic syntax description data cache block lock clear dcblc ct ,r a ,r b treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. data cache block touch and lock set dcbtls ct ,r a ,r b treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. instruction model RM0004 201/1176 the cache-locking apu defines a flash clear for all data cache lock bits (using l1csr0[clfr]) and in the instruction cache (using l1csr1[iclfr]). this allows system software to clear all data cache locking bits without knowing the addresses of the lines locked. 3.6.5 machine check apu the machine check apu defines a separate interrupt type for machine check interrupts. it provides additional save and restore sprs (mcsrr and mcsrr1). the return from machine check interrupt instruction ( rfmci ), is described in ta b l e 1 1 5 . 3.6.6 vle extension this section lists instructions defined or supported by the vle extension. unless otherwise noted, instructions that are not prefixed with e_ or se_ have identical encodings and semantics as in book e or in the eis. book e?defined instructions listed in the tables in this section can be executed when the processor is in vle mode; book e instructions not listed cannot. a complete list of supported in structions is provided in instruction listings on page 217 .? processor control instructions this section lists processor control instructions that can be executed when a processor is in vle mode. these instructions are grouped as follows: system linkage instructions on page 201? processor control register manipulation instructions on page 202? instruction synchronization instruction on page 202 ? system linkage instructions data cache block touch for store and lock set dcbtstls ct ,r a ,r b it is implementation dependent whether this instruction is treated as a load or store with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. instruction cache block lock clear icblc ct ,r a ,r b treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. instruction cache block touch and lock set icbtls ct ,r a ,r b treated as a load with respect to any memory barriers, synchronization, translation and protection, and debug address comparisons. table 114. cache locking apu instructions (continued) name mnemonic syntax description table 115. machine check apu instruction name mnemonic syntax implementation notes return from machine check interrupt rfmci ? restores mcsrr0 and mcsrr1 values; context-synchronizing. RM0004 instruction model 202/1176 the se_sc , se_rfi , se_rfci , and se_rfdi system linkage instructions, shown in table 116 , enable a program to call on the system to perform a service (that is, invoke a system call interrupt), and enable the system to return from performing a service or from processing an interrupt. processor control register manipulation instructions in addition to the book e processor control register manipulation instructions, the vle extension provides 16-bit forms of instructions to move to/from the lr and ctr, listed in table 117 instruction synchronization instruction table 118 lists the vle-defined se_isync instruction. table 116. system linkage instruction set index mnemonic instru ction reference se_sc system call page -954 se_rfci` return from critical interrupt page -949 se_rfdi return from debug interrupt page -859 se_rfi return from interrupt page -950 table 117. system register manipulation instruction set index mnemonic instruction reference se_mfctr r x move from count register page -938 mfdcr r d , dcrn move from device control register book e se_mflr r x move from link register page -939 mfmsr r d move from machine state register book e mfspr r d , sprn move from special purpose register book e se_mtctr r x move to count register page -942 mtdcr dcrn,r s move to device control register book e se_mtlr r x move to link register page -943 mtmsr r s move to machine state register book e mtspr sprn,r s move to special purpose register book e wrtee r a write msr external enable book e wrteei e write msr external enable immediate book e table 118. instruction synchronization instruction set index mnemonic instruction reference se_isync instruction synchronize page -929 instruction model RM0004 203/1176 branch operation instructions this section lists branch instructions that can be executed when a processor is in vle mode. it also describes the registers that support them. registers for branch operations the sections listed in the following describe the registers that support branch operations: chapter 2.5.1: condition register (cr) on page 61 ? chapter 2.5.2: link register (lr) on page 66 ? chapter 2.5.3: count register (ctr) on page 67 ? branch instructions the sequence of instruction execution can be changed by the branch instructions. because vle instructions must be aligned on half-word boundaries, the low-order bit of the generated branch target address is forced to 0 by the processor in performing the branch. the branch instructions compute the ea of the target in one of the following ways, as described in chapter 10.2: instruction memory addressing modes on page 854 .? 1. adding a displacement to the address of the branch instruction. 2. using the address contained in the lr (branch to link register [and link]). 3. using the address contained in the ctr (branch to count register [and link]). branching can be conditional or unconditional, and the return address can optionally be provided. if the return address is to be provided (lk = 1), the ea of the instruction following the branch instruction is placed into the lr after the branch target address has been computed: this is done whether or not the branch is taken. in branch conditional instructions, the bi32 or bi16 instruction field specifies the cr bit to be tested. for 32-bit instructions using bi32, cr[32?47] (corresponding to bits in cr0?cr3) may be specified. for 16-bit instructions using bi16, only cr[32?35] (bits within cr0) may be specified. in branch conditional instructions, the bo32 or bo16 field specifies the conditions under which the branch is taken and how the branch is affected by or affects the cr and ctr. note that vle instructions also have different encodings for the bo32 and bo16 fields than in book e?s bo field. if the bo32 field specifies that the ctr is to be decremented, ctr[32?63] are decremented. if bo[16,32] specifies a condition that must be true or false, that condition is obtained from the contents of cr[bi+32]. (note that cr bits are numbered 32? 63. bi refers to the bi field in the branch instruction encoding. for example, specifying bi = 2 refers to cr[34].) encodings for the bo32 field for the vle extension are shown in table 120 . table 119. vle extension bo32 encodings bo32 description 00 branch if the condition is false. 01 branch if the condition is true. RM0004 instruction model 204/1176 the encoding for the bo16 field for the vle extension is shown in table 120 . the various branch instructions supported by the vle extension are shown in table 121 . condition register instructions condition register instructions are provided to transfer values to/from various portions of the cr. the vle extension does not introduce any additional functionality beyond that defined in book e for cr operations, but does remap the cr-logical and mcrf instruction functionality into major opcode 31. these instructions operate identically to the book e instructions, but are encoded differently. table 122 lists condition regi ster instructions supported in vle mode. 10 decrement ctr[32?63] , then branch if the decremented ctr[32?63] 0. 11 decrement ctr[32?63], then branch if the decremented ctr[32?63] = 0. table 120. vle extension bo16 encodings bo16 description 0 branch if the condition is false. 1 branch if the condition is true. table 121. branch instruction set index mnemonic instruction reference e_b bd24 e_bl bd24 branch branch & link page -903 se_b bd8 se_bl bd8 branch branch & link page -903 e_bc bo32 , bi32 , bd15 se_bc bo16 , bi16 , bd8 e_bcl bo32 , bi32 , bd15 branch conditional branch conditional branch conditional & link page -904 se_bctr se_bctrl branch to count register branch to count register & link page -906 se_blr se_blrl branch to link register branch to link register & link page -908 table 122. condition register instruction set index mnemonic instruction reference e_crand crb d ,crb a ,crb b condition register and page -920 e_crandc crb d ,crb a ,crb b condition register and with complement page -920 e_creqv crb d ,crb a ,crb b condition register equivalent page -920 e_crnand crb d ,crb a ,crb b condition register nand page -921 e_crnor crb d ,crb a ,crb b condition register nor page -922 table 119. vle extension bo32 encodings bo32 description instruction model RM0004 205/1176 integer instructions this section lists the integer instruct ions supported by the vle extension. integer load instructions the integer load instructions, listed in table 123 , compute the ea of the memory to be accessed as described in chapter 10.1: data memory addressing modes on page 854 .? the byte, half word, or word in memory addressed by ea is loaded into gpr( r d) or gpr( r z). the vle extension supports both big- and little-endian byte ordering for data accesses. some integer load instructions have an update form in which gpr( r a) is updated with the ea. for these forms, if r a 0 and r a r d, the ea is placed into gpr( r a) and the memory element (byte, half word, word, or double word) addressed by ea is loaded into gpr( r d). if r a = 0 or r a= r d, the instruction form is invalid. this is the same behavior as specified for load with update instructions in book e. e_cror crb d ,crb a ,crb b condition register or page -923 e_crorc crb d ,crb a ,crb b condition register or with complement page -923 e_crxor crb d ,crb a ,crb b condition register xor page -925 e_mcrf cr d ,cr s move condition register field page -936 mcrxr cr d move to condition register from integer exception register book e mfcr r d move from condition register book e mtcrf fxm ,r s move to condition register fields book e table 123. basic integer load instruction set index mnemonic instruction reference e_lbz r d , d (r a ) e_lbzu r d , d8 (r a ) se_lbz r z , sd4 (r x ) load byte and zero load byte and zero with update load byte and zero (16-bit form) page -930 lbzx r d ,r a ,r b lbzux r d ,r a ,r b load byte and zero indexed load byte and zero with update indexed book e e_lha r d , d (r a ) e_lhau r d , d8 (r a ) load halfword algebraic load halfword algebraic with update page -931 lhax r d ,r a ,r b lhaux r d ,r a ,r b load halfword algebraic indexed load halfword algebraic with update indexed book e table 122. condition register instruction set index mnemonic instruction reference RM0004 instruction model 206/1176 integer load byte-reversed instructions are listed in ta bl e 1 2 4 . the vle-defined integer load mult iple instruction is listed in table 125 . the vle-defined integer load and reserve instruction is listed in ta b l e 1 2 6 . integer store instructions the integer store instructions compute the ea of the memory to be accessed as described in chapter 10.1: data memory addressing modes on page 854 .? the contents of gpr( r s) or gpr( r z) are stored into the byte, half word, or word in memory addressed by ea. the vle extension supports both big- and little-endian byte ordering for data accesses. e_lhz r d , d (r a ) e_lhzu r d , d8 (r a ) se_lhz r z , sd4 (r x ) load halfword and zero load halfword and zero with update load halfword and zero (16-bit form) page -932 lhzx r d ,r a ,r b lhzux r d ,r a ,r b load halfword and zero indexed load halfword and zero with update indexed book e e_lwz r d , d (r a ) e_lwzu r d , d8 (r a ) se_lwz r z , sd4 (r x ) load word and zero load word and zero with update load word and zero (16-bit form) page -935 lwzx r d ,r a ,r b lwzux r d ,r a ,r b load word and zero indexed load word and zero with update indexed book e table 124. integer load byte-reverse instruction set index mnemonic instruction reference lhbrx r d ,r a ,r b load halfword byte-reverse indexed book e lwbrx r d ,r a ,r b load word byte-reverse indexed book e table 125. integer load multiple instruction set index mnemonic instruction reference e_lmw r d , d8 (r a ) load multiple word page -934 table 126. integer load and reserve instruction set index mnemonic instruction reference lwarx r d ,r a ,r b load word and reserve indexed book e table 123. basic integer load instruction set index mnemonic instruction reference instruction model RM0004 207/1176 some integer store instructions have an update form, in which gpr( r a) is updated with the ea. for these forms, the following rules (from book e) apply. if r a 0, the ea is placed into gpr( r a). if r s = r a, the contents of gpr( r s) are copied to the target memory element and then ea is placed into gpr( r a). the basic integer store in structions are listed in ta b l e 1 2 7 . the integer store byte-reverse instructions are listed in ta b l e 1 2 8 . the integer store multiple instruction is listed in ta bl e 1 2 9 . the integer store conditional instruction is listed in ta bl e 1 3 0 . table 127. basic integer store instruction set index mnemonic instruction reference e_stb r s , d (r a ) e_stbu r s , d8 (r a ) se_stb r z , sd4 (r x ) store byte store byte with update store byte (16-bit form) page -958 stbx r s ,r a ,r b stbux r s ,r a ,r b store byte indexed store byte with update indexed book e e_sth r s , d (r a ) e_sthu r s , d8 (r a ) se_sth r z , sd4 (r x ) store halfword store halfword with update store halfword (16-bit form) page -959 sthx r s ,r a ,r b sthux r s ,r a ,r b store halfword indexed store halfword with update indexed book e e_stw r s , d (r a ) e_stwu r s , d8 (r a ) se_stw r z , sd4 (r x ) store word store word with update store word (16-bit form) page -961 stwx r s ,r a ,r b stwux r s ,r a ,r b store word indexed store word with update indexed book e table 128. integer store byte-reverse instruction set index mnemonic instruction reference sthbrx r s ,r a ,r b store halfword byte-reverse indexed book e stwbrx r s ,r a ,r b store word byte-reverse indexed book e table 129. integer store multiple instruction set index mnemonic instruction reference e_stmw r s , d8 (r a ) store multiple word page -960 table 130. integer store conditional instruction set index mnemonic instruction reference stwcx. r s ,r a ,r b store word conditional indexed book e RM0004 instruction model 208/1176 integer arithmetic instructions the integer arithmetic instructions use the contents of the gprs as source operands, and place results into gprs, into status bits in the xer and into cr0. the integer arithmetic instructions treat source operands as signed, two?s complement integers unless the instru ction is explicitly identified as performing an unsigned operation. the e_add2i. instruction and the oim5-form instruction, se_subi. , set the first three bits of cr0 to characterize bits 32?63 of the result. these bits are set by signed comparison of bits 32?63 of the result to zero. e_addic [ . ] and e_subfic [ . ] always set ca to reflect the carry out of bit 32. the integer arithmetic in structions are listed in table 131 . table 131. integer arithmetic instruction set index mnemonic instruction reference add r d ,r a ,r b add. r d ,r a ,r b addo r d ,r a ,r b addo. r d ,r a ,r b add book e se_add r x ,r yadd page -897 addc r d ,r a ,r b addc. r d ,r a ,r b addco r d ,r a ,r b addco. r d ,r a ,r b add carrying book e adde r d ,r a ,r b adde. r d ,r a ,r b addeo r d ,r a ,r b addeo. r d ,r a ,r b add extended book e e_addi r d ,r a , sci8 e_addi. r d ,r a , sci8 e_add16i r d ,r a , si e_add2i. r d , si se_addi r x , oimm add immediate page -898 e_addic r d ,r a , sci8 e_addic. r d ,r a , sci8 add immediate carrying page -900 e_add2is r d , si add immediate shifted page -898 divw r d ,r a ,r b divw. r d ,r a ,r b divwo r d ,r a ,r b divwo. r d ,r a ,r b divide word book e divwu r d ,r a ,r b divwu. r d ,r a ,r b divwuo r d ,r a ,r b divwuo. r d ,r a ,r b divide word unsigned book e instruction model RM0004 209/1176 integer logical and move instructions logical instructions perform bit-parallel operations on 32-bit operands or move register or immediate values into registers. the move instructions move values into a gp from either another gpr, or an immediate value. the x-form logical instructions with rc = 1 and the sci8-form logical instructions with rc = 1 set the first three bits of cr field 0 as described in integer arithmetic instructions on page 208 .? the logical instructions do not change xer[so,ov,ca]. the integer logical inst ructions are listed in ta bl e 1 3 2 . mulhw r d ,r a ,r b mulhw. r d ,r a ,r b multiply high word book e mulhwu r d ,r a ,r b mulhwu. r d ,r a ,r b multiply high word unsigned book e e_mulli r d ,r a , sci8 e_mull2i r d , si multiply low immediate page -944 mullw r d ,r a ,r b mullw. r d ,r a ,r b mullwo r d ,r a ,r b mullwo. r d ,r a ,r b multiply low word book e se_mullw r x ,r y multiply low word page -945 neg r d ,r a se_neg r x neg. r d ,r a nego r d ,r a nego. r d ,r a negate page -946 se_sub r x ,r y subtract page -962 subf r d ,r a ,r b subf. r d ,r a ,r b subfo r d ,r a ,r b subfo. r d ,r a ,r b subtract from book e se_subf r x ,r y subtract from page -963 subfc r d ,r a ,r b subfc. r d ,r a ,r b subfco r d ,r a ,r b subfco. r d ,r a ,r b subtract from carrying book e e_subfic r d ,r a , sci8 e_subfic. r d ,r a , sci8 subtract from immediate carrying page -964 se_subi r x , oimm se_subi. r x , oimm subtract immediate page -965 table 131. integer arithmetic instruction set index (continued) mnemonic instruction reference RM0004 instruction model 210/1176 table 132. integer logical instruction set index mnemonic instruction reference and [ . ] r a ,r s ,r b se_and [ . ] r x ,r y and page -901 andc [ . ] r a ,r s ,r b se_andc r x ,r y and with complement page -901 e_andi [ . ] r a ,r s , sci8 se_andi r x , ui5 e_and2i. r d , ui and immediate page -901 e_and2is. r d , ui and immediate shifted page -901 se_bclri r x , ui5 bit clear page -905 se_bgeni r x , ui5 bit generate page -907 se_bmski r x , ui5 bit mask generate page -909 se_bseti r x , ui5 bit set page -910 cntlzw r a ,r s cntlzw. r a ,r s count leading zeros word book e eqv r a ,r s ,r b eqv. r a ,r s ,r b equivalent book e extsb r a ,r s extsb. r a ,r s se_extsb r x extend sign byte page -926 extsh r a ,r s extsh. r a ,r s se_extsh r x extend sign halfword page -926 se_extzb r x extend with zeros byte page -927 se_extzh r x extend with zeros halfword page -927 e_li r d , li20 se_li r x , ui7 load immediate page -933 e_lis r d , ui load immediate shifted page -933 se_mfar r x ,ar y move from alternate register page -937 se_mr r x ,r y move register page -940 se_mtar ar x ,r y move to alternate register page -941 nand r a ,r s ,r b nand. r a ,r s ,r b nand book e nor r a ,r s ,r b nor. r a ,r s ,r b nor book e or r a ,r s ,r b or. r a ,r s ,r b se_or r x ,r y or page -948 se_not r xnot page -947 instruction model RM0004 211/1176 integer compare and bit test instructions the integer compare instructions compare the contents of gpr(ra) with one of the following: the value of the sci8 field the zero-extended value of the ui field the zero-extended value of the ui5 field the sign-extended value of the si field the contents of gpr( r b) or gpr( r y). the following comparisons are signed: e_cmph , e_cmpi , e_cmp16i , e_cmph16i , se_cmp , se_cmph , and se_cmpi . the following comparisons are unsigned: e_cmphl , e_cmpli , e_cmphl16i , e_cmpl16i , se_cmpli , se_cmpl , and se_cmphl . when operands are treated as 32-bit signed quantities, gpr n [32] is the sign bit. when operands are treated as 16-bit signed quantities, gpr n [48] is the sign bit. for 32-bit implementations, the l field must be zero. compare instructions set one of the left-most three bits of the designated cr field and clears the other two. xer[so] is copied to bit 3 of the designated cr field. the cr field is set as shown in ta bl e 1 3 3 . the integer bit test instruction tests the bit specified by the ui5 instruction field and sets the cr0 field as shown in ta bl e 1 3 4 . orc r a ,r s ,r b orc. r a ,r s ,r b or with complement book e e_ori [ . ] r a ,r s , sci8 e_or2i r d , ui or immediate page -966 e_or2is r d , ui or immediate shifted page -966 xor r a ,r s ,r b xor. r a ,r s ,r b xor book e e_xori [ . ] r a ,r s , sci8 xor immediate page -966 table 133. cr settings for compare instructions bit name description 0lt ( r a or r x) < sci8, si, ui5, or gpr( r b or r y) (signed comparison) ( r a or r x) < u sci8, ui, ui5 or gpr( r b or r y) (unsigned comparison) 1gt( r a or r x) > sci8, si, ui5, or gpr( r b or r y) (signed comparison) ( r a or r x) > u sci8, ui, ui5 or gpr( r b or r y) (unsigned comparison) 2eq( r a or r x) = sci8, si, ui, ui5, or gpr( r b or r y) 3 so summary overflow from the xer table 132. integer logical instruction set index (continued) mnemonic instruction reference RM0004 instruction model 212/1176 table 135 is an index for integer compare and bit test operations. integer select instruction the isel instruction provides a means to select one of two registers and place the result in a destination register under the control of a predicate value supplied by a cr bit. the integer select inst ruction is listed in ta b l e 1 3 6 . integer trap instructions trap instructions test for a specified set of conditions by comparing the contents of one gpr with a second gpr. if any of the conditions tested by a trap instruction are met, a trap table 134. cr settings for integer bit test instructions bit name description 0 lt always cleared 1gt rx ui5 == 1 2eq rx ui5 == 0 3 so summary overflow from the xer table 135. integer compare and bit test instruction set index mnemonic instruction reference se_btsti r x , ui5 bit test immediate page -911 cmp cr d , l ,r a ,r b se_cmp r x ,r y compare page -912 e_cmph cr d ,r a ,r b se_cmph r x ,r y compare halfword page -914 e_cmph16i r a , si16 compare halfword immediate page -914 e_cmphl cr d ,r a ,r b se_cmphl r x ,r y compare halfword logical page -916 e_cmphl16i r a , ui16 compare halfword logical immediate page -916 e_cmpi cr d ,r a , sci8 e_cmp16i r a , si16 se_cmpi r x , ui5 compare immediate page -912 cmpl cr d , l ,r a ,r b se_cmpl r x ,r y compare logical page -918 e_cmpli cr d ,r a , sci8 e_cmpl16i r a , ui16 se_cmpli r x , ui5 compare logical immediate page -918 table 136. integer select instruction set index mnemonic instruction reference isel r d ,r a ,r b ,cr b integer select eis instruction model RM0004 213/1176 exception type program interrupt is invoked. if none of the tested conditions are met, instruction execution continues normally. the contents of gpr( r a) are compared with the contents of gpr( r b). for twi and tw , only the contents of bits 32?63 of r a (and r b) participate in the comparison. this comparison results in five conditions that are anded with to. if the result is not 0, the trap exception type program interrupt is invoked. these conditions are as shown in table 137 . the integer trap inst ruction is listed in table 138 . 3 integer rotate and shift instructions instructions are provided that perform shifts and rotates on data from a gpr and return the result, or a portion of the result, to a gpr. the rotation operations rotate a 32-bit quantity left by a specified number of bit positions. bits that exit from position 32 enter at position 63. the rotate 32 operation is used to rotate a given 32-bit quantity. some rotate and shift instructions employ a mask generator. the mask is 32 bits long, and consists of 1 bits from a start bit, mstart , through and including a stop bit, mstop , and 0-bits elsewhere. the values of mstart and mstop range from 32 to 63. if mstart > mstop, the 1 bits wrap around from position 63 to position 0. thus the mask is formed as follows: if mstart mstop then mask mstart:mstop = ones mask all other bits = zeros else mask mstart:63 = ones mask 32:mstop = ones mask all other bits = zeros there is no way to specify an all-zero mask. table 137. integer trap conditions to bit anded with condition 0 less than, using signed comparison 1 greater than, using signed comparison 2 equal 3 less than, using unsigned comparison 4 greater than, using unsigned comparison table 138. integer trap instruction set index mnemonic instruction reference tw to ,r a ,r b trap word book e RM0004 instruction model 214/1176 for instructions that use the rotate 32 operation, the mask start and stop positions are always in bits 32?63 of the mask. the use of the mask is described in following sections. the rotate word and shift word instructions with rc = 1 set the first three bits of cr field 0 as described in book e. rotate and shift instructions do not change the ov and so bits. rotate and shift instructions, except algebraic right shifts, do not change the ca bit. the instructions in ta bl e 1 3 9 rotate the contents of a register. depending on the instruction type, the amount of the rotation is either specified as an immediate, or contained in a gpr. the instructions in ta bl e 1 4 0 rotate the contents of a register. depending on the instruction type, the result of the rotation is either inserted into the target register under control of a mask (if a mask bit is 1, the associated bit of the rotated data is placed into the target register; if a mask bit is 0, the associated bit in the target register remains unchanged) or anded with a mask before being placed into the target register. the rotate left instructions allow right-rotation of the contents of a register to be performed (in concept) by a left-rotation of 32- n , where n is the number of bits by which to rotate right. they allow right-rotation of the contents of bits 32?63 of a register to be performed (in concept) by a left-rotation of 32- n , where n is the number of bits by which to rotate right. the integer shift instru ctions are listed in table 141 . table 139. integer rotate instruction set index mnemonic instruction reference e_rlw r a ,r s ,r b rotate left word page -951 e_rlwi r a ,r s , sh rotate left word immediate page -951 table 140. integer rotate with mask instruction set index mnemonic instruction reference e_rlwimi r a ,r s , sh , mb , me rotate left word imm ediate then mask insert page -952 e_rlwinm r a ,r s , sh , mb , me rotate left word imm ediate then and with mask page -953 table 141. integer shift instruction set index mnemonic instru ction reference slw r a ,r s ,r b slw. r a ,r s ,r b se_slw r x ,r y shift left word page -955 e_slwi r a ,r s , sh se_slwi r x , ui5 shift left word immediate page -955 sraw r a ,r s ,r b sraw. r a ,r s ,r b se_sraw r x ,r y shift right algebraic word page -956 srawi r a ,r s , sh srawi. r a ,r s , sh se_srawi r x , ui5 shift right algebraic word immediate page -956 instruction model RM0004 215/1176 srw r a ,r s ,r b srw. r a ,r s ,r b se_srw r x ,r y shift right word page -957 e_srwi r a ,r s , sh se_srwi r x , ui5 shift right word immediate page -957 table 141. integer shift instruction set index mnemonic instru ction reference RM0004 instruction model 216/1176 storage control instructions this section lists storage control inst ructions, which include the following: storage synchronization instructions on page 216? cache management instructions on page 216? tlb management instructions on page 216? storage synchronization instructions the memory synchronization instructions implemented by the vle extension are identical to those defined in book e. the storage synchronization instructions are listed in ta bl e 1 4 2 . cache management instructions cache management instructions implemented by the vle extension are identical to those defined in book e. the cache management instructions are listed in ta b l e 1 4 3 . tlb management instructions the tlb management instructions implemented by the vle extension are identical to those defined in book e and in the eis. the tlb management instructions are listed in ta b l e 1 4 4 . table 142. storage synchronization instruction set index mnemonic instruction reference mbar memory barrier book e msync memory synchronize book e table 143. cache management instruction set index mnemonic instruction reference dcba r a ,r b data cache block allocate book e dcbf r a ,r b data cache block flush book e dcbi r a ,r b data cache block invalidate book e dcbst r a ,r b data cache block store book e dcbt ct ,r a ,r b data cache block touch book e dcbtst ct ,r a ,r b data cache block touch for store book e dcbz r a ,r b data cache block set to zero book e icbi r a ,r b instruction cache block invalidate book e icbt ct ,r a ,r b instruction cache block touch book e instruction model RM0004 217/1176 vle instruction alignment and byte ordering an instruction fetched from memory must be placed in the pipeline with its bytes in the proper order. otherwise, the instruction decoder cannot recognize it. book e allows instructions to be placed into memory marked as either big- or little-endian. this is manageable because book e instructions are always word-size aligned on word boundaries. the vle extension includes both half-word? and word-length instructions are aligned on half-word boundaries. because of this, only big-endian instruction memory is supported when executing from a page of vle instructions. attempts to execute vle instructions from a page marked as little-endian generate an instruction storage interrupt byte-ordering exception. instruction listings this section lists instructions either defined or supported by the vle extension. table 145 lists instructions by instruction name. table 144. tlb management instruction set index mnemonic instruction reference tlbivax r a ,r b tlb invalidate virtual address indexed book e tlbre tlb read entry book e tlbsx r a ,r b tlb search indexed book e tlbsync tlb synchronize book e tlbwe tlb write entry book e table 145. instructions listed by name instruction mnemonic reference add add r d ,r a ,r b add. r d ,r a ,r b addo r d ,r a ,r b addo. r d ,r a ,r b book e add carrying addc r d ,r a ,r b addc. r d ,r a ,r b addco r d ,r a ,r b addco. r d ,r a ,r b book e add extended adde r d ,r a ,r b adde. r d ,r a ,r b addeo r d ,r a ,r b addeo. r d ,r a ,r b book e and with complement andc [ . ] r a ,r s ,r b se_andc r x ,r y book e page -901 and and [ . ] r a ,r s ,r b se_and [ . ] r x ,r y book e page -901 compare cmp cr d , l ,r a ,r b se_cmp r x ,r y book e page -912 RM0004 instruction model 218/1176 compare logical cmpl cr d , l ,r a ,r b se_cmpl r x ,r y book e page -918 count leading zeros word cntlzw r a ,r s cntlzw. r a ,r s book e data cache block allocate dcba r a ,r b book e data cache block flush dcbf r a ,r b book e data cache block invalidate dcbi r a ,r b book e data cache block store dcbst r a ,r b book e data cache block touch dcbt ct ,r a ,r b book e data cache block touch for store dcbtst ct ,r a ,r b book e data cache block set to zero dcbz r a ,r b book e divide word divw r d ,r a ,r b divw. r d ,r a ,r b divwo r d ,r a ,r b divwo. r d ,r a ,r b book e divide word unsigned divwu r d ,r a ,r b divwu. r d ,r a ,r b divwuo r d ,r a ,r b divwuo. r d ,r a ,r b book e equivalent eqv r a ,r s ,r b eqv. r a ,r s ,r b book e extend sign byte extsb r a ,r s extsb. r a ,r s se_extsb r x book e book e page -926 extend sign halfword extsh r a ,r s extsh. r a ,r s se_extsh r x book e book e page -926 add immediate shifted e_add2is r d , si page -897 add immediate e_addi r d ,r a , sci8 e_addi. r d ,r a , sci8 e_add16i r d ,r a , si e_add2i. r d , si se_addi r x , oimm page -897 add immediate carrying e_addic r d ,r a , sci8 e_addic. r d ,r a , sci8 page -900 and immediate shifted e_and2is. r d , ui page -901 and immediate e_andi [ . ] r a ,r s , sci8 se_andi r x , ui5 e_and2i. r d , ui page -901 table 145. instructions listed by name (continued) instruction mnemonic reference instruction model RM0004 219/1176 branch conditional branch conditional branch conditional & link e_bc bo32 , bi32 , bd15 se_bc bo16 , bi16 , bd8 e_bcl bo32 , bi32 , bd15 page -904 branch branch & link e_b bd24 e_bl bd24 page -903 compare halfword e_cmph cr d ,r a ,r b se_cmph r x ,r y page -914 compare halfword immediate e_cmph16i r a , si16 page -914 compare halfword logical e_cmphl cr d ,r a ,r b se_cmphl r x ,r y page -916 compare halfword logical immediate e_cmphl16i r a , ui16 page -916 compare immediate e_cmpi cr d ,r a , sci8 e_cmp16i r a , si16 se_cmpi r x , ui5 page -912 compare logical immediate e_cmpli cr d ,r a , sci8 e_cmpl16i r a , ui16 se_cmpli r x , ui5 page -918 condition register and e_crand crb d ,crb a ,crb b page -920 condition register and with complement e_crandc crb d ,crb a ,crb b page -920 condition register equivalent e_creqv crb d ,crb a ,crb b page -920 condition register nand e_crnand crb d ,crb a ,crb b page -921 condition register nor e_crnor crb d ,crb a ,crb b page -922 condition register or e_cror crb d ,crb a ,crb b page -923 condition register or with complement e_crorc crb d ,crb a ,crb b page -924 condition register xor e_crxor crb d ,crb a ,crb b page -925 load byte and zero load byte and zero with update load byte and zero (16-bit form) e_lbz r d , d (r a ) e_lbzu r d , d8 (r a ) se_lbz r z , sd4 (r x ) page -930 load halfword algebraic load halfword algebraic with update e_lha r d , d (r a ) e_lhau r d , d8 (r a ) page -931 load halfword and zero load halfword and zero with update load halfword and zero (16-bit form) e_lhz r d , d (r a ) e_lhzu r d , d8 (r a ) se_lhz r z , sd4 (r x ) page -932 load immediate e_li r d , li20 se_li r x , ui7 page -933 load immediate shifted e_lis r d , ui page -933 load multiple word e_lmw r d , d8 (r a ) page -934 table 145. instructions listed by name (continued) instruction mnemonic reference RM0004 instruction model 220/1176 load word and zero load word and zero with update load word and zero (16-bit form) e_lwz r d , d (r a ) e_lwzu r d , d8 (r a ) se_lwz r z , sd4 (r x ) page -935 move condition register field e_mcrf cr d ,cr s page -936 multiply low immediate e_mulli r d ,r a , sci8 e_mull2i r d , si page -944 or immediate shifted e_or2is r d , ui page -948 or immediate e_ori [ . ] r a ,r s , sci8 e_or2i r d , ui page -948 rotate left word e_rlw r a ,r s ,r b page -951 rotate left word immediate e_rlwi r a ,r s , sh page -951 rotate left word immediate then mask insert e_rlwimi r a ,r s , sh , mb , me page -952 rotate left word immediate then and with mask e_rlwinm r a ,r s , sh , mb , me page -953 shift left word immediate e_slwi r a ,r s , sh se_slwi r x , ui5 page -955 shift right word immediate e_srwi r a ,r s , sh se_srwi r x , ui5 page -957 store byte store byte with update store byte (16-bit form) e_stb r s , d (r a ) e_stbu r s , d8 (r a ) se_stb r z , sd4 (r x ) page -958 store halfword store halfword with update store halfword (16-bit form) e_sth r s , d (r a ) e_sthu r s , d8 (r a ) se_sth r z , sd4 (r x ) page -959 store multiple word e_stmw r s , d8 (r a ) page -960 store word store word with update store word (16-bit form) e_stw r s , d (r a ) e_stwu r s , d8 (r a ) se_stw r z , sd4 (r x ) page -961 subtract from immediate carrying e_subfic r d ,r a , sci8 e_subfic. r d ,r a , sci8 page -964 xor immediate e_xori [ . ] r a ,r s , sci8 page -966 instruction cache block invalidate icbi r a ,r b book e instruction cache block touch icbt ct ,r a ,r b book e integer select isel r d ,r a ,r b ,cr beis load byte and zero indexed load byte and zero with update indexed lbzx r d ,r a ,r b lbzux r d ,r a ,r b book e load halfword algebraic indexed load halfword algebraic with update indexed lhax r d ,r a ,r b lhaux r d ,r a ,r b book e load halfword byte-reverse indexed lhbrx r d ,r a ,r b book e table 145. instructions listed by name (continued) instruction mnemonic reference instruction model RM0004 221/1176 load halfword and zero indexed load halfword and zero with update indexed lhzx r d ,r a ,r b lhzux r d ,r a ,r b book e load word and reserve indexed lwarx r d ,r a ,r b book e load word byte-reverse indexed lwbrx r d ,r a ,r b book e load word and zero indexed load word and zero with update indexed lwzx r d ,r a ,r b lwzux r d ,r a ,r b book e memory barrier mbar book e move to condition register from integer exception register mcrxr cr d book e move from condition register mfcr r d book e move from device control register mfdcr r d , dcrn book e move from machine state register mfmsr r d book e move from special purpose register mfspr r d , sprn book e memory synchronize msync book e move to condition register fields mtcrf fxm ,r s book e move to device control register mtdcr dcrn,r s book e move to machine state register mtmsr r s book e move to special purpose register mtspr sprn,r s book e multiply high word mulhw r d ,r a ,r b mulhw. r d ,r a ,r b book e multiply high word unsigned mulhwu r d ,r a ,r b mulhwu. r d ,r a ,r b book e multiply low word mullw r d ,r a ,r b mullw. r d ,r a ,r b mullwo r d ,r a ,r b mullwo. r d ,r a ,r b book e nand nand r a ,r s ,r b nand. r a ,r s ,r b book e negate neg r d ,r a se_neg r x neg. r d ,r a nego r d ,r a nego. r d ,r a book e page -946 book e book e book e nor nor r a ,r s ,r b nor. r a ,r s ,r b book e or or r a ,r s ,r b or. r a ,r s ,r b se_or r x ,r y book e book e page -948 table 145. instructions listed by name (continued) instruction mnemonic reference RM0004 instruction model 222/1176 or with complement orc r a ,r s ,r b orc. r a ,r s ,r b book e add se_add r x ,r y page -897 bit clear se_bclri r x , ui5 page -905 branch to count register branch to count register & link se_bctr se_bctrl page -906 bit generate se_bgeni r x , ui5 page -907 branch to link register branch to link register & link se_blr se_blrl page -908 bit mask generate se_bmski r x , ui5 page -909 bit set se_bseti r x , ui5 page -910 branch branch & link se_b bd8 se_bl bd8 page -903 bit test immediate se_btsti r x , ui5 page -911 extend with zeros byte se_extzb r x page -927 extend with zeros halfword se_extzh r x page -927 instruction synchronize se_isync page -929 move from alternate register se_mfar r x ,ar y page -937 move from count register se_mfctr r x page -938 move from link register se_mflr r x page -939 move register se_mr r x ,r y page -940 move to alternate register se_mtar ar x ,r y page -941 move to count register se_mtctr r x page -942 move to link register se_mtlr r x page -943 multiply low word se_mullw r x ,r y page -945 not se_not r x page -947 subtract se_sub r x ,r y page -962 subtract from se_subf r x ,r y page -963 subtract immediate se_subi r x , oimm se_subi. r x , oimm page -965 shift left word slw r a ,r s ,r b slw. r a ,r s ,r b se_slw r x ,r y book e book e page -955 shift right algebraic word sraw r a ,r s ,r b sraw. r a ,r s ,r b se_sraw r x ,r y book e book e page -956 table 145. instructions listed by name (continued) instruction mnemonic reference instruction model RM0004 223/1176 table 145 lists instructions that can be executed in vle mode by mnemonic. shift right algebraic word immediate srawi r a ,r s , sh srawi. r a ,r s , sh se_srawi r x , ui5 book e book e page -956 shift right word srw r a ,r s ,r b srw. r a ,r s ,r b se_srw r x ,r y book e book e page -957 store byte indexed store byte with update indexed stbx r s ,r a ,r b stbux r s ,r a ,r b book e store halfword byte-reverse indexed sthbrx r s ,r a ,r b book e store halfword indexed store halfword with update indexed sthx r s ,r a ,r b sthux r s ,r a ,r b book e store word byte-reverse indexed stwbrx r s ,r a ,r b book e store word conditional indexed stwcx. r s ,r a ,r b book e store word indexed store word with update indexed stwx r s ,r a ,r b stwux r s ,r a ,r b book e subtract from subf r d ,r a ,r b subf. r d ,r a ,r b subfo r d ,r a ,r b subfo. r d ,r a ,r b book e subtract from carrying subfc r d ,r a ,r b subfc. r d ,r a ,r b subfco r d ,r a ,r b subfco. r d ,r a ,r b book e tlb invalidate virtual address indexed tlbivax r a ,r b book e tlb read entry tlbre book e tlb search indexed tlbsx r a ,r b book e tlb synchronize tlbsync book e tlb write entry tlbwe book e trap word tw to ,r a ,r b book e write msr external enable wrtee r a book e write msr external enable immediate wrteei e book e xor xor r a ,r s ,r b xor. r a ,r s ,r b book e table 145. instructions listed by name (continued) instruction mnemonic reference RM0004 instruction model 224/1176 table 146. instructions listed by mnemonic mnemonic instruction reference add r d ,r a ,r b add. r d ,r a ,r b addo r d ,r a ,r b addo. r d ,r a ,r b add book e addc r d ,r a ,r b addc. r d ,r a ,r b addco r d ,r a ,r b addco. r d ,r a ,r b add carrying book e adde r d ,r a ,r b adde. r d ,r a ,r b addeo r d ,r a ,r b addeo. r d ,r a ,r b add extended book e andc [ . ] r a ,r s ,r b and with complement book e and [ . ] r a ,r s ,r band book e cmp cr d , l ,r a ,r b compare book e cmpl cr d , l ,r a ,r b compare logical book e cntlzw r a ,r s cntlzw. r a ,r s count leading zeros word book e dcba r a ,r b data cache block allocate book e dcbf r a ,r b data cache block flush book e dcbi r a ,r b data cache block invalidate book e dcbst r a ,r b data cache block store book e dcbt ct ,r a ,r b data cache block touch book e dcbtst ct ,r a ,r b data cache block touch for store book e dcbz r a ,r b data cache block set to zero book e divw r d ,r a ,r b divw. r d ,r a ,r b divwo r d ,r a ,r b divwo. r d ,r a ,r b divide word book e divwu r d ,r a ,r b divwu. r d ,r a ,r b divwuo r d ,r a ,r b divwuo. r d ,r a ,r b divide word unsigned book e eqv r a ,r s ,r b eqv. r a ,r s ,r b equivalent book e extsb r a ,r s extsb. r a ,r s extend sign byte book e extsh r a ,r s extsh. r a ,r s extend sign halfword book e instruction model RM0004 225/1176 e_add2is r d , si add immediate shifted page -897 e_addi r d ,r a , sci8 e_addi. r d ,r a , sci8 e_add16i r d ,r a , si e_add2i. r d , si add immediate page -897 e_addic r d ,r a , sci8 e_addic. r d ,r a , sci8 add immediate carrying page -900 e_and2is. r d , ui and immediate shifted page -901 e_andi [ . ] r a ,r s , sci8 e_and2i. r d , ui and immediate page -901 e_bc bo32 , bi32 , bd15 e_bcl bo32 , bi32 , bd15 branch conditional branch conditional & link -904page e_b bd24 e_bl bd24 branch branch & link page -903 e_cmph cr d ,r a ,r b compare halfword page -914 e_cmph16i r a , si16 compare halfword immediate page -914 e_cmphl cr d ,r a ,r b compare halfword logical page -916 e_cmphl16i r a , ui16 compare halfword logical immediate page -916 e_cmpi cr d ,r a , sci8 e_cmp16i r a , si16 compare immediate page -912 e_cmpli cr d ,r a , sci8 e_cmpl16i r a , ui16 compare logical immediate page -918 e_crand crb d ,crb a ,crb b condition register and page -920 e_crandc crb d ,crb a ,crb b condition register and with complement page -920 e_creqv crb d ,crb a ,crb b condition register equivalent page -920 e_crnand crb d ,crb a ,crb b condition register nand page -921 e_crnor crb d ,crb a ,crb b condition register nor page -922 e_cror crb d ,crb a ,crb b condition register or page -923 e_crorc crb d ,crb a ,crb b condition register or with complement page -924 e_crxor crb d ,crb a ,crb b condition register xor page -925 e_lbz r d , d (r a ) e_lbzu r d , d8 (r a ) load byte and zero load byte and zero with update page -930 e_lha r d , d (r a ) e_lhau r d , d8 (r a ) load halfword algebraic load halfword algebraic with update page -931 e_lhz r d , d (r a ) e_lhzu r d , d8 (r a ) load halfword and zero load halfword and zero with update page -932 e_li r d , li20 load immediate page -933 e_lis r d , ui load immediate shifted page -933 table 146. instructions listed by mnemonic (continued) mnemonic instruction reference RM0004 instruction model 226/1176 e_lmw r d , d8 (r a ) load multiple word page -935 e_lwz r d , d (r a ) e_lwzu r d , d8 (r a ) load word and zero load word and zero with update page -936 e_mcrf cr d ,cr s move condition register field page -944 e_mulli r d ,r a , sci8 e_mull2i r d , si multiply low immediate page -948 e_or2is r d , ui or immediate shifted page -948 e_ori [ . ] r a ,r s , sci8 e_or2i r d , ui or immediate page -951 e_rlw r a ,r s ,r b rotate left word page -951 e_rlwi r a ,r s , sh rotate left word immediate page -952 e_rlwimi r a ,r s , sh , mb , me rotate left word im mediate then mask insert page -953 e_rlwinm r a ,r s , sh , mb , me rotate left word immediate then and with mask page -955 e_slwi r a ,r s , sh shift left word immediate page -935 e_srwi r a ,r s , sh shift right word immediate book e e_stb r s , d (r a ) e_stbu r s , d8 (r a ) store byte store byte with update page -958 e_sth r s , d (r a ) e_sthu r s , d8 (r a ) store halfword store halfword with update page -959 e_stmw r s , d8 (r a ) store multiple word page -960 e_stw r s , d (r a ) e_stwu r s , d8 (r a ) store word store word with update page -961 e_subfic r d ,r a , sci8 e_subfic. r d ,r a , sci8 subtract from immediate carrying page -964 e_xori [ . ] r a ,r s , sci8 xor immediate page -966 icbi r a ,r b instruction cache block invalidate book e icbt ct ,r a ,r b instruction cache block touch book e isel r d ,r a ,r b ,cr b integer select eis lbzx r d ,r a ,r b lbzux r d ,r a ,r b load byte and zero indexed load byte and zero with update indexed book e lhax r d ,r a ,r b lhaux r d ,r a ,r b load halfword algebraic indexed load halfword algebraic with update indexed book e lhbrx r d ,r a ,r b load halfword byte-reverse indexed book e lhzx r d ,r a ,r b lhzux r d ,r a ,r b load halfword and zero indexed load halfword and zero with update indexed book e lwarx r d ,r a ,r b load word and reserve indexed book e lwbrx r d ,r a ,r b load word byte-reverse indexed book e table 146. instructions listed by mnemonic (continued) mnemonic instruction reference instruction model RM0004 227/1176 lwzx r d ,r a ,r b lwzux r d ,r a ,r b load word and zero indexed load word and zero with update indexed book e mbar memory barrier book e mcrxr cr d move to condition register from integer exception register book e mfcr r d move from condition register book e mfdcr r d , dcrn move from device control register book e mfmsr r d move from machine state register book e mfspr r d , sprn move from special purpose register book e msync memory synchronize book e mtcrf fxm ,r s move to condition register fields book e mtdcr dcrn,r s move to device control register book e mtmsr r s move to machine state register book e mtspr sprn,r s move to special purpose register book e mulhw r d ,r a ,r b mulhw. r d ,r a ,r b multiply high word book e mulhwu r d ,r a ,r b mulhwu. r d ,r a ,r b multiply high word unsigned book e mullw r d ,r a ,r b mullw. r d ,r a ,r b mullwo r d ,r a ,r b mullwo. r d ,r a ,r b multiply low word book e nand r a ,r s ,r b nand. r a ,r s ,r b nand book e neg r d ,r a neg. r d ,r a nego r d ,r a nego. r d ,r a negate book e nor r a ,r s ,r b nor. r a ,r s ,r b nor book e or r a ,r s ,r b or. r a ,r s ,r b or book e orc r a ,r s ,r b orc. r a ,r s ,r b or with complement book e se_add r x ,r yadd page -897 se_addi r x , oimm add immediate page -897 se_andc r x ,r y and with complement page -901 se_andi r x , ui5 and immediate page -901 table 146. instructions listed by mnemonic (continued) mnemonic instruction reference RM0004 instruction model 228/1176 se_and [ . ] r x ,r yand page -901 se_bc bo16 , bi16 , bd8 branch conditional page -904 se_bclri r x , ui5 bit clear page -905 se_bctr se_bctrl branch to count register branch to count register & link page -905 se_bgeni r x , ui5 bit generate page -906 se_blr se_blrl branch to link register branch to link register & link page -907 se_bmski r x , ui5 bit mask generate page -908 se_bseti r x , ui5 bit set page -909 se_b bd8 se_bl bd8 branch branch & link page -910 se_btsti r x , ui5 bit test immediate page -903 se_cmp r x ,r y compare page -912 se_cmph r x ,r y compare halfword page -914 se_cmphl r x ,r y compare halfword logical page -916 se_cmpi r x , ui5 compare immediate page -912 se_cmpl r x ,r y compare logical page -918 se_cmpli r x , ui5 compare logical immediate page -918 se_extsb r x extend sign byte page -926 se_extsh r x extend sign halfword page -926 se_extzb r x extend with zeros byte page -927 se_extzh r x extend with zeros halfword page -927 se_isync instruction synchronize page -929 se_lbz r z , sd4 (r x ) load byte and zero (16-bit form) page -930 se_lhz r z , sd4 (r x ) load halfword and zero (16-bit form) page -932 se_li r x , ui7 load immediate page -933 se_lwz r z , sd4 (r x ) load word and zero (16-bit form) page -935 se_mfar r x ,ar y move from alternate register page -937 se_mfctr r x move from count register page -938 se_mflr r x move from link register page -939 se_mr r x ,r y move register page -940 se_mtar ar x ,r y move to alternate register page -941 se_mtctr r x move to count register page -942 se_mtlr r x move to link register page -943 table 146. instructions listed by mnemonic (continued) mnemonic instruction reference instruction model RM0004 229/1176 se_mullw r x ,r y multiply low word page -945 se_neg r x negate page -946 se_not r xnot page -947 se_or r x ,r yor page -948 se_slw r x ,r y shift left word page -955 se_slwi r x , ui5 shift left word immediate page -955 se_sraw r x ,r y shift right algebraic word page -956 se_srawi r x , ui5 shift right algebraic word immediate page -956 se_srw r x ,r y shift right word page -957 se_srwi r x , ui5 shift right word immediate page -957 se_stb r z , sd4 (r x ) store byte (16-bit form) page -958 se_sth r z , sd4 (r x ) store halfword (16-bit form) page -959 se_stw r z , sd4 (r x ) store word (16-bit form) page -961 se_sub r x ,r y subtract page -962 se_subf r x ,r y subtract from page -963 se_subi r x , oimm se_subi. r x , oimm subtract immediate page -965 slw r a ,r s ,r b slw. r a ,r s ,r b shift left word book e sraw r a ,r s ,r b sraw. r a ,r s ,r b shift right algebraic word book e srawi r a ,r s , sh srawi. r a ,r s , sh shift right algebraic word immediate book e srw r a ,r s ,r b srw. r a ,r s ,r b shift right word book e stbx r s ,r a ,r b stbux r s ,r a ,r b store byte indexed store byte with update indexed book e sthbrx r s ,r a ,r b store halfword byte-reverse indexed book e sthx r s ,r a ,r b sthux r s ,r a ,r b store halfword indexed store halfword with update indexed book e stwbrx r s ,r a ,r b store word byte-reverse indexed book e stwcx. r s ,r a ,r b store word conditional indexed book e stwx r s ,r a ,r b stwux r s ,r a ,r b store word indexed store word with update indexed book e table 146. instructions listed by mnemonic (continued) mnemonic instruction reference RM0004 instruction model 230/1176 3.7 instruction listing table 147 lists instructions defined in book e, in the powerpc architecture, and by the eis. a check mark ( ) or text in a column indicates that the instruction is defined or implemented. the eis-specific instructions are indicated by the name of the apu or architectural extension that defines the instruction. subf r d ,r a ,r b subf. r d ,r a ,r b subfo r d ,r a ,r b subfo. r d ,r a ,r b subtract from book e subfc r d ,r a ,r b subfc. r d ,r a ,r b subfco r d ,r a ,r b subfco. r d ,r a ,r b subtract from carrying book e tlbivax r a ,r b tlb invalidate virtual address indexed book e tlbre tlb read entry book e tlbsx r a ,r b tlb search indexed book e tlbsync tlb synchronize book e tlbwe tlb write entry book e tw to ,r a ,r btrap word book e wrtee r a write msr external enable book e wrteei e write msr external enable immediate book e xor r a ,r s ,r b xor. r a ,r s ,r b xor book e table 146. instructions listed by mnemonic (continued) mnemonic instruction reference table 147. list of instructions mnemonic book e classic eis mn emonic book e classic eis addc [ o ][ . ] ? e_cmpli vle adde [ o ][ . ] ? e_crand vle addi ? e_crandc vle addic [ . ] ? e_creqv vle addis ? e_crnand vle addme [ o ][ . ] ? e_crnor vle addze [ o ][ . ] ? e_cror vle add [ o ] . ] ? e_crorc vle andc [ . ] ? e_crxor vle andi. ? e_lbz vle instruction model RM0004 231/1176 andis. ? e_lbzu vle and [ . ] ? e_lha vle b ? e_lhau vle ba ? e_lhz vle bc ? e_lhzu vle bca ? e_li vle bcctr ? e_lis vle bcctrl ? e_lmw vle bcl ? e_lwz vle bcla ? e_lwzu vle bclr ? e_mcrf vle bclrl ? e_mull2i vle bl ? e_mulli vle bla ? e_or2i vle brinc spe apu e_or2is vle cmp ? e_ori [ . ]vle cmpi ? e_rlw vle cmpl ? e_rlwi vle cmpli ? e_rlwimi vle cntlzw [ . ] ? e_rlwinm vle crand ? e_slwi vle crandc ? e_srwi vle creqv ? e_stb vle crnand ? e_stbu vle crnor ? e_sth vle cror ? e_sthu vle crorc ? e_stmw vle crxor ? e_stw vle dcba ? e_stwu vle dcbf ? e_subfic vle dcbi ? e_subfic. vle dcblc cache locking e_xori [ . ]vle dcbst ? fabs [ . ] ? table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis RM0004 instruction model 232/1176 dcbt ? fadds [ . ] ? dcbtls cache locking fadd [ . ] ? dcbtst ? fcfid [ . ] ? dcbtstls cache locking fcmpo ? dcbz ? fcmpu ? divwu [ o ][ . ] ? fctidz [ . ] ? divw [ o ][ . ] ? fctid [ . ] ? eciwx fctiwz [ . ] ? ecowx fctiw [ . ] ? efsabs scalar spfp fdivs [ . ] ? efsadd scalar spfp fdiv [ . ] ? efscfsf scalar spfp fmadds [ . ] ? efscfsi scalar spfp fmadd [ . ] ? efscfuf scalar spfp fmr [ . ] ? efscfui scalar spfp fmsubs [ . ] ? efscmpeq scalar spfp fmsub [ . ] ? efscmpgt scalar spfp fmuls [ . ] ? efscmplt scalar spfp fmul [ . ] ? efsctsf scalar spfp fnabs [ . ] ? efsctsi scalar spfp fneg [ . ] ? efsctsiz scalar spfp fnmadds [ . ] ? efsctuf scalar spfp fnmadd [ . ] ? efsctui scalar spfp fnmsubs [ . ] ? efsctuiz scalar spfp fnmsub [ . ] ? table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis instruction model RM0004 233/1176 efsdiv scalar spfp fres [ . ] ? efsmul scalar spfp frsp [ . ] ? efsnabs scalar spfp frsqrte [ . ] ? efsneg scalar spfp fsel [ . ] ? efssub scalar spfp fsqrts [ . ] ? efststeq scalar spfp fsqrt [ . ] ? efststgt scalar spfp fsubs [ . ] ? efststlt scalar spfp fsub [ . ] ? eieio now mbar icbi ? eqv [ . ] ? icblc cache locking evabs spe apu icbt evaddiw spe apu icbtls cache locking evaddsmiaaw spe apu isel integer select evaddssiaaw spe apu isync ? evaddumiaaw spe apu lbz ? evaddusiaaw spe apu lbzu ? evaddw spe apu lbzux ? evand spe apu lbzx ? evandc spe apu ld evcmpeq spe apu ldarx evcmpgts spe apu ldu table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis RM0004 instruction model 234/1176 evcmpgtu spe apu ldux evcmplts spe apu ldx evcmpltu spe apu lfd ? evcntlsw spe apu lfdu ? evcntlzw spe apu lfdux ? evdivws spe apu lfdx ? evdivwu spe apu lfs ? eveqv spe apu lfsu ? evextsb spe apu lfsux ? evextsh spe apu lfsx ? evfsabs vector spfp lha ? evfsadd vector spfp lhau ? evfscfsf vector spfp lhaux ? evfscfsi vector spfp lhax ? evfscfuf vector spfp lhbrx ? evfscfui vector spfp lhz ? evfscmpeq vector spfp lhzu ? evfscmpgt vector spfp lhzux ? evfscmplt vector spfp lhzx ? evfsctsf vector spfp lmw ? evfsctsi vector spfp lswi ? table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis instruction model RM0004 235/1176 evfsctsiz vector spfp lswx ? evfsctuf vector spfp lwa evfsctui vector spfp lwarx ? evfsctuiz vector spfp lwaux evfsdiv vector spfp lwax evfsmul vector spfp lwbrx ? evfsnabs vector spfp lwz ? evfsneg vector spfp lwzu ? evfssub vector spfp lwzux ? evfststeq vector spfp lwzx ? evfststgt vector spfp mbar evfststlt vector spfp mcrf ? evldd spe apu mcrfs ? evlddx spe apu mcrxr ? evldh spe apu mfapidi evldhx spe apu mfcr ? evldw spe apu mfdcr evldwx spe apu mffs [ . ] ? evlhhesplat spe apu mfmsr ? evlhhesplatx spe apu mfpmr performa nce monitor table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis RM0004 instruction model 236/1176 evlhhossplat spe apu mfspr ? evlhhossplatx spe apu mfsr evlhhousplat spe apu mfsrin evlhhousplatx spe apu mftb evlwhe spe apu msync evlwhex spe apu mtcrf ? evlwhos spe apu mtdcr evlwhosx spe apu mtfsb0 [ . ] ? evlwhou spe apu mtfsb1 [ . ] ? evlwhoux spe apu mtfsfi [ . ] ? evlwhsplat spe apu mtfsf [ . ] ? evlwhsplatx spe apu mtmsr ? evlwwsplat spe apu mtmsrd 64-bit only evlwwsplatx spe apu mtpmr performa nce monitor evmergehi spe apu mtspr ? evmergehilo spe apu mtsr evmergelo spe apu mtsrd evmergelohi spe apu mtsrdin evmhegsmfaa spe apu mtsrin evmhegsmfan spe apu mulhd. table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis instruction model RM0004 237/1176 evmhegsmiaa spe apu mulhdu. evmhegsmian spe apu mulhwu [ . ] ? evmhegumiaa spe apu mulhw [ . ] ? evmhegumian spe apu mulld. evmhesmf spe apu mulldo. evmhesmfa spe apu mulli ? evmhesmfaaw spe apu mullw [ o ][ . ] ? evmhesmfanw spe apu nand [ . ] ? evmhesmi spe apu neg [ o ][ . ] ? evmhesmia spe apu nor [ . ] ? evmhesmiaaw spe apu orc [ . ] ? evmhesmianw spe apu ori ? evmhessf spe apu oris ? evmhessfa spe apu or [ . ] ? evmhessfaaw spe apu rfci evmhessfanw spe apu rfi ? evmhessiaaw spe apu rfid evmhessianw spe apu rfmci machine check evmheumi spe apu rldcl. evmheumia spe apu rldcr. evmheumiaaw spe apu rldic. table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis RM0004 instruction model 238/1176 evmheumianw spe apu rldicl. evmheusiaaw spe apu rldicr. evmheusianw spe apu rldimi. evmhogsmfaa spe apu rlwimi [ . ] ? evmhogsmfan spe apu rlwinm [ . ] ? evmhogsmiaa spe apu rlwnm [ . ] ? evmhogsmian spe apu sc ? evmhogumiaa spe apu se_add vle evmhogumian spe apu se_addi vle evmhosmf spe apu se_andc vle evmhosmfa spe apu se_andi vle evmhosmfaaw spe apu se_and [ . ]vle evmhosmfanw spe apu se_b vle evmhosmi spe apu se_bc vle evmhosmia spe apu se_bclri vle evmhosmiaaw spe apu se_bctr vle evmhosmianw spe apu se_bctrl vle evmhossf spe apu se_bgeni vle evmhossfa spe apu se_bl vle evmhossfaaw spe apu se_blr vle evmhossfanw spe apu se_blrl vle table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis instruction model RM0004 239/1176 evmhossiaaw spe apu se_bmski vle evmhossianw spe apu se_bseti vle evmhoumi spe apu se_btsti vle evmhoumia spe apu se_cmp vle evmhoumiaaw spe apu se_cmph vle evmhoumianw spe apu se_cmphl vle evmhousiaaw spe apu se_cmpi vle evmhousianw spe apu se_cmpl vle evmra spe apu se_cmpli vle evmwhsmf spe apu se_extsb vle evmwhsmfa spe apu se_extsh vle evmwhsmi spe apu se_extzb vle evmwhsmia spe apu se_extzh vle evmwhssf spe apu se_isync vle evmwhssfa spe apu se_lbz vle evmwhumi spe apu se_lhz vle evmwhumia spe apu se_li vle evmwlsmiaaw spe apu se_lwz vle evmwlsmianw spe apu se_mfar vle evmwlssiaaw spe apu se_mfctr vle evmwlssianw spe apu se_mflr vle table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis RM0004 instruction model 240/1176 evmwlumi spe apu se_mr vle evmwlumia spe apu se_mtar vle evmwlumiaaw spe apu se_mtctr vle evmwlumianw spe apu se_mtlr vle evmwlusiaaw spe apu se_mullw vle evmwlusianw spe apu se_neg vle evmwsmf spe apu se_not vle evmwsmfa spe apu se_or vle evmwsmfaa spe apu se_slw vle evmwsmfan spe apu se_slwi vle evmwsmi spe apu se_sraw vle evmwsmia spe apu se_srawi vle evmwsmiaa spe apu se_srw vle evmwsmian spe apu se_srwi vle evmwssf spe apu se_stb vle evmwssfa spe apu se_sth vle evmwssfaa spe apu se_stw vle evmwssfan spe apu se_sub vle evmwumi spe apu se_subf vle evmwumia spe apu se_subi vle evmwumiaa spe apu se_subi. vle table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis instruction model RM0004 241/1176 evmwumian spe apu slbia evnand spe apu slbie evneg spe apu sldi evnor spe apu slw [ . ] ? evor spe apu srad. evorc spe apu sradi. evrlw spe apu srawi [ . ] ? evrlwi spe apu sraw [ . ] ? evrndw spe apu srd. evsel spe apu srw [ . ] ? evslw spe apu stb ? evslwi spe apu stbu ? evsplatfi spe apu stbux ? evsplati spe apu stbx ? evsrwis spe apu std evsrwiu spe apu stdcx. evsrws spe apu stdu evsrwu spe apu stdux evstdd spe apu stdx evstddx spe apu stfd ? evstdh spe apu stfdu ? table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis RM0004 instruction model 242/1176 evstdhx spe apu stfdux ? evstdw spe apu stfdx ? evstdwx spe apu stfiwx ? evstwhe spe apu stfs ? evstwhex spe apu stfsu ? evstwho spe apu stfsux ? evstwhox spe apu stfsx ? evstwwex spe apu sth ? evstwwex spe apu sthbrx ? evstwwo spe apu sthu ? evstwwox spe apu sthux ? evsubfsmiaaw spe apu sthx ? evsubfssiaaw spe apu stmw ? evsubfumiaaw spe apu stswi ? evsubfusiaaw spe apu stswx ? evsubfw spe apu stw ? evsubifw spe apu stwbrx ? evxor spe apu stwcx. ? extsb [ . ] ? stwu ? extsh [ . ] ? stwux ? extsw. 64-bit only stwx ? e_add16i vle subfc [ o ][ . ] ? e_add2i. vle subfe [ o ][ . ] ? table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis instruction model RM0004 243/1176 e_add2is vle subfic ? e_addi vle subfme [ o ][ . ] ? e_addi. vle subfze [ o ][ . ] ? e_addic vle subf [ o ][ . ] ? e_addic. vle sync now msync e_and2i. vle tlbia e_and2is. vle tlbie e_andi [ . ]vle tlbivax e_b vle tlbre e_bc vle tlbsx e_bcl vle tlbsync ? e_bl vle tlbwe e_cmp16i vle tw ? e_cmph vle twi ? e_cmph16i vle wrtee e_cmphl vle wrteei e_cmphl16i vle xori [ . ] ? e_cmpi vle xor [ . ] ? e_cmpl16i vle table 147. list of instructions (continued) mnemonic book e classic eis mn emonic book e classic eis RM0004 interrupts and exceptions 244/1176 4 interrupts and exceptions this chapter provides a general description of the book e exception and interrupt models as they are implemented on st processors. it identifies and describes the portions of the interrupt model that are defined by the book e architecture and by the book e implementation standards (eis). note: : terminology the book e architecture has defined additional resources for interrupt handling. as a result, the terms ?interrupt? and ?exception? differ somewhat from their use in previous st documentation, such as the programming environments manual. use of these terms is now as follows: - an interupt is the action in which the proc essor saves its context (typically the machine state register (msr) and next instruction address) and begins execution at a predetermined interrupt handler address with a modified msr. - an exception is the event that, if enabled, causes the processor to take an interrupt. book e describes exceptions as being generated by signals from internal and external peripherals, instructions, the internal time r facility, debug events, or error conditions. 4.1 overview book e defines are two categories of interrup ts, noncritical and critical, for which separate resources are provided to save state when the interrupt is taken and to restore state when the interrupt handler returns control to the interrupted program. using the model provided by the book e architecture, the eis defines additional interrupt types which may be implemented on st book e devices. these are described in ta bl e 1 4 8 . table 148. interrupt types category description programming resources book e defined noncritical interrupts first-level interrupts that let the processor change program flow to handle conditions generated by external signals, errors, or unusual conditions arising from program execution or from programmable timer- related events. these interrupts are largely identical to those defined by the oea. srr0/srr1 sprs and rfi instruction. asynchronous noncritical interrupts can be masked by the external interrupt enable bit, msr[ee]. critical interrupts book e?defined. critical input, watchdog timer, and debug interr upts. these interrupts can be taken during a noncritical interrupt or during regular program flow. book e defines the critical input, watchdog timer, debug, and machine check interrupts as critical interrupts. the eis defines additional resources for machine check and debug interrupts. critical save and restore sprs (csrr0/csrr1) and the rfci instruction. critical input and watchdog timer critical interrupts can be masked by the critical enable bit, msr[ce]. debug events can be masked by the debug enable bit msr[de]. interrupts and exceptions RM0004 245/1176 all interrupts except eis-defined interrupts are ordered within the two categories of noncritical and critical, such that only one interrupt of each category is reported, and when an interrupt is processed (taken), no program state is lost. because save/restore register pairs are serially reusable, care must be taken to preserve program state that may be lost when an unordered interrupt is taken. (see chapter 4.10 .? ) all interrupts except the machine check interr upt are context synchronizing as defined in context synchronization on page 144 .? a machine check interrupt acts like a context- synchronizing operation with respect to subsequent instructions; that is, a machine check interrupt need not satisfy items 1 and 2 of context synchronization on page 144 ,? but satisfies items 3 and 4. eis defined (consult implem entation documentation to determine whether these in terrupts are implemented) machine check interrupt the eis-defined machine check apu provides a separate set of resources for the machine check interrupt, which is similar to the book e?defined crit ical interrupt type. machine check save and restore sprs (mcsrr0/mcsrr1) and the rfmci instruction. can be masked by the machine check enable bit, msr[me]. debug interrupt the eis-defined debug apu provides a separate set of resources for the debug interrupt, which is similar to the book e? defined critical interrupt type. debug save and restore sprs (dsrr0/dsrr1) and the rfdi instruction. can be masked by the machine check enable bit, msr[de]. the debug apu extends the book e debug register model for more detailed control of debug resources. table 148. interrupt types category description programming resources RM0004 interrupts and exceptions 246/1176 4.2 eis interrupt definitions this section gives an overview of additions and modifications to the book e interrupt model defined by the eis. specific details are also provided throughout this chapter. except for the following, the core comp lex reports exceptions as specified in book e: the machine check exception differs as follows: ? it is not processed as a critical interrupt, but uses mcsrr0 and mcsrr1 for saving the return address and the msr in case the machine check is recoverable. ? return from machine check interrupt instruction ( rfmci ) is implemented to support the return to the address saved in mcsrr0. ? a machine check syndrome register, mcsr, logs the cause of the machine check (instead of esr). the core complex reports the machine check exception as described in chapter 4.7.2 .? the following interrupts are defined for use with the embedded floating-point and signal-processi ng (spe) apus: ? spe/embedded floating-point unavailable interrupt. ivor32 (spr 528) contains the vector offset. see spe/embedded floating-point apu un available interrupt on page 272 .? ? embedded floating-point data interrupt. ivor33 (spr 529) contains the vector offset. see embedded floating-point data interrupt on page 272 .? ? embedded floating-point round interrupt. ivor34 (spr 530) contains the vector offset. see embedded floating-point round interrupt on page 273 .? the following additional bits are defined to support spe and spfp exceptions: ? msr[38] is defined as the ve ctor available bit (spe). if this bit is clear and software attempts to execute any of the spe instructions, the spe unavailable interrupt is taken. if this bit is set, software can execute any spe instructions. note: spfp instructions require ms r[spe] to be set. an attempt to execute an spfp instruction when msr[spe] is 0 causes an spe apu unavailable interrupt. embedded vector and scalar floating-point apu instructions on page 196 ,? lists affected instructions. ? esr[spe], the spe exception bit, is set wh en the processor re ports an exception related to the execution of spfp or spe instructions. the debug exception implementation does not support iac3, iac4, dac3, and dac4 comparisons. the core complex supports instruction address compare (iac1 and iac2) and data address compare (dac1 and dac2) for effective addresses only. real-address support is not provided. some implementations do not support the book e-defined floating-point unavailable and auxiliary processor un available interrupts. data value compare (dvc) debug exceptions are not supported. the interrupt priorities differ from those specified in book e as described in chapter 4.11 .? alignment exceptions. vector operations can cause alignment exceptions as described in chapter 4.7.6 .? book e and the machine check apu define sources of externally generated interrupts. interrupts and exceptions RM0004 247/1176 4.2.1 recoverability from interrupts all interrupts except some machine check interrupts are recoverable. the state of the core complex (return address and msr contents) is saved when a machine check interrupt is taken. the conditions that cause a machine check may or may not prohibit recovery. 4.3 interrupt registers table 149 summarizes registers used for interrupt handling. these registers are described in detail in chapter 2 .? RM0004 interrupts and exceptions 248/1176 table 149. interrupt registers defined by the powerpc architecture register description book e interrupt registers save/restore register 0 (srr0) on a noncritical interrupt, srr0 is se t to the current or next instruction address. when rfi is executed, instruction exec ution continues at the address in srr0. in general, srr0 contains th e address of the instruction that caused the noncritical interrupt or the address of the instruction to return to after a noncritical interrupt is serviced. save/restore register 1 (srr1) when a noncritical interrupt is taken, msr contents are placed into srr1. when rfi is executed, srr1 contents are plac ed into the msr. srr1 bits that correspond to reserved msr bits are also reserved. note that an msr bit that is reserved may be altered by rfi . critical save/restore register 0 (csrr0) when a critical interrupt is taken, csrr0 is set to the current or next instruction address. when rfci is executed, instruction execution continues at the address in csrr0. in general, csrr0 contains the address of the instruction that caused the critical interrupt, or the address of the instruction to return to after a critical interrupt is serviced. critical save/restore register 1 (csrr1) when a critical interrupt is taken, msr contents are placed into csrr1. when rfci is executed, csrr1 contents are placed into the msr. csrr1 bits that correspond to reserved msr bits are also reserved. note that an msr bit that is reserved may be altered by rfci . data exception address register (dear) dear contains the address referenced by a load, store, or cache management instruction that caused an alignment, data tlb miss, or data storage interrupt. interrupt vector prefix register (ivpr) ivpr[32?47] provides the high-order 48 bits of the address of the interrupt handling routine for each interrupt ty pe. the 16-bit vector offsets are concatenated to the right of ivpr to form the address of the interrupt handling routine. ivpr[48?63] are reserved. interrupts and exceptions RM0004 249/1176 exception syndrome register (esr) provides a syndrome to differentiate between exceptions that can generate the same interrupt type. when one of these types of interrupts is generated, bits corresponding to the specific exception that generated the interrupt are set and all other esr bits are cleared. other interrupt types do not affect the esr. esr does not need to be cleared by software. exception syndrome register (esr) on page 84 , ? shows esr bit definitions. an implementation may define additional esr bits to identify implementation- specific or architected interrupt types; the eis defines esr[ilk] and esr[spe]. note: system software may need to identify the type of instruction that caused the interrupt and examine the tlb entry and esr to fully identify the exception or exceptions. for example, because both protection violation and byte-ordering exception conditions may be present, and either causes a data storage interrupt, system software would have to look beyond esr[bo], such as the state of msr[pr] in srr1 and the tlb entry page protection bits, to determine if a protection violation also occurred. the eis defines esr[56] as the spe exc eption bit (spe). it is set when the processor reports an exception relate d to the execution of an spfp or spe instruction. note that the eis definition of the machine check interrupt uses the machine check syndrome register (mcsr) rather than the esr. table 149. interrupt registers defined by the powerpc architecture (continued) register description RM0004 interrupts and exceptions 250/1176 interrupt vector offset registers (ivors) holds the quad-word index from the base address provided by the ivpr for each interrupt type. ivor0?ivor15 are provided for defined interrupt types. spr numbers corresponding to ivor16?ivor31 are reserved. ivor[32? 47,60?63] are reserved. spr numbers for ivor32?ivor63 are allocated for implementation-dependent use. (ivor32?ivor34 (spr 528?530) are used by interrupts defined by the eis.) ivor assignments are shown below. book e?defined interrupts ivor number interrupt type ivor0 critical input ivor1 machine check ivor2 data storage ivor3 instruction storage ivor4 external input ivor5 alignment ivor6 program ivor7 floating-point unavailable ivor8 system call ivor9 auxiliary processor unavailable ivor10 decrementer ivor11 fixed-interval timer interrupt ivor12 watchdog timer interrupt ivor13 data tlb error ivor14 instruction tlb error ivor15 debug iivor16?ivor31 reserved eis-defined interrupts (ivor32? ivor63) ivor number interrupt type ivor32 spe apu unavailable ivor33 embedded floating- point data ivor34 embedded floating- point round ivor35 performance monitor ivor36 processor doorbell ivor37 processor doorbell critical machine state register (msr) msr[38] is defined as the vector availa ble bit (spe). it functions as follows: 0: if software attempts to execute an instruction that tries to access the upper word of a 64-bit gpr, an spe apu unavailable inte rrupt is taken. 1: software can execute any embedded floating-point or spe instructions. eis-specific inte rrupt registers machine check save/restore register 0 (mcsrr0) when a machine check interrupt is taken, mcsrr0 is set to the current or next instruction address. when rfmci is executed, instructio n execution continues at the address in mcsrr0. in general, mcsrr0 contains the address of the instruction that caused the machine check interrupt, or the address of the instruction to return to after a machine check interrupt is serviced. machine check save/restore register 1 (mcsrr1) when a machine check interrupt is taken, msr contents are placed into mcsrr1. when rfmci is executed, mcsrr1 cont ents are restored to msr. mcsrr1 bits that correspond to reserv ed msr bits are also reserved. note that an msr bit that is reserved may be altered by rfmci . table 149. interrupt registers defined by the powerpc architecture (continued) register description interrupts and exceptions RM0004 251/1176 machine check syndrome register (mcsr) when a machine check interrupt is taken, mcsr is updated to differentiate among machine check conditions. mcsr also indicates whether a machine check condition is recoverable. abist status is logged in mcsr[48?54]. these read-only bits do not initiate machine check (or any other interrupt). an abist bit being set indicates an error being detected in the corresponding module. processors that do not implement the machine check apu use the book e? defined esr for this purpose. machine check syndrome register (mcsr) on page 88 ,? shows mcsr bit definitions. machine check address register (mcar) when a machine check interrupt is taken, mcar is updated with the address of the data associated with the machine check. note that if a machine check interrupt is caused by a signal, the mcar contents are not meaningful. see machine check address register (mcar/mcaru) on page 88 .? table 149. interrupt registers defined by the powerpc architecture (continued) register description RM0004 interrupts and exceptions 252/1176 4.4 exceptions exceptions are caused directly by instruction execution or by an asynchronous event. in either case, the exception may cause one of several types of interrupts to be invoked. the following examples are of exceptions caused directly by instruction execution: an attempt to execute a reserved-illegal inst ruction (illegal instruction exception-type program interrupt) an attempt by an application program to execute a privileged instruction or to access a privileged spr (privileged instruction exception-type program interrupt) in general, an attempt by an application program to access a nonexistent spr (unimplemented operation instruction exception-type program interrupt). note the following behavior defined by the eis: ? if msr[pr] = 1 (user mode), spr bit 5 = 0 (user-accessible spr), and the spr number is invalid, an illegal in struction exception is taken. ? if msr[pr] = 0 (supervisor mode) and the spr number is invalid, an illegal instruction exception is taken. ? if msr[pr] = 1, spr bit 5 = 1, and invalid spr address (supervisor-only spr), a privileged instruction exception-type program interrupt is taken. execution of a defined instru ction using an invalid form (illegal instruction exception- type program interrupt, unimplemented operation exception-type program interrupt, or privileged instruction exception-type program interrupt). an attempt to access a location that is either unavailable (instruction or data tlb error interrupt) or not permitted (instruction or data storage interrupt) an attempt to access a location with an effective address alignment not supported by the implementation (alignment interrupt) execution of a system call ( sc ) instruction (system call interrupt) execution of a trap instruction whose trap condition is met (trap interrupt type) execution of a floating-point instruction when floating-point instructions are unavailable (floating-point unav ailable interrupt) execution of a floating-point instruction that causes a floating-point enabled exception to exist (enabled exception-type program interrupt) execution of a defined instruction that is not implemented (illegal instruction exception or unimplemented operation exception-type program interrupt) execution of an allocated instruction that is not implemented (illegal instruction exception or unimplemented operation exception-type program interrupt) execution of an allocated instruction when the auxiliary instruction is unavailable (auxiliary unavailable interrupt) execution of an allocated instruction th at causes an auxiliary enabled exception (enabled exception-type program interrupt) invocation of an interrupt is precise, except that if one of the imprecise modes for invoking a floating-point enabled exception-type program interrupt is in effect, the invocation may be imprecise. when the interrupt is invoked imprecisely, the excepting instruction does not appear to complete before the next instruction starts (because the invocation of the interrupt required to complete execution has not occurred). interrupts and exceptions RM0004 253/1176 4.5 interrupt classes all interrupts except machine check are categorized by two independent characteristics: critical/noncritical. some interrupt types demand immediate attention even if other interrupt types being processed have not had the opportunity to save the machine state (that is, return address and captured state of the msr). to enable taking a critical interrupt immediately after a noncritical interrupt is taken (that is, before the machine state is saved), two sets of save/restore register pairs are provided. critical interrupts use csrr0/csrr1, and noncritical interrupts use srr0/srr1. asynchronous/synchronous. asynchronous interrupts are caused by events external to instruction execution; synchronous interrupts are caused by instruction execution and are either precise or imprecise. ta bl e 1 5 0 describes asynchronous and synchronous interrupts. table 150. asynchronous and synchronous interrupts class description asynchronous caused by events independent from in struction execution. for asynchronous interrupts, the address reported to the in terrupt handling routine is the address of the instruction that would have executed next, had the asynchronous interrupt not occurred. RM0004 interrupts and exceptions 254/1176 4.5.1 requirements for sy stem reset generation book e does not specify a system reset interrupt as was defined in the aim version of the powerpc architecture. a system reset is typica lly initiated in one of the following ways: assertion of a signal that resets the internal state of the core complex by writing a 1 to dbcr0[34], if msr[de] = 1 synchronous, precise caused directly by instruction executio n. synchronous interr upts are precise or imprecise. these interrupts precisely indicate the address of the instruction causing the exception or, for certain synchronous, precise interrupt types, the address of the immediately following instruction. when the execution or attempted execution of an instruction causes a synchronous, precise in terrupt, the following conditions exist at the interrupt point: whether srr0 or csrr0 addresses the inst ruction causing the exception or the next instruction is determined by the interrupt type and status bits. an interrupt is generated such that all inst ructions before the instruction causing the exception appear to have completed with respect to the executing processor. however, some accesses associated with these preceding instructions may not have been performed with respect to other processors and mechanisms. the exception-causing instruction may appear not to have begun execution (except for causing the exception), may be partially executed, or may have completed, depending on the interrupt type. see chapter 4.9 .? architecturally, no instruction beyond th e exception-causing instruction executed. synchronous, imprecise imprecise interrupts may indicate the address of the instruction causing the exception that generated the interrupt or so me instruction after that instruction. when execution or attempted execution of an instruction causes an imprecise interrupt, the following conditions exist at the interrupt point. srr0 or csrr0 addresses either the exception-causing instruction or some instruction following the exception-causing instruction that generated the interrupt. an interrupt is generated such that a ll instructions preceding the instruction addressed by srr0 or csrr0 appear to have completed with respect to the executing processor. if context synchronization fo rces the imprecise interrupt due to an instruction that causes another exception that generates an interrupt (for example, alignment or data storage interrupt), srr0 addresses the interrupt-forcing instruction, which may have partially executed (see chapter 4.9 ? ). if execution synchronization forces an imprecise interrupt due to an execution- synchronizing instruction other than msync or isync , srr0 or csrr0 addresses the interrupt-forcing instruction, which a ppears not to have begun execution (except for its forcing the imprecise interrupt). if the interrupt is forced by msync or isync , srr0 or csrr0 may address msync or isync , or the following instruction. if context or execution synchronization forc es an imprecise interrupt, the instruction addressed by srr0 or csrr0 may have partially executed (see chapter 4.9 ? ). no instruction following the instruction ad dressed by srr0 or csrr0 has executed. table 150. asynchronous and synchronous interrupts (continued) class description interrupts and exceptions RM0004 255/1176 4.6 interrupt processing associated with each kind of interrupt is an interrupt vector, the address of the initial instruction that is executed when an interrupt occurs. interrupt processing consists of saving a small part of the processor?s state in certain registers, identifying the cause of the interrupt in another register, and continuing execution at the corresponding interrupt vector location. when an exception exists that causes an interrupt to be generated and it has been determined that the interrupt can be taken, the following steps are performed: 1. srr0 (for noncritical class interrupts) or csrr0 (for critical class interrupts) or mcsrr0 for machine check interrupts is loaded with an instruction address that depends on the type of interrupt; see the specific interrupt description for details. 2. the esr or mcsr is loaded with informatio n specific to the exception type. note that many interrupt types can only be caused by a single type of exception event, and thus do not need nor use an esr setting to indicate the cause of the interrupt. 3. srr1 (for noncritical class interrupts) or csrr1 (for critical class interrupts) or mcsrr1 for machine check interrupts is loaded with a copy of the msr contents. 4. new msr values take effect beginning with the first instruction following the interrupt. the msr is updated as follows: ? msr[spe,we,ee,pr,fp,fe0,fe1,is,ds] are cleared by all interrupts. ? msr[ce,de] are cleared by critical class interrupts and unchanged by noncritical class interrupts. ? msr[me] is cleared by machine check interrupts and unchanged by other interrupts. ? other defined msr bits are unchanged by all interrupts. msr fields are described in chapter 2.6.1: machine state register (msr) on page 68 .? 5. instruction fetching and execution resumes, using the new msr value, at a location specific to the interrupt type (ivpr[32?47] || ivor n [48?59] || 0b0000) the ivor n for the interrupt type is described in ta b l e 1 5 1 . ivpr and ivor contents are indeterminate upon reset and must be initialized by system software. interrupts do not clear reservations obtained with load and reserve instructions. the operating system should do so at appropriate points, such as at process switch. at the end of a noncritical interrupt handling routine, executing rfi causes the msr to be restored from the srr1 contents and instruction execution to resume at the address contained in srr0. likewise, rfci and rfmci perform the same function at the end of critical and machine check interrupt handling routines respectively, using the critical and machine check save/restore registers. note: in general, at process switch, due to possible process interlocks and possible data availability requirements , the operating system needs to consider executing the following: stwcx. ?clears outstanding reservations to prevent pairing a lwarx in the old process with a stwcx. in the new one msync ?ensures that memory operations of an interrupted process complete with respect to other processors before that process begins executing on another processor rfi , rfci , rfmci , or isync ?ensures that instructions in the new process execute in the new context RM0004 interrupts and exceptions 256/1176 4.7 interrupt definitions table 151 summarizes each interrupt type, the various exception types that may cause that interrupt, the interrupt classification, which esr bits can be set, which msr bits can mask the interrupt type, and which ivor is used to specify the vector address. table 151. interrupt and exception types ivor interrupt type exception type exception class (1) esr (2) mask bits notes page ivor0 critical input critical input a, c ? msr[ce] (3) 4.7.1 on page 258 ivor1 machine check machine check c ? msr[me] (4),(5) 4.7.2 on page 259 ivor2 data storage (dsi) access sp [spe],[st], [fp,ap] ? (6) 4.7.3 on page 260 load reserve or store conditional to write- through required location (w = 1) sp [st] ? 6 cache locking sp {dlk 0 ,dlk 1 } [dlk,ilk],[st] ? (7) byte ordering sp [st],[fp,ap],bo ? ? ivor3 instruction storage (isi) access sp ? ? ? 4.7.4 on page 262 byte ordering sp bo ? ? ivor4 external input a ? msr[ee] 3 4.7.5 on page 263 ivor5 alignment sp [st],[fp,ap], [spe,ap,st] ?? 4.7.6 on page 263 ivor6 program illegal sp pil ? ? 4.7.7 on page 265 privileged sp ppr,[ap] ? ? trap sp ptr ? ? floating-point enabled sp, si fp,[pie] msr[fe0,fe1] (8),(9) auxiliary processor enabled sp ap ? 9 unimplemented op sp puo,[fp,ap] ? 11 ivor7 floating-point unavailable sp ? 4.7.8 on page 267 ivor8 system call sp ? ? ? 4.7.9 on page 267 ivor9 auxiliary processor unavailable sp ? 4.7.10 on page 267 interrupts and exceptions RM0004 257/1176 ivor10 decrementer a? msr[ee], tcr[die] ? 4.7.11 on page 268 ivor11 fixed interval timer a? msr[ee], tcr[fie] ? 4.7.12 on page 268 ivor12 watchdog a, c ? msr[ce], tcr[wie] ? 4.7.13 on page 269 ivor13 data tlb error data tlb miss sp [spe],[st], [fp,ap] ?? 4.7.14 on page 269 ivor14 instruction tlb error instruction tlb miss sp ? ? ? 4.7.15 on page 270 ivor15 debug trap (synchronous) a, sp, c ? msr[de], dbcr0[idm] ? 4.7.16 on page 271 instruction address compare (synchronous) a, sp, c ? msr[de], dbcr0[idm] ? data address compare (synchronous) a, sp, c ? msr[de], dbcr0[idm] ? instruction complete sp, c ? msr[de], dbcr0[idm] (10) branch taken sp, c ? msr[de], dbcr0[idm] 10 return from interrupt sp, c ? msr[de], dbcr0[idm] ? interrupt taken si, c ? msr[de], dbcr0[idm] ? unconditional debug event si, c ? msr[de], dbcr0[idm] ? ivor32 spe / embedded fp apu unavailable spe apu unavailable sp ? ? (11) on page 272 ivor33 embedded fp data embedded fp data exception sp ? ? 11 on page 272 ivor34 embedded fp round embedded fp round exception sp ? ? 11 on page 273 1. a = asynchronous, c = critical, si = synchronous , imprecise, sp = synchronous, precise 2. in general, when an interrupt causes an esr bit or bits to be set (or cl eared) as indicated in the ta ble, it also causes all other esr bits to be cleared. special rules may apply for implementation-specific esr bits legend: xxx (no brackets) means esr[xxx] is set. [xxx] means esr[xxx] could be set. [xxx,yyy] means either esr[xxx] or esr[yyy] may be set, but never both. {xxx,yyy} means either esr[xxx] or esr[yyy] may be set, or possibly both. 3. although not part of book e, system interrupt controllers commonly provide independent mask and status bits for critical input and external input interrupt sources. table 151. interrupt and exception types (continued) ivor interrupt type exception type exception class (1) esr (2) mask bits notes page RM0004 interrupts and exceptions 258/1176 4.7.1 critical input interrupt a critical input interrupt occurs when no hig her priority exception exists, a critical input exception is presented to the interrupt mechanism, and msr[ce] = 1. the specific definition of a critical input exception is implementation-dependent but is typically caused by assertion of an asynchronous signal that is part of the system. in addition to msr[ce], implementations may provide other ways to mask the critical input interrupt. csrr0, csrr1, and msr are updated as shown in ta bl e 1 5 2 . instruction execution resumes at address ivpr[32?47] || ivor0[48?59] || 0b0000. critical interrupt input signals are level sensitive; to guarantee that the core complex can take a critical input interrupt, the critical input interrupt signal must be asserted until the interrupt is taken. otherwise, whether the core complex takes an critical interrupt depends on whether msr[ce] is set when the cr itical interrupt signal is asserted. note: to avoid redundant critical input interrupts, software must take any actions required by the implementation to clear any critical input exception status before reenabling msr[ce]. 4. machine check interrupts are not asynchronous or synchronous. see chapter 4.7.2 .? 5. machine check status information is commonly provided as par t of the system implementation but is not part of book e. 6. software must examine the instruction and the subject tl b entry to determine the exact cause of the interrupt. 7. cache locking and cache locking ex ceptions are implementation-dependent. 8. the precision of the floating-point enabled exception ty pe is controlled by msr[fe0,fe 1], as described in interrupts and exceptions RM0004 259/1176 4.7.2 machine check interrupt the eis defines the machine check apu, which differs from the book e definition of the machine check interrupt as follows: book e defines machine check interrupts as critical interrupts, but the machine check apu treats them as a distinct interrupt type. machine check is no longer a critical interrupt but uses mcsrr0 and mcsrr1 to save the return address and the msr in ca se the machine check is recoverable. return from machine chec k interrupt instruction ( rfmci ) is implemented to support the return to the address saved in mcsrr0. an address related to the machine check may be stored in mcar, according to ta bl e 1 5 3 . a machine check syndrome register, mcsr, is used to log the cause of the machine check (instead of esr). the mcsr is described in ta bl e 1 5 3 . the following general information applies to both the book e and eis definitions. a machine check interrupt occurs when no higher priority exception exists, a machine check exception is presented to the interrupt mechanism, and msr[me] = 1. specific causes of machine check exceptions are implementation-dependent, as are the details of the actions taken on a machine check interrupt. machine check interrupts are typically caused by a hardware or memo ry subsystem failure or by an attempt to access an invalid address. they may be caused indirectly by execution of an instruction, but may not be recognized or reported until long after the processor has executed past the instruction that caused the machine check. as such, machine check interrupts are not thought of as synchronous or asynchronous nor as precise or imprecise. the following general rules apply: no instruction after the one whose address is reported to the machine check interrupt handler in mcsrr0 has begun execution. the instruction whose address is reported to the machine check interrupt handler in mcsrr0 and all prior instructions may or may not have completed successfully. all instructions certain to complete appear to have done so within the context existing before the machine check interrupt. no further interrupts (other than possible additional machine check interrupts) occur as a result of those instructions. if msr[me] is cleared, the processor enters checkstop state immediately on detecting the machine check condition. when a machine check interrupt is taken, registers are updated as shown in ta b l e 1 5 3 . table 153. machine check interrupt settings register setting csrr0 (1) set to an instruction address. as closely as possible, set to the effective address of an instruction that was executing or about to be executing when the machine check exception occurred. csrr1 1 set to the msr contents at the time of the interrupt msr ucle, spe, we, ce, ee, pr, fp, me, fe0, fe1, de, is, ds, pmm, and ri are cleared. esr implementation-dependent. the eis us es the mcsr rather than the esr. machine check apu registers RM0004 interrupts and exceptions 260/1176 instruction execution resumes at address ivpr[32?47] || ivor1[48?59] || 0b0000. note: 1 if a memory subsystem error causes a machine check interrupt, the subsystem may return incorrect data, which may be placed into registers or on-chip caches. 2 for implementations on which a machine check interrupt is caused by referring to an invalid physical address, executing dcbz or dcba can cause a delayed machine check interrupt by establishing a data cache block associated with an invalid physical address. a machine check interrupt can occur later if and when an attempt is made to write that block to main memory, for example as the result of executing an instruction that causes a cache miss for which the block is the target for replacement or as the result of executing dcbst or dcbf . 4.7.3 data storage interrupt a data storage interrupt (dsi) occurs when no higher priority exception exists and a data storage exception is presented to the interrupt mechanism. ta b l e 1 5 4 describes exception conditions for a data storage interrupt as defined by book e. mcsrr0 on a best-effort basis, the core complex se ts this to an effective address of some instruction that was executing or about to be executing when the machine check condition occurred. mcsrr1 msr[37?38,46?55,57?59,61?63] are loaded with equivalent msr bits. all other bits are reserved. mcar/ mcaru when a machine check interrupt is taken, the machine check address register is updated with the address of the data associated with th e machine check. note that if a machine check interrupt is caused by a signal, the mcar contents are not meaningful. see machine check address register (mcar/mcaru) on page 88 . mcaru is an alias to the upper 32 bits of mcar. mcsr set according to the machine check condition. see ta bl e 2 0 . 1. these registers are us ed if the machine check apu is not implemented. table 153. machine check interrupt settings (continued) register setting table 154. data storage interrupt exception conditions exception cause read access control exception occurs when either of the following conditions exists: in user mode (msr[pr] = 1), a load or load-class cache management instruction attempts to access a memory location that is not user-mode read enabled (page access control bit ur = 0). in supervisor mode (msr[pr] = 0), a load or load-class cache management instruction attempts to access a location that is not supervisor-mode read enabled (page access control bit sr = 0). write access control exception occurs when either of the following conditions exists: in user mode (msr[pr] = 1), a store or store-class cache management instruction attempts to access a location that is not user-mode write enabled (page access control bit uw = 0). in supervisor mode (msr[pr] = 0), a store or store-class cache management instruction attempts to access a location that is not supervisor-mode write enabled (page access control bit sw = 0). interrupts and exceptions RM0004 261/1176 instructions icbt , dcbt , dcbtst , and dcba , and lswx or stswx with a length of zero cannot cause a data storage interrupt, regardless of the effective address. note: icbi and icbt are treated as loads from the addressed byte with respect to address translation and protection. they use msr[ds], not msr[is], to determine translation for their operands. instruction storage interrupts and instruction tlb error interrupts are associated with instruction fetching and not execution. data storage interrupts and data tlb error interrupts are associated with the execution of instruction cache management instructions. when a data storage interrupt occurs, the processor suppresses execution of the instruction causing the data storage exception. srr0, srr1, esr, msr, and dear, are updated as follows: byte-ordering exception the implementation cannot access data in the byte order specified by the page?s endian attribute. note: note: the byte-ordering exception is provided to assist implementations that cannot support dynamically switching byte ordering between consecutive accesses, the byte order for a class of accesses, or misaligned accesses using a specific byte order. load/store accesses that cross a page boundary such that endianness changes cause a byte-ordering exception. cache locking exception (eis) the locked state of one or more cac he lines has the potential to be altered. this exception is implementation-dependen t. a cache locking exception occurs with the execution of icbtls , icblc , dcbtls , dcbtstls , or dcblc when (msr[pr] = 1) and (msr[ucle] = 0). esr is set as follows: for icbtls and icblc , esr[ilk] is set. for dcbtls , dcbtstls , or dcblc , esr[dlk] is set. book e refers to this as a cache-locking exception. storage synchronization exception occurs when either of the following conditions exists: an attempt is made to execute a load and reserve or store conditional instruction from or to a location that is write-through required or caching inhibited. (if the interrupt does not occur, the instruction executes correctly.) a store conditional instruction produces an effective address for which a normal store would cause a data storage interrupt but the processor does not have the reservation from a load and reserve instruction. book e states that it is implementation-dependent whether a data storage interrupt occurs. the eis defines that the data storage interrupt is taken. table 154. data storage interrupt exception conditions (continued) exception cause RM0004 interrupts and exceptions 262/1176 instruction execution resumes at address ivpr[32?47] || ivor2[48?59] || 0b0000. 4.7.4 instruction storage interrupt an instruction storage interrupt occurs when no higher priority exception exists and an instruction storage exception is presented to the interrupt mechanism. instruction storage exception conditions are described in ta bl e 1 5 6 . note that book e provides this exception to a ssist implementations that cannot dynamically switch byte ordering between consecutive accesses, do not support the byte order for a class of accesses, or do not support misa ligned accesses using a specific byte order. when an instruction storage interrupt occurs, the processor suppresses execution of the instruction causing the exception. srr0, srr1, msr, and esr are updated as shown in ta b l e 1 5 7 . table 155. data storage interrupt register settings register setting srr0 set to the effective address of t he instruction causing the interrupt srr1 set to the msr contents at the time of the interrupt esr fpset if the instruction causing the interrupt is a floating-point load or store; otherwise cleared stset if the instruction causing the interrupt is a store or store-class cache management instruction; otherwise cleared dlkdlk is set when a dsi occurs because dcbtls , dcbtstls , or dcblc is executed in user mode and msr[ucle] = 0. apset if the instruction causing the interrupt is an auxiliary processor load or store; otherwise cleared boset if the instruction ca used a byte-ordering exception; otherwise cleared all other defined esr bits are cleared. msr ce, me, and de are unchanged. all other msr bits are cleared. dear set to the effective address of a byte that lies both within the range of bytes being accessed by the access or cache management instruction and within the page whose access caused the exception table 156. instruction storage interrupt exception conditions exception cause execute access control exception in user mode, an instruction fetch attempts to access a memory location that is not user mode execute enabled (page access control bit ux = 0). in supervisor mode, an instruction fetch attempts to access a memory location that is not supervisor mode execut e enabled (page access control bit sx = 0). byte-ordering exception the implementation cannot fetch the instruct ion in the byte order specified by the page?s endian attribute. the eis defi nes that accesses that cross a page boundary such that endianness changes cause a byte-ordering exception. interrupts and exceptions RM0004 263/1176 note: permissions violation and byte-ordering exceptions are not mutually exclusive. even if esr[bo] is set, system software must examine the tlb entry accessed by the fetch to determine whether a permissions violation also may have occurred. instruction execution resumes at address ivpr[32?47] || ivor3[48?59] || 0b0000. 4.7.5 external input interrupt an external input interrupt occurs when no higher priority exception exists, an external input exception is presented to the interrupt mechanism, and msr[ee] = 1. the specific definition of an external input exception is implementation-dependent and is typically caused by assertion of an asynchronous signal t hat is part of the processing system. to guarantee that the core complex can take an external interrupt, the external interrupt pin must be asserted until the interrupt is taken. otherwise, whether the external interrupt is taken depends on whether msr[ee] is set when the external interrupt signal is asserted. in addition to msr[ee], implementations may provide other ways to mask this interrupt. srr0, srr1, and msr are updated as shown in ta b l e 1 5 8 . instruction execution resumes at address ivpr[32?47] || ivor4[48?59] || 0b0000. note: to avoid redundant external input interrupts, software must take any actions required to clear any external input exception status before reenabling msr[ee]. 4.7.6 alignment interrupt an alignment interrupt occurs when no higher priority exception exists and an alignment exception is presented to the interrupt mechanism. an alignment exception may occur when an implementation cannot perform a data access for one of the following reasons: the operand of a load or store is not aligned. the instruction is a move assist, load multiple, or store multiple. a dcbz operand is in write-through-required or caching-inhibited memory, or dcbz is executed in an implementation with no data cache or a write-through data cache. the operand of a store, except store conditional, is in write-through required memory. table 157. instruction storage interrupt register settings register setting srr0 set to the effective address of the instru ction causing the instruction storage interrupt srr1 set to the msr contents at the time of the interrupt msr ce, me, and de are unchanged. all other msr bits are cleared. esr bo is set if the instruction fetch caused a byte-ordering exception; otherwise cleared. all other defined esr bits are cleared. table 158. external input interrupt register settings register setting srr0 set to the effective address of the next instruction to be executed srr1 set to the msr contents at the time of the interrupt msr ce, me, and de are unchanged. all other msr bits are cleared. RM0004 interrupts and exceptions 264/1176 the eis defines the following alignment exception conditions: execution of a dcbz references a page marked as write-through or cache inhibited. a load multiple word instruction ( lmw ) reads an address that is not a multiple of four. a lwarx or stwcx . instruction references an address that is not a multiple of four. spfp and spe apu instructions are not alig ned on a natural boundary. a natural boundary is defined by the size of the data element being accessed. a vector operation reports an exception if the physical address of the following instructions is not aligned to the 64-bit boundary: evldd , evlddx , evldw , evldwx , evldh , evldhx , evstdd , evstddx , evstdw , evstdwx , evstdh , and evstdhx . ta b l e 1 5 9 describes additional esr settings. for lmw and stmw with a non?word-aligned operand and for load and reserve and store conditional instructions with an misaligned operand, an implementation may yield boundedly undefined results instead of causing an alignment interrupt. a store conditional to a write- through required location may either cause an alignment or data storage interrupt or may correctly execute the instruction. for all other cases listed above, an implementation may execute the instruction correctly instead of causing an alignment interrupt. for dcbz , correct execution means clearing each byte of the block in main memory. note: book e does not support use of an misaligned effective address by load and reserve and store conditional instructions. if an misaligned effective address is specified, the alignment interrupt handler should treat the instruction as a programming error and must not attempt to emulate the instruction. when an alignment interrupt occurs, the processor suppresses the execution of the instruction causing the alignment exception. srr0, srr1, msr, dear, and esr are updated as shown in ta bl e 1 5 9 . instruction execution resumes at address ivpr[32?47] || ivor5[48?59] || 0b0000. table 159. alignment interrupt register settings register setting srr0 set to the effective address of the instruction causing the alignment interrupt srr1 set to the msr contents at the time of the interrupt msr ce, me, and de are unchanged. all other msr bits are cleared. dear set to the ea of a byte that is both within the range of the bytes being accessed by the memory access or cache management instruction, and within the page whose access caused the alignment exception esr fp set if the instruction causing the interrupt is a floating-point load or store; otherwise cleared st set if the instruction causing the in terrupt is a store; otherwise cleared ap set if the instruction causing the interrup t is an auxiliary processor load or store; otherwise cleared the following bits may be affected for ve ctor alignment exception conditions: spe set ap set (may not be supported on all processors) st set only if the instruction causing the e xception is a store and is cleared for a load all other defined esr bits are cleared. interrupts and exceptions RM0004 265/1176 4.7.7 program interrupt a program interrupt occurs when no higher priority exception exists and a program exception is presented to the interrupt mechanism. a program interrupt is caused when any of the following exceptions occurs during execution of an instruction. table 160. program interrupt exception conditions exception cause floating-point enabled exception caused when (msr[fe0] | msr[fe1]) & fpscr[fex] = 1. fpscr[fex] is set by the execution of a floating-point instru ction that causes an enabled exception, including the case of a move to fpscr instruction that causes an exception bit and the corresponding enable bit both to be 1. note that in this context, the term ?enabled exception? refers to the enabling provided by fpscr control bits. see chapter 2.4.2: floating-point status an d control register (fpscr) on page 58 .? whether the interrupt is precise or im precise is determined by msr[fe0,fe1], as described in ta bl e 2 0 . auxiliary processor enabled exception implementation dependent illegal instruction exception always occurs when execution of any of the following kinds of instructions is attempted. ? a reserved-illegal instruction ? in user mode, an mtspr or mfspr that specifies an sprn value with sprn[5] = 0 (user-mode accessible) that represents an unimplemented spr ? (eis) if an invalid spr address is accessible only in supervisor mode and the processor is in supervisor mode (msr[pr] = 0), results are undefined. ? (eis) if the invalid spr address is ac cessible only in the supervisor mode and the processor is in user mode (msr[pr] = 1), a privileged instruction exception is taken. may occur when execution is attempted of any of the following kinds of instructions. if the exception does not occur, the alternative is shown in parentheses. see the user?s ma nual for the implementation. ? an instruction that is in invalid form (boundedly undefined results). ?an lswx instruction for which r a or r b is in the range of registers to be loaded (boundedly undefined results) ? a reserved no-op instruction (no-operation performed is preferred). ? a defined or allocated instruction that is not implemented (unimplemented operation exception). unimplemented bo ok e instructions take an illegal instruction exception. ? the eis defines that an attempt to exec ute a 64-bit book e instruction causes an illegal instruction exception. privileged instruction exception occurs when msr[pr] = 1 and execution is attempted of any of the following: ? a privileged instruction ?an mtspr or mfspr instruction that specifies a privileged spr (sprn[5] = 1) ? (eis) an mtpmr or mfpmr instruction that specifies a privileged pmr (pmrn[5] = 1) trap exception occurs when any of the conditi ons specified in a trap instruction are met. unimplemented operation exception may occur when a defined or allocated instruction is encountered that is not implemented. otherwise an illegal instruction exception occurs. see the reference manual for the implementation. RM0004 interrupts and exceptions 266/1176 whether a floating-point enabled interrupt is precise or imprecise is determined by msr[fe0,fe1], as described in ta b l e 1 6 1 . srr0, srr1, msr, and esr are updated as shown in ta b l e 1 6 2 . instruction execution resumes at address ivpr[32?47] || ivor6[48?59] || 0b0000. table 161. msr[fe0,fe1] settings fe0,fe1 description 01,10 imprecise. when such a program interrupt is taken, if the address saved in srr0 is not that of the instruction that caused the exception (that is, the instruction that caused fpscr[fex] to be set), esr[pie] is set. note that some implementations may ignore these bit settings and treat all af fected interrupts as precise. 11 precise. 00 the interrupt is masked and the interrupt su bsequently occurs if and when floating-point enabled exception-type program interrupts are enabled by setting either or both fe0,fe1 and also causes esr[pie] to be set. table 162. program interrupt register settings register description srr0 for all program interrupts except an enab led exception when in an imprecise mode (see table 164 ), set to the ea of the instruct ion that caused the interrupt. for an imprecise enabled exception, set to the ea of the excepting instruction or of some subsequent instruction that has not been execut ed (in which case esr[pie] is set). if the instruction is msync or isync , srr0 does not point more than 4 bytes beyond the msync or isync . if fpscr[fex] = 1 but both msr[fe0,fe1] = 00, an enabled exception-type program interrupt occurs before or at the next synch ronizing event if [fe0,fe1] are altered by any instruction so that the expres sion (msr[fe0] | msr[fe1]) & fp scr[fex] is 1. when this occurs, esr[pie] is set and srr0 is loaded with the ea of the instruction that would have executed next, not with the ea of the instruct ion that modified msr causing the interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. esr pil set if an illegal instruction exception- type program interrupt; otherwise cleared. ppr set if a privileged instruction exception- type program interrupt; otherwise cleared. ptr set if a trap exception-type program interrupt; otherwise cleared. puo set if an unimplemented operation exc eption-type program interrupt; otherwise cleared. fp set if the instruction causing the interrupt is a floating-point instruction; otherwise cleared. pie set if a floating-point enabled exception-type program interrupt, and the address saved in srr0 is not the address of the instruction causing the exception (that is, the instruction that caused fpscr[fex] to be set); otherwise cleared. ap set if the instruction causing the interrupt is an auxiliary processor instruction; otherwise cleared. all other defined esr bits are cleared. interrupts and exceptions RM0004 267/1176 4.7.8 floating-point unavailable interrupt a floating-point unavailable interrupt occurs when no higher priority exception exists, an attempt is made to execute a floating-point instruction (including floating-point loads, stores, and moves), and msr[fp] = 0. when a floating-point unavailable interrupt occurs, the processor suppresses execution of the instruction causing the floating-point unavailable interrupt. srr0, srr1, and msr are updated as shown in ta b l e 1 6 3 . instruction execution resumes at address ivpr[32?47]||ivor7[48?59]||0b0000. 4.7.9 system call interrupt a system call interrupt occurs when no higher priority exception exists and a system call ( sc ) instruction is executed. srr0, srr1 , and msr are updated as shown in ta b l e 1 6 4 . instruction execution resumes at address ivpr[32?47] || ivor8[48?59] || 0b0000. 4.7.10 auxiliary processor unavailable interrupt an auxiliary processor unavailable interrupt occurs when no higher prio rity exception exists, an attempt is made to execute an auxiliary processor instructi on (including auxiliary processor loads, stores, and moves), the targ et auxiliary processor is present on the implementation, and the auxiliary processor is configured as unavailable. details of the auxiliary processor and its configuration ar e implementation-depende nt. see the reference manual for the implementation. when an auxiliary processo r unavailable interrupt occu rs, the processor suppresses execution of the instructio n causing the auxilia ry processor unavailable interrupt. registers srr0, srr1, and msr are updated as shown in table 165 . table 163. floating-point unavailable interrupt register settings register description srr0 set to the effective address of the instruction that caused the interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. table 164. system call interrupt register settings register description srr0 set to the effective address of the instruction after the sc instruction. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. RM0004 interrupts and exceptions 268/1176 instruction execution resumes at address ivpr[32?47]||ivor9[48?59]||0b0000. 4.7.11 decrementer interrupt a decrementer interrupt occurs when no higher priority exception exists, a decrementer exception exists (tsr[dis] = 1) & the interrupt is enabled (tcr[die] = 1 and msr[ee] = 1). msr[ee] also enables external input and fixed-interval timer interrupts. srr0, srr1, msr, and tsr are updated as shown in table 166 . instruction execution resumes at address ivpr[32?47] || ivor10[48?59] || 0b0000. note: to avoid redundant decrementer interrupts, before reenabling msr[ee], the interrupt handling routine must clear tsr[dis] by writing a word to tsr using mtspr with a 1 in any bit position to be cleared and 0 in all others. the data written to the tsr is not direct data, but a mask. writing a 1 to this bit causes it to be cleared; writing a 0 has no effect. 4.7.12 fixed-interv al timer interrupt a fixed-interval timer interrupt occurs when no higher priority exception exists, a fixed- interval timer exception exists (tsr[fis] = 1), and the interrupt is enabled (tcr[fie] = 1 and msr[ee] = 1). the fixed-interval timer period is determined by tcr[fp], which, when concatenated with tcr[fpext], specifies one of 64 bit locations of the time base used to signal a fixed- interval timer exception on a transition from 0 to 1. tcr[fpext],tcr[fp] = 000000 selects tbu[ 32]. tcr[fpext],tcr[fp] = 111111 selects tbl[63]. note: msr[ee] also enables external input and decrementer interrupts. srr0, srr1, msr, and tsr are updated as shown in table 167 . table 165. auxiliary processor unavailable interrupt register settings register setting srr0 set to the effective address of the instruction that caused the interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. table 166. decrementer interrupt register settings register setting srr0 set to the effective address of the next instruction to be executed. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. tsr dis is set. interrupts and exceptions RM0004 269/1176 instruction execution resumes at address ivpr[32?47] || ivor11[48?59] || 0b0000. note: to avoid redundant fixed-interval timer interrupts, before reenabling msr[ee], the interrupt handling routine must clear tsr[fis] by writing a word to tsr using mtspr with a 1 in any bit position to be cleared and 0 in all others. the data written to the tsr is not direct data, but a mask. writing a 1 causes the bit to be cleared; writing a 0 has no effect. 4.7.13 watchdog timer interrupt a watchdog timer interrupt occurs when no higher priority exception exists, a watchdog timer exception exists (tsr[wis] = 1), and the interrupt is enabled (tcr[wie] = 1 and msr[ce] = 1). msr[ce] also enables the critical input interrupt. csrr0, csrr1, msr, and tsr are updated as shown in ta bl e 1 6 8 . instruction execution resumes at address ivpr[32?47] || ivor12[48?59] || 0b0000. note: to avoid redundant watchdog timer interrupts, before reenabling msr[ce], the interrupt handling routine must clear tsr[wis] by writing a word to tsr using mtspr with a 1 in any bit position to be cleared and 0 in all others. the data written to the tsr is not direct data, but a mask. writing a 1 to this bit causes it to be cleared; writing a 0 has no effect. 4.7.14 data tlb error interrupt a data tlb error interrupt occurs when no higher priority exception exists and the exception described in ta b l e 1 6 9 is presented to the interrupt mechanism. table 167. fixed-interval timer interrupt register settings register setting srr0 set to the effective address of the next instruction to be executed. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. tsr fis is set. table 168. watchdog timer interrupt register settings register setting csrr0 set to the effective address of the next instruction to be executed. csrr1 set to the msr contents at the time of the interrupt. msr me is unchanged; all other msr bits are cleared. tsr wis is set. table 169. data tlb error interrupt exception conditions exception description data tlb miss exception virtual addresses associated with an instruction fetch do not match any valid tlb entry. RM0004 interrupts and exceptions 270/1176 if a store conditional instruction produces an effective address for which a normal store would cause a data tlb error interrupt, but the processor does not have the reservation from a load and reserve instruction, book e defines it as implementation-dependent whether a data tlb error interrupt occurs. the eis defines that the interrupt is taken. when a data tlb error interrupt occurs, the processor suppresses execution of the instruction causing the data tlb error exception. srr0, srr1, msr, dear, and esr are updated as shown in ta bl e 1 7 0 . table 192 shows mas register settings for data and instruction tlb error interrupts. mas register updates for exceptions, tlbsx, and tlbre on page 328 ,? describes how these values are set as defined by the eis. instruction execution resumes at address ivpr[32?47] || ivor13[48?59] || 0b0000. 4.7.15 instruction tlb error interrupt an instruction tlb error interrupt occurs when no higher priority exception exists and the exception described in ta b l e 1 7 1 is presented to the interrupt mechanism. when an instruction tlb error interrupt occurs, the processor suppresses execution of the instruction causing the instruction tlb miss exception. srr0, srr1, and msr are updated as shown in ta b l e 1 7 2 . table 170. data tlb error interrupt register settings register setting srr0 set to the effective address of the inst ruction causing the data tlb error interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. dear set to the ea of a byte that is both within the range of the bytes being accessed by the memory access or cache management inst ruction and within the page whose access caused the data tlb error exception. esr stset if the instruction causing the interrupt is a store, dcbi , or dcbz instruction; otherwise cleared. fpset if the instruction causing the interrupt is a floating-point load or store; otherwise cleared. apset if the instruction causi ng the interrupt is an auxili ary processor load or store; otherwise cleared. all other defined esr bits are cleared. mas n see ta b l e 1 9 3 . table 171. instruction tlb error interrupt exception conditions exception description instruction tlb miss exception the virtual addresses associated with a fetch do not match any valid tlb entry. interrupts and exceptions RM0004 271/1176 instruction execution resumes at address ivpr[32?47] || ivor14[48?59] || 0b0000. 4.7.16 debug interrupt a debug interrupt occurs when no higher priority interrupt exists, a debug exception exists in the dbsr, and debug interrupts are enabled (dbcr0[idm] = 1 and msr[de] = 1). a debug exception occurs when a debug event causes a corresponding dbsr bit to be set. csrr0, csrr1, msr, and dbsr are updated as shown in table 173 . instruction execution resumes at address ivpr[32?47] || ivor15[48?59] || 0b0000. 4.7.17 eis-defined interrupts the interrupts in this section are defined by the eis. table 172. instruction tlb error interrupt register settings register setting srr0 set to the effective address of the instruct ion causing the instruction tlb error interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. mas n see ta bl e 1 9 2 . table 173. debug interrupt register settings register setting csrr0 for debug exceptions that occur while de bug interrupts are enabled (dbcr0[idm] = 1 and msr[de] = 1), csrr0 is set as follows: ? for instruction address compare (iac r egisters), data address compare (dac1r, dac1w, dac2r, and dac2w), data value compare (dvc1 and dvc2), trap (trap), or branch taken (brt) debug exceptions, set to the address of the instruction causing the debug interrupt. ? for instruction complete (icmp) debug exc eptions, set to the address of the instruction that would have executed after the one that caused the debug interrupt. ? for unconditional debug event (ude) debug exceptions, set to the address of the instruction that would have executed ne xt if the debug interrupt had not occurred. ? for interrupt taken (irpt) debug exceptions, set to the interrupt vector value of the interrupt that caused the interrupt taken debug event. ? for return from interrupt (ret) debug exceptions, set to the address of the instruction that would have executed after the rfi , rfci , or rfmci that caused the debug interrupt. ? for debug exceptions that occur while de bug interrupts are disabled (dbcr0[idm] = 0 or msr[de] = 0), a debug interrupt occurs at the next synchronizing event if dbcr0[idm] and msr[de] are modified such that they are both set and if the debug exception status is still set in the dbsr. w hen this occurs, csrr0 holds the address of the instruction that would have executed ne xt, not the address of the instruction that modified dbcr0 or msr and thus caused the interrupt. csrr1 set to the msr contents at the time of the interrupt. msr me is unchanged. all other msr bits are cleared. dbsr set to indicate type of debug event. (see chapter 2.13.2: debug status register (dbsr) on page 116 . ) RM0004 interrupts and exceptions 272/1176 spe/embedded floating-point apu unavailable interrupt an spe apu unavailable interrupt is taken if msr[spe] is cleare d and an spe, embedded scalar double-precision or embedded vector single-precision floating-point instruction is executed. it is not used by the embedded scalar single-precision floating-point apu. when an spe unavailable interrupt occurs, t he processor suppresse s execution of the instruction causing the interrupt. ta b l e 1 7 4 describes register settings. if the spe/embedded floating-point un available interrupt occurs, the processor suppresses execution of the instruction causing the exception. the srr0, srr1, msr, and esr registers are modified as shown in ta b l e 1 7 4 . instruction execution resumes at address ivpr?47] || ivor32[48?59] || 0b0000. embedded floating-point data interrupt an embedded floating-point data interrupt is generated in the following cases: spefscr[finve] = 1 and either spefscr[finvh,finv] = 1 spefscr[fdbze] = 1and either spefscr[fdbzh,fdbz] = 1 spefscr[funfe] = 1 and either spefscr[funfh,funf] = 1 spefscr[fovfe] = 1 and either spefscr[fovfh,fovf] = 1 note that although spefscr status bits can be updated by using mtspr , interrupts occur only if they are set as the result of an arithmetic operation. when an embedded floating-point data interrupt occurs, the processor suppresses execution of the instruction causing the interrupt. ta bl e 1 7 5 shows register settings. instruction execution resumes at address ivpr[32?47] || ivor33[48?59] || 0b0000. table 174. spe/embedded floati ng-point apu unavailable in terrupt regist er settings register setting srr0 set to the effective address of the instruction caus ing the interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged . all other bits are cleared. esr spe (bit 24) is set. all other esr bits are cleared. table 175. embedded floating-point data interrupt register settings register setting srr0 set to the effective address of the instruction causing the interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other bits are cleared. esr spe (bit 24) is set. all other esr bits are cleared. spefscr one or more of the finvh, finv, fdbzh, fdbz, funfh, funf, fo vfh, or fovf bits are set to indicate the interrupt type. interrupts and exceptions RM0004 273/1176 embedded floating-point round interrupt the embedded floating-point round interrupt is taken on any of the following conditions: spefscr[finxe] = 1 and any of the spefscr[fgh,fxh,fg,fx] bits = 1 spefscr[frmc] = 0b10 (+ ) spefscr[frmc] = 0b11 (? ) note that although thes e spefscr status bits can be updated by using an mtspr [spefscr], interrupts occur only if they are set as the result of an arithmetic operation. when an embedded floating-point round interrupt occurs, the unrounded (truncated) result is placed in the target register. ta bl e 1 7 6 describes register settings. instruction execution resumes at address ivpr[32?47] || ivor34[48?59] || 0b0000. 4.8 performance monitor interrupt the performance monitor provides a performance monitor interrupt that is triggered by an enabled condition or event. an enabled condition or event is as follows: a pmc x register overflow condition occurs with the following settings: pmlca x [ce] = 1; that is, for the given counter the overflow condition is enabled. pmc x [32] = 1; that is, the given counter indicates an overflow. for a performance monitor interrupt to be signaled on an enabled condition or event, pmgc0[pmie] must be set. the performance monitor can also freeze the performance monitor counters triggered by an enabled condition or event. for the performance monitor counters to freeze on an enabled condition or event, pmgc0[fcece] must be set. although the interrupt condition could occur with msr[ee] = 0, the interrupt cannot be taken until msr[ee] = 1. if a counter overflows while pmgc0[fcece] = 0, pmlca[ce] = 1, and msr[ee] = 0, it is possible for the counter to wrap around to all zeros again without the performance monitor interrupt being taken. the priority of the performance monitor interrupt is below that of the fixed-interval interrupt and above that of the decrementer interrupt. table 176. embedded floating-point round interrupt register settings register setting srr0 set to the effective address of the inst ruction following the instruction causing the interrupt. srr1 set to the msr contents at the time of the interrupt. msr ce, me, and de are unchanged. all other msr bits are cleared. esr spe (bit 24) is set. all other esr bits are cleared. spefscr fgh, fxh, fg, fx, and frmc are set appropriately to indicate the interrupt type. RM0004 interrupts and exceptions 274/1176 4.9 partially executed instructions in general, the powerpc architecture permits load and store instructions to be partially executed, interrupted, and then restarted from the beginning upon return from the interrupt. to guarantee that a particular load or store instruction completes without being interrupted and restarted, software must mark the memory as guarded and use an elementary (non- string or non-multiple) load or store aligned on an operand-sized boundary. to guarantee that load and store instructions can, in general, be restarted and completed correctly without software intervention, the following rules apply when an execution is partially executed and then interrupted: for an elementary load, no part of a target register r d or fr d has been altered. for update forms of load or store, the update register, r a, will not have been altered. the following effects are permissible when certain instructions are partially executed and then restarted: for any store, bytes at the target location may have been altered (if write access to that page in which bytes were altered is permitted by the access control mechanism). in addition, for store conditional instructions, cr0 has been set to an undefined value, and it is undefined whether the reservation has been cleared or not. for any load, bytes at the addressed location may have been accessed (if read access to that page in which bytes were acce ssed is permitted by the access control mechanism). for load multiple or load string, some registers in the range to be loaded may have been altered. including the addressing registers r a and possibly r b in the range to be loaded is a programming error, and thus the rules for partial execution do not protect these registers against overwriting. in no case is access control violated. as previously stated, elementary, aligned, guarded loads and stores are the only access instructions guaranteed not to be interrupted after being partially executed. the following list identifies the specific instruct ion types for which interruption after partial execution may occur, as well as the specific interrupt types that could cause the interruption: 1. any load or store (except elementary, aligned, or guarded): ? any asynchronous interrupt ? machine check ? program (imprecise mode floating-point enabled) ? program (imprecise mode auxiliary processor enabled) ? decrementer ? fixed-interval timer ? watchdog timer ? debug (unconditional debug event) 2. misaligned elementary load or store, or any multiple or string: all of the above listed under item 1, plus the following: ? alignment ? data storage (if the access crosses a protection boundary) ? debug (data address compare, data value compare) interrupts and exceptions RM0004 275/1176 the mtcrf and mfcr instructions can also be partially executed due to the occurrence of any of the interrupts listed under item 1 at the time mtcrf or mfcr was executing. all instructions before mtcrf or mfcr have completed execution. some memory accesses generated by these preceding instructions may not have completed. no subsequent instruction has begun execution. the mtcrf or mfcr instruction, whose address was saved in srr0/csrr0 at the time of the interrupt, may appear not to have begun or may have partially executed. 4.10 interrupt ordering and masking multiple exceptions that can each generate an interrupt can exist simultaneously. however, the powerpc architecture does not provide for reporting multiple simultaneous interrupts of the same class (critical or noncritical). therefore, the powerpc architecture defines that interrupts must be ordered with one another and provides a way to mask certain persistent interrupt types. when an interrupt type is mask ed (disabled) and an event causes an exception that would normally generate an interrupt of that type, the exception persists as a status bit in a register (which register depends upon the exception type) but no interrupt is generated. later, if the interrupt type is enabled (unmasked) and the exception status has not been cleared by software, the interrupt due to the original exception event is finally generated. (a typical implementation has such a mechanism for certain debug events. a signal that triggers an asynchronous interrupt, such as external input, must be asserted until they are taken. there is no mechanism for saving the external interrupt if the signal is negated before the interrupt is taken. all interrupts are level-sensitiv e except for machine check, which is edge- triggered.) all asynchronous interrupt types and some synchronous interrupt types can be masked. an example of a maskable synchronous interrupt type is the floating-point enabled exception- type program interrupt. the execution of a floating-point instruction that causes fpscr[fex] to be set is considered an exception event, regardless of the setting of msr[fe0,fe1]. if msr[fe0,fe1] are both 0, the floating-point enabled exception-type program interrupt is masked, but the exception persists in fpscr[fex]. later, if msr[fe0,fe1] are enabled, the interrupt is generated. the powerpc architecture allows implementation s to avoid situations in which an interrupt would cause state information (saved in save/restore registers) from a previous interrupt to be overwritten and lost. as a first step, upon any noncritical class interrupt, hardware automatically disables further asynchronous, noncritical class interrupts (external input) by clearing msr[ee]. likewise, upon any critical class interrupt, hardware automatically disables further asynchronous interrupts, both critical and noncritical, by clearing msr[ce] and msr[ee]. critical input, watchdog timer, and debug interrupts are disabled by clearing msr[ce,de]. note that machine check interrupt s, while considered neither asynchronous nor synchronous, are not maskable by msr[ce,de,ee] and could be presented in a situation that could cause loss of state information. this first step of clearing msr[ee] (and msr[ce ,de] for critical class interrupts) prevents subsequent asynchronous interrupts from overwriting save/restore registers before software can save their contents. on any interrupt, hardware also automatically clears msr[we,pr,fp,fe0,fe1,is,ds], which helps avoid subsequent interrupts of certain other types. however, guaranteeing that these interrupt types do not occur also requires system software to avoid executing instructions that could cause (or enable) a subsequent interrupt, if srr1 contents have not been saved. RM0004 interrupts and exceptions 276/1176 4.10.1 guidelines fo r system software table 177 lists actions system software must avoid before saving save/restore register contents. if the machine check apu is not implemented, machine check interrupts are a special case. machine checks are critical interrupts, but norm al critical interrupts (c ritical input, watchdog timer, and debug) do not automatically disable machine checks. machine checks are disabled by clearing msr[me], and only a machine check interrupt itself automatically clears this bit. thus there is always the ri sk that a machine check interrupt could occur table 177. operations to avoid operation reason reenabling msr[ee] (or msr[ce,de] in critical class interrupt handlers) prevents any asynchronous interrupts, snd (in the case of msr[de]) any debug interrupts, including synchronous and asynchronous types branching (or sequential execution) to addresses not mapped by the tlb, mapped without ux = 1 or sx = 1 permission, or causing large address or instruction address overflow exceptions. prevents instruction st orage, instruction tlb error, and instruction address overflow interrupts load, store, or cache management instructions to addresses not mapped by the tlb or not having required access permissions. prevents data storage and data tlb error interrupts execution of system call ( sc ) or trap ( tw , twi , td , tdi ) prevents system call and trap exception-type program interrupts execution of any floating-point instruction prevents floating-point unavailable interrupts. note that this interrupt would occur upon execution of any floating-point instruction, due to the automatic clearing of msr[fp]. however, even if software were to reenable msr[fp], floating-point instructions must still be avoided to prevent program interrupts due to various possible program interrupt exceptions (floating-point enabled, unimplemented operation). reenabling of msr[pr] prevents priv ileged instruction exception-type program interrupts. alternatively, software could reenable msr[pr] but avoid executing any privileged instructions. execution of any auxiliary processor instruction prevents auxiliary processor unavailable, auxiliary processor enabled type, and unimplemented operation type program interrupts execution of any illegal instructions pr events illegal instruction exception-type program interrupts execution of any instruction that could cause an alignment interrupt prevents alignment interrupts, including string or multiple instructions and misaligned elementary load or store instructions. chapter 4.7.6: alignment interrupt ,? lists instructions that cause alignment interrupts. interrupts and exceptions RM0004 277/1176 within a normal critical interrupt handler before it saves the save/restore registers? contents. in such a case, the interr upt may not be recoverable. it is unnecessary for hardware or software to avoid critical-class interrupts from within noncritical-class interrupt handlers (hence hardware does not automatically clear msr[ce,me,de] on a noncritical interrupt), since the two interrupt classes use different save/restore registers. however, because a critical class interrupt can occur within a noncritical handler before the noncritical handler saves srr0/srr1, hardware and software must cooperate to avoid both critical and noncritical class interrupts from within critical class interrupt handlers. therefore, within the critical class interrupt handler, both pairs of save/restore registers may contain data necessary to system software. 4.10.2 interrupt order enabled interrupt types for which simultaneous exceptions can exist are prioritized as follows: 1. synchronous (non-debug) interrupts: ? data storage ? instruction storage ? alignment ?program ? floating-point unit unavailable ? auxiliary processor unavailable ? system call ? data tlb error ? instruction tlb error only one of the above synchronous interrupt types may have an existing exception generating it at a given time. this is guaranteed by the exception priority mechanism (see chapter 4.11: exception priorities ? ) and the sequential execution model. 2. machine check 3. debug 4. critical input 5. watchdog timer 6. external input 7. fixed-interval timer 8. decrementer although, as indicated above, noncritical, synchronous exception types listed under item 1 are generated with higher priority than critical interrupt types in items 2?5, noncritical interrupts are immediately followed by the highest priority existing critical interrupt type, without executing any instructions at the noncritical interrupt handler. this is because noncritical interrupt types do not automatically disable msr mask bits for critical interrupt types (ce and me). in all other cases, a particular interrupt type listed above automatically disables subsequent interrupts of the same type, as well as all lower priority interrupt types. RM0004 interrupts and exceptions 278/1176 4.11 exception priorities book e requires all synchronous (precise and imprecise) exceptions to be reported in program order, as required by the sequential execution model. the one exception to this rule is the case of multiple synchronous imprecise exceptions. upon a synchronizing event, all previously executed instructions are required to report any synchronous imprecise interrupt- generating exceptions, and the interrupt is then generated with all of those exception types reported cumulatively in the esr and in any status registers associated with the particular exception type (such as the fpscr). for any single instruction attempting to cause multiple exceptions for which the corresponding synchronous interrupt types are enabled, this section defines the priority order by which the instruction is permitted to cause a single enabled exception, thus generating a particular synchronous interrupt. note that it is this exception priority mechanism, along with the requirement that synchronous interrupts be generated in program order, that guarantees that at any given time there exists for consideration only one of the synchronous interrupt types listed in item 1 of chapter 4.10.2: interrupt order .? the exception priority mechanism also prevents certain debug exceptions from existing in combination with certain other synchronous interrupt-generating exceptions. the eis defines priorities for all exceptions including those defined in optional apus. interrupt types are defined as either synchronous (the interrupt is as a direct result of an instruction in execution) or asynchronous, (the interrupt results from an event external to the execution of a particular instruction or an instruction removes a gating condition to a pending exception). except for machine check interrupts, which can be either synchronous or asynchronous, interrupts are either synchronous or asynchronous exclusively. because asynchronous interrupts may temporally be sampled either before or after an instruction is completed, an implementation can order asynchronous interrupts among only asynchronous interrupts and order synchr onous interrupts among only synchronous interrupt. the distinction is important because synchronous interrupts that require post- completion actions (such as system call or debug instruction complete exceptions) cannot be separated from the completion of the instruction. therefore, asynchronous interrupts cannot be sampled during the completion and post-completion synchronous exceptions for a given instruction. the relative priorities for asynchronous exceptions is given in ta bl e 1 7 8 and for synchronous exceptions in and ta b l e 1 7 9 . in many cases, certain exceptions cannot occur at the same time (for example, program-trap and program-illegal cannot occur on the same instruction). in general those exceptions are grouped at the same relative priority. interrupts and exceptions RM0004 279/1176 table 178. eis asynchronous exception priorities relative priority exception interrupt level (1) 1. the interrupt level defines the set of save/restore registers used when the interrupt is taken?base (srr0/srr1), critical (csrr0/csrr1), debug (dsrr0/dsrr1), and machine check (mcsrr0/mcsrr1). interrupt nature pre/post completion (2) 2. pre- or post-completion refers to whether the exception occurs before an instruction completes (pre) and the corresponding interrupt points to the instruction c ausing the exception, or if the instruction completes (post) and the corresponding interrupt point s to the next instruction to be executed. comments 0 machine check machine check asynch/synch pre for synch asynchronous exceptions may come from processor or from an external source. 1 debug?ude critical/debug asynch n/a generally used for an externally generated high priority attention signal. debug?ide critical/debug asynch n/a usually taken after msr[de] goes from 0 to 1 via rfdi / rfci or mtmsr . debug?interrupt taken critical/debug asynch n/a debug interrupt taken after original interrupt changed nia and msr. debug?critical interrupt taken debug asynch n/a debug interrupt taken after original critical interrupt has changed nia and msr. 2 critical input critical asynch n/a 3 watchdog critical asynch n/a 4 external input base asynch n/a 18 fixed interval timer base asynch n/a 19 decrementer base asynch n/a 20 performance monitor base asynch n/a RM0004 interrupts and exceptions 280/1176 table 179. eis synchronous exception priorities relative priority exception interrupt level (1) interrupt nature pre/post completion (2) comments 5 debug?instruction address compare critical/debug synch pre 6 itlb base synch pre isi base synch pre 7 fp unavailable base synch pre altivec unavailable base synch pre defined by the altivec apu. spe unavailable base synch pre defined by the spe apu. embedded floating- point unavailable base synch pre defined by the embedded floating point apus. 8 debug?trap critical/debug synch pre 9 program?illegal instruction base synch pre program? unimplemented operation base synch pre program?privileged instruction base synch pre program?trap base synch pre program?fp enabled base synch pre an fp enabled interrupt may be imprecise. 10 (alignment) base synch pre alignment may be handled at either priority. 11 dtlb base synch pre data storage base synch pre 12 alignment base synch pre alignment may be handled at either priority. interrupts and exceptions RM0004 281/1176 13 system call base synch post points srr0 to instruction after sc (post completion). embedded fp data base synch pre defined by the spe apu. embedded fp round base synch post points srr0 to the instruction after the one causing the exception (post completion). defined by spe apu. altivec assist base synch pre defined by the altivec apu. 14 debug?return from interrupt critical/debug synch pre debug?return from critical interrupt debug synch pre defined by the enhanced debug apu. debug?branch taken critical/debug synch pre 15 debug?dac critical/debug synch pre or post preferred method is pre- completion. 16 debug?dvc critical/debug synch pre or post preferred method is pre- completion. 17 debug?instruction complete critical/debug synch post points [cd]srr0 to next instruction (post completion). 1. the interrupt level defines the set of save/restore registers used when the interrupt is taken?base (srr0/srr1), critical (csrr0/csrr1), debug (dsrr0/dsrr1), and machine check (mcsrr0/mcsrr1). 2. pre- or post-completion refers to whether the exception occurs before an instruction completes (pre) and the corresponding interrupt points to the instruction c ausing the exception, or if the instruction completes (post) and the corresponding interrupt point s to the next instruction to be executed. table 179. eis synchronous exception priorities (continued) relative priority exception interrupt level (1) interrupt nature pre/post completion (2) comments RM0004 storage architecture 282/1176 5 storage architecture this chapter describes the cache and mmu portions of the book e implementation standards (eis). note that not all features that are defined by the eis storage architecture are supported on all st eis processors; consult the user documentation. this chapter is organized into three section: chapter 5.2: memory and cache coherency ? chapter 5.3: cache model ? chapter 5.4: storage model ? 5.1 overview the book e architecture memory and cache definitions support a wide variety of embedded implementations. to provide such flexibility, book e defines many features in a very general way, leaving specific details up to the implementation. to ensure consistency among its book e cores and devices, st has defined more specific implementation standards. however, these standards still leave many detai ls up to individual implementations. to provide context for those features, this chapter describes aspects of the memory hierarchy and the memory management model defined by book e; it also describes the st eis. note: this chapter describes some features (in particular, registers) in a very general way that does not include some details that are important to the programmer. there are also small differences in how some features are defined here and how they are implemented. for implementation-specific details, see the user documentation. throughout this chapter, references to load instructions include cache management and other instructions that are stated in the instruction descriptions to be treated as a load, and references to store instructions include the cache management and other instructions that are treated as a store. the following apus, which are part of the eis storage architecture, are defined in chapter 8: storage-related apus on page 848 ? : cache line locking apu cache way partitioning apu direct cache flush apu these apus may be implemented independently of each other. they are defined together in a single specification because it is likely that an implem entation will include more than one of these apus. 5.2 memory and cache coherency the primary objective of a coherent memory system is to provide the same image of memory to all devices using the system. coherency allows synchronization and cooperative use of shared resources. otherwise, multiple copies of data corresponding to a memory location, some containing outdated values, could exist in a system, resulting in errors when the outdated values are used. each memory-sharing device must follow rules for managing the state of its cache. this section describes the coherency mechanisms of the book e architecture and the cache coherency protocols that the st book e devices support. storage architecture RM0004 283/1176 unless specifically noted, the discussion of c oherency in this section applies to the core complex data cache only. the instruction cache is not snooped for general coherency with other caches; however, it is snooped when the instruction cache block invalidate ( icbi ) instruction is executed by this processor or any processor in the system. 5.2.1 memory/cache access attributes some memory characteristics can be set on a page basis by using the wimge bits in the translation lookaside buffer (tlb) entries. these bits allow both uniprocessor and multiprocessor system designs to expl oit numerous system-level performance optimizations. the wimge attributes control the following: write-through (w bit) caching-inhibited (i bit) memory-coherency-required (m bit) guarded (g bit) endianness (e bit) in addition to the wimge bits, the book e mmu model defines the following attributes on a page basis: user-definable (u 0, u1, u2, u3) the eis defines the following optional attributes, which are manipulated by software through mmu assist register 2 (mas2): alternate coherency mode (acm). the acm attribute, programmed through mas2[acm], allows an implementation to employ multiple coherency methods and to participate in multiple coherency protocols. if the m attribute (memory coherence required) is not set for a page (m = 0), the page has no coherency associated with it and the acm attribute is ignored. if the m attribute is set for a page (m = 1), the acm attribute determines the coherency domain (or protocol) used. acm values are implementation dependent. variable length encoding (vle). the vle attribute, mas2[vle], identifies pages that contain instructions from the vle instruction set. if vle = 0, instructions fetched from the page are decoded and executed as powerpc (and associated eis apus) instructions. if vle = 1, instructions fetched from the page are decoded and executed as power embedded instructions. consult the user documentation to determine whether the eis-defined attributes are implemented. the wimge attributes are programmed by the operating system for each page. the w and i attributes control how the processor performing an access uses its own cache. the m attribute ensures that coherency is maintai ned for all copies of the addressed memory location. the g attribute prevents speculative loading from the addressed memory location. (an operation is said to be performed speculatively if, at the time that it is performed, it is not known to be required by the sequential execution model.) the e attribute defines the order in which the bytes that comprise a multiple-byte data object are stored in memory (big- or little-endian). the wimge attributes occupy 5 bits in the tlb entries for page address translation. the operating system writes the wimge bits for each page into the tlb entries in system memory as it maps translations. for more information, see tlb entries on page 319 .? RM0004 storage architecture 284/1176 all combinations of these attributes are suppo rted except those that simultaneously specify a region as write-through and caching-inhibited. write-through and caching-inhibited attributes are mutually exclusive because the write-through attribute permits the data to be in the data cache while the caching-inhibited attribute does not. memory that is write-through or caching-inhibited is not intended for general-purpose programming. for example, lwarx and stwcx. instructions may cause the system dsi exception handler to be invoked if they specify a location in memory having either of these attributes. some implementations take a data storage interrupt if the location is write- through but does not take the interrupt if the location is cache-inhibited. note that, except that the guarded bit does not prevent instruction prefetches, the definitions of the wimg bits are unchanged write-through attribute a page marked w = 0 is considered to be write-back. if some store instructions executed by a given processor access locations in a block as write-through and other store instructions executed by the same processor access locations in that block as write-back, software must ensure that the block cannot be accessed by another processor or mechanism in the system. a store to a write-through (w = 1) memory location is performed in main memory and may cause additional memory locations to be accessed. if a copy of the block containing the specified location is retained in the data cache, the store is also performed in the data cache. a store to write-through memory cannot cause a block to be put in a modified state in the data cache. also, if a store instruction that accesses a block in a location marked as write-through is executed when the block is already considered to be modified in the data cache, the block may continue to be considered to be modified in the data cache even if the store causes all modified locations in the block to be written to main memory. in some processors, accesses caused by separate store instructions that specify locations in write-through memory may be combined into one access. this is called store-gathering. such combining does not occur if the store instructions are separated by an msync or an mbar . caching-inhibited attribute a load instruction that specifies a location in caching-inhibited (i = 1) memory is performed to main memory and may cause additional locations in main memory to be accessed unless the specified location is also guarded. an instruction fetch from caching-inhibited memory may cause additional words in main memory to be accessed. no copy of the accessed locations is placed into the caches. in some processors, nonoverlapping accesses caused by separate load instructions that specify locations in caching- inhibited memory may be combined into one access, as may nonoverlapping accesses caused by separate store instructions to caching-inhibited memory (that is, store-gathering). such combining does not occur if the load or store instructions are separated by an msync instruction, or by an mbar instruction if the memory is also guarded. memory-coherence-required attribute memory coherence refers to the ordering of stores to a single location. atomic stores to a given location are coherent if they are serialized in some order, and no processor or mechanism is able to observe any subset of those stores as occurring in a conflicting order. this serialization order is an abstract seque nce of values; the physical location need not storage architecture RM0004 285/1176 assume each of the values written to it. for example, a processor may update a location several times before the value is written to physical memory. the result of a store operation is not available to every processor or mechanism at the same instant, and it may be that a processor or mechanism observes only some of the values that are written to a location. however, when a location is accessed atomically and coherently by all processors and mechanisms, the sequence of values loaded from the location by any processor or mechanism during any interval of time forms a sub-sequence of the sequence of values that the location logically held during that interval. that is, a processor or mechanism can never load a newer value first and then, later, load an older value. memory coherence is managed in blocks called c oherence blocks. although a block?s size is implementation-dependent, it is usually larger than a word and is often the size of a cache block. when memory coherence is not required (m = 0), the hardware need not enforce data coherence for memory accesses initiated by the processor. when memory coherence is required (m = 1), the hardware must enforce data coherence for memory accesses initiated by the processor. hardware support for the memory-coherence-required attribute is optional for implementations that do not support multiprocessing. guarded attribute when the guarded bit is set, the page is designated as guarded. this setting can be used to protect certain memory areas from read accesses made by the processor that are not dictated directly by the program. if areas of physical memory are not fully populated (in other words, there are holes in the physical memory map within this area), this setting can protect the system from undesired accesses caused by speculative (ref erred to as ?out of order? in the architecture specification, and described in definition of apeculative and out-of-order memory accesses on page 285 ? ) load operations that could lead to the generation of the machine check exception. also, the guarded bit can be used to prevent speculative load operations from occurring to certain peripheral devices that produce undesired results when accessed in this way. definition of apeculative and out-of-order memory accesses in the architecture definition, the term ?out of order? replaced the term ?speculative? with respect to memory accesses to avoid a conflict between the word?s meaning in the context of execution of instructions past unresolved branches. the architecture?s use of out of order in this context could in turn be confused with the notion of loads and stores being reordered in a weakly ordered memory system. in the context of memory accesses, this docume nt uses the terms ?speculative? and ?out of order? as follows: speculative memory access?an access to memory that occurs before it is known to be required by the sequential execution model. out-of-order memory access?a memory access performed ahead of one that may have preceded it in the sequential model, such as is allowed by a weakly ordered memory model. performing operations speculatively an operation is said to be nonspeculative if it is guaranteed to be required by the sequential execution model. any other operation is said to be performed speculatively, which the architecture specification refers to as out of order. RM0004 storage architecture 286/1176 operations are performed spec ulatively by hardware on the ex pectation that the results will be needed by an instruction that will be requ ired by the sequenti al execution model. whether the results are needed depends on whether control flow is diverted away from the instruction by an event such as an exception, branch, trap, system call, return from interrupt instruction, or anything else that changes the context in which the instruction is executed. typically, the hardware performs operations speculatively when it has resources that would otherwise be idle, so the operation incurs little or no cost. if subsequent events such as branches or exceptions indicate that the operation would not have been performed, the processor abandons any results of the operation except as described below. most operations can be performed speculatively, as long as the machine appears to follow the sequential execution model. certain speculative operations are restricted, as follows: stores?a store instruction cannot execute speculatively in a manner such that the alteration of the target location can be observed by other processors or mechanisms. accessing guarded memory?the restrictions for this case are given in speculative accesses to guarded memory on page 286 .? no error of any kind other than a machine check exception may be reported due to an operation that is performed speculatively, until such time as it is known that the operation is required by the sequential execution model. the only other permitted side effect (other than machine check) of performing an operation speculatively is that nonguarded memory locations that could be fetched into a cache by nonspeculative execution may be fetched speculatively into that cache. guarded memory memory is said to be well behaved if the corresponding physical memory exists and is not defective, and if the effects of a single access to it are indistinguishable from the effects of multiple identical accesses to it. data and in structions can be fetched speculatively from well-behaved memory without causing undesired side effects. memory is said to be guarded if the g bit is set for the page. in general, memory that is not well-behaved should be guarded. because such memory may represent an i/o device or include nonexistent locations, a speculativ e access to such memory may cause an i/o device to perform incorrect operations or may cause a machine check. note that if separate store instructions access memory that is both caching-inhibited and guarded, the accesses are performed in the order specified by the program. if an aligned load or store that is not a string or multiple access to caching-inhibited, guarded memory has accessed main memory and an external, decrementer, or imprecise-mode floating-point enabled exception is pending, the load or store is completed before the exception is taken. speculative accesses to guarded memory accesses for load instructions from guarded memory may be performed speculatively if a copy of the target location is in a cache; in this case, the location may be accessed from the cache or from main memory. note that software should ensure that only well-behaved memory is loaded into a cache, either by marking as caching-inhibited (and guarded) all memory that may not be well- behaved or by marking such memory caching-allowed (and guarded) and referring only to cache blocks that are well-behaved. storage architecture RM0004 287/1176 instrubction accesses: guarded memory and no-execute memory the g bit is ignored for instruction fetches, and instructions are speculatively fetched from guarded pages. to prevent speculative fetches from pages that do not contain instructions and are not well-behaved, the page should be designated as no-execute (with the ux/sx page permission bits cleared). if the effective address of the current instruction is mapped to no-execute memory, an isi exception is generated. endianness objects may be loaded from or stored to memory in byte, half-word, word, or double-word units. for a particular data length, the load and store operations are symmetrical; a store followed by a load of the same data object yields an unchanged value. book e makes no guarantees about the order in which the bytes that comprise multiple-byte data objects are stored into memory. the endianness (e) page attribute distinguishes between memory that is big or little endian, as described in the following subsections. except for instruction fetches, it is always permitted to access the same location using two effective addresses with different e bit settings. instruction pages must be flushed from any caches before the e bit can be changed for those addresses. see byte ordering on page 141 ,? for more information about endianness. big-endian pages if a stored multiple-byte object is probed by reading its component bytes one at a time using load-byte instructions, the store order may be perceived. if such probing shows that the lowest memory address contains the highest-order byte of the multiple-byte scalar, the next- higher sequential address the next-least-significant byte, and so on, the multiple-byte object is stored in big-endian form. big-endian memory is defined on a page basis by the memory/cache attribute, e = 0. note that strings are not multiple-byte scalars but are interpreted as a series of single-byte scalars. bytes in a string are loaded from memory using a load string word instruction, starting at the lowest-numbered address, and placed into the target register or registers starting at the left-most byte of the least-significant word. bytes in a string are stored using a store string word instruction from the source register, starting at the left-most byte of the least-significant word, and placed into memory, starting at the lowest-numbered address. little-endian pages alternatively, if the probing shows that the lowest memory address contains the lowest-order byte of the multiple-byte scalar, the next-higher sequential address the next-most-significant byte, and so on, the multiple-byte object is st ored in little-endian form. little-endian memory is defined on a page basis by the memory/cache attribute, e = 1, and for book e devices is defined as true little-endian memory. structure mapping examples the following c programming example defines the data structure s used in this section to demonstrate how the bytes that comprise each element (a, b, c, d, e, and f) are mapped into memory. the structure contains scalars (shown in hexadecimal in the comments) and a sequence of characters, shown in single quotation marks. struct { int a; /* 0x1112_1314 word*/ double b; /* 0x2122_2324_2526_2728double word*/ char * c; /* 0x3132_3334 word*/ char d[7]; /* 'l','m','n','o','p ','q','r' array of bytes*/ RM0004 storage architecture 288/1176 short e; /* 0x5152 half word*/ int f; /* 0x6162_6364 word*/ } s; big-endian mapping of the structure ia shown below. big-endian mapping of structure note that the msb of each scalar is at the lowest address. the mapping uses padding (indicated by (x)) to align the scalars?4 bytes between elements a and b, 1 byte between d and e, and 2 bytes between e and f. note that the padding is determined by the compiler, not the architecture. the structure using little-endian mapping, showing double words laid out with addresses increasing from right to left. little-endian mapping of structure s ?alternate view contents 11 12 13 14 (x) (x) (x) (x) address0001020304050607 contents 21 22 23 24 25 26 27 28 address 08 09 0a 0b 0c 0d 0e 0f contents 31 32 33 34 ?l? ?m? ?n? ?o? address1011121314151617 contents ?p? ?q? ?r? (x) 51 52 (x) (x) address 18 19 1a 1b 1c 1d 1e 1f contents 61 62 63 64 (x) (x) (x) (x) address2021222324252627 contents (x) (x) (x) (x) 11 12 13 14 address0706050403020100 contents 21 22 23 24 25 26 27 28 address 0f 0e 0d 0c 0b 0a 09 08 contents ?o? ?n? ?m? ?l? 31 32 33 34 address1716151413121110 contents (x) (x) 51 52 (x) ?r? ?q? ?p? address 1f 1e 1d 1c 1b 1a 19 18 contents (x) (x) (x) (x) 61 62 63 64 address2726252423222120 storage architecture RM0004 289/1176 mismatched memory cache attributes accesses to the same memory location using two effective addresses for which the write- through required attribute (w bit) differs meet the memory coherence requirements described in write-through attribute on page 284 ,? if the accesses are performed by a single processor. if the accesses are performed by two or more processors, coherence is enforced by the hardware only if the write-through attribute is the same for all the accesses. loads, stores, dcbz instructions, and instruction fetches to the same memory location using two effective addresses for which the caching-inhibited attribute (i bit) differs must meet the requirement that a copy of the target location of an access to caching-inhibited memory not be in the cache. violation of this requirement is considered a programming error; software must ensure that the location has not previously been brought into the cache or, if it has, that it has been flushed from the cache. if the programming error occurs, the result of the access is boundedly undefined. it is not considered a programming error if the target location of any other cache management instruction to caching-inhibited memory is in the cache. accesses to the same memory location using two effective addresses for which the memory coherence attribute (m bit) differs may require explicit software synchronization before accessing the location with m = 1 if the location has previously been accessed with m = 0. any such requirement is syst em-dependent. for example, in some systems that use bus snooping, no software synchronization may be required. in some directory-based systems, software may be required to execute dcbf instructions on each processor to flush all cache entries accessed with m = 0 before accessing those locations with m = 1. accesses to the same memory location using two effective addresses for which the guarded attribute (g bit) differs are always permitted. except for instruction fetches, accesses to the same memory location using two effective addresses for which the endian storage attribute (e bit) differs are always permitted as described in endianness on page 287 .? instruction memory locations must be flushed before the endian attribute can be changed for those addresses. the requirements on mismatched user-defined memory attributes (u0?u3) is implementation-dependent. coherency paradoxes and wimge care must be taken with respect to the use of the wimge bits if coherent memory support is desired. careless programming of these bits may create situations that present coherency paradoxes to the processor. these paradoxes c an occur within a single processor or across several processors. it is important to note that, in the presence of a paradox, the operating system software is respon sible for correctness. in particular, a coherency paradox can occur when the state of these bits is changed without appropriate precautions (such as flushing the pages that correspond to the changed bits from the caches of all processors in the system) or when the address translations of aliased real addresses specify different values for certain wimge bit values. for more information, see mismatched memory cache attributes on page 289 .? support for m = 1 memory is optional. cache attribute settings where both w = 1 and i = 1 are not supported. for all supported combinations of the w, i, and m bits, both g and e may be 0 or 1. the default setting of the wimge bits is 0b01000. RM0004 storage architecture 290/1176 self-modifying code when a processor modifies any memory location that can contain an instruction, software must ensure that the instruction cache is made consistent with data memory and that the modifications are made visible to the instruction fetching mechanism. this must be done even if the cache is disabled or if the page is marked caching-inhibited. the following instruction sequence can be used to accomplish this when the instructions being modified are in memory that is memory-coherence required and one processor both modifies the instructions and executes them. (additional synchronization is needed when one processor modifies instruct ions that anoth er will execute.) the following sequence synchronizes the instruction stream (using either dcbst or dcbf ): dcbst (or dcbf )|update memory msync |wait for update icbi |remove (invalidate) copy from instruction cache msync |ensure that icbi invalidation at icache has completed isync |remove copy in own instruction buffer 5.2.2 shared memory the architecture supports sharing memory between programs, between different instances of the same program, and between processors and other mechanisms. it also supports access to a memory location by one or more programs using different effective addresses. in these cases, memory is shared in blocks that are an integral number of pages. when one physical memory location has different effective addresses, the addresses are said to be aliases. each application can be granted separate access privileges to aliased pages. lock acquisition and import barriers on page 294 ,? gives examples of how msync and mbar are used to control memory access ordering when memory is shared among programs. memory access ordering the memory model in book e for memory ac cess ordering is weakly consistent. this provides an opportunity for improved performance over a model with stronger consistency rules but places the responsibility on the progra m to ensure that orderi ng or synchronization instructions are properly placed for correct execution of the program. the order in which a processor accesses memory, the order in which those accesses are performed with respect to other processors or mechanisms, and the order in which they are performed in main memory may all be different. ta bl e 1 8 0 describes how the architecture defines requirements for ordering of loads and stores. storage architecture RM0004 291/1176 when a processor (p1) executes msync or mbar , a memory barrier is created that separates applicable memory accesses into two groups, g1 and g2. g1 includes all applicable memory accesses associated with instructions preceding the barrier-creating instruction, and g2 includes all applicable memory accesses associated with instructions following the barrier-creating instruction. ta bl e shows an example using a two-processor system. table 180. load and store ordering type of access architecture definition load ordering with respect to other loads the architecture guarantees that loads that are both caching-inhibited (i = 1) and guarded (g = 1) are not reordered with respect to one another. if a load instruction depends on the value returned by a preceding load (because the value is used to compute the effective address specified by the second load), the corresponding memory accesses are performed in program order with respect to any processor or me chanism to the ext ent required by the associated memory coherence required attributes (that is, the memory coherence required attribute, if any, a ssociated with each access). this applies even if the dependency does not affect program logic (for example, the value returned by the first load is anded with zero and then added to the effective address specified by the second load). store ordering with respect to other stores if two store instructions specify me mory locations that are both caching inhibited and guarded, the corresponding memory accesses are performed in program order with respect to any processor or mechanism. otherwise, stores are weakly ordered with respect to one another. store ordering with respect to loads the architecture specifies that an msync or mbar must be used to ensure sequential ordering of loads with respect to stores. table 181. memory barrier when coherency is required (m = 1) processor 1 (p1) memory access groups g1 and g2 processor 2 (p2) instruction 1 g1: memory accesses generated by p1 before the memory barrier when memory coherence is required, g1 accesses that affect p2 are also performed before the memory barrier. instruction 2 instruction 3 instruction 4 instruction 5 ( msync or mbar )?memory barrier barrier generated by p1 does not order p2 instructions or associated accesses with respect to other p2 instructions and associated accesses. instruction 6 g2: memory accesses generated by p1 after the memory barrier when memory coherence is required, g2 accesses that affect p2 are also performed after the memory barrier. instruction 7 instruction 8 instruction 9 instruction 10 RM0004 storage architecture 292/1176 the memory barrier ensures that all memory accesses in g1 are performed with respect to any processor or mechanism, to the extent required by the associated memory coherence required attributes (that is, the memory-coherence required attribute, if any, associated with each access), before any memory accesses in g2 are performed with respect to that processor or mechanism. the ordering enforced by a memory barrier is said to be cumulative if it also orders memory accesses that are performed by processors and mechanisms other than p1, as follows: g1 includes all applicable memory accesses by any such processor or mechanism that have been performed with respect to p1 before the memory barrier is created. g2 includes all applicable memory accesses by any such processor or mechanism that are performed after a load instruction executed by that processor or mechanism has returned the value stored by a store that is in g2. table 182 shows an example of a cumulative memory barrier in a two-processor system. table 182. cumulative memory barrier a memory barrier created by msync is cumulative and applies to all accesses except those associated with fetching instructions following the msync . see the definition of mbar in memory synchronization instructions on page 175 ,? for a description of the corresponding properties of the memory barrier created by that instruction. programming considerations because stores cannot be performed out of program order, as described in book e, if a store instruction depends on the value returned by a preceding load (because the value the load returns is needed to compute either the effective address specified by the store or the value to be stored), the corresponding accesses are guaranteed to be performed in program order. the same applies whether or not the store instruction executes is dependent upon a conditional branch that in turn depends on the value returned by a preceding load. for example, if a conditional branch depends on a preceding load and that branch chooses processor 1 (p1) memory access groups g1 and g2 processor 2 (p2) p1 instruction 1 g1: memory accesses generated by p1 and p2 that affect p1. includes accesses generated by executing p2 instructions l?o (assuming that the access generated by instruction o occurs before p1?s msync is executed). p2 instruction l p1 instruction 2 p2 instruction m p1 instruction 3 p2 instruction n p1 instruction 4 p2 instruction o p1 instruction 5 ( msync )?cumulative memory barrie r applies to all accesses except those associated with fetc hing instructions following msync . p2 instruction p p2 instruction q p2 instruction r p1 instruction 6 g2: memory accesses generated by p1 and p2. includes accesses generated by p2 instructions p?x (assuming that the access generated by instruction p occurs after p1?s msync is executed) performed after a load instruction executed by p2 has returned the value stored by a store that is in g2. the msync memory barrier does not affect accesses associated with instruction fe tching that occur after the msync . p2 instruction s p1 instruction 7 p 2 instruction t p1 instruction 8 p2 instruction u p1 instruction 9 p2 instruction v p1 instruction 10 p2 instruction w p1 instruction 11 p2 instruction x storage architecture RM0004 293/1176 between a path that includes a store instruction if the condition is met, that dependent store is not performed unless and until the condition determined by the load is met. because instructions following an isync cannot execute until all instructions preceding isync have completed, if an isync follows a conditional branch instruction that depends on the value returned by a preceding load instruction, that load is performed before any loads caused by instructions following the isync . this is true even if the effects of the dependency are independent of the value loaded (for example, the value is compared to itself and the branch tests cr n [eq]), and even if the branch target is the next sequential instruction. except for the cases described above and earlier in this section, data and control dependencies do not order memory accesses. examples include the following: if a load specifies the same memory locati on as a preceding store and the location is not caching inhibited, the load may be satisfied from a store queue (a buffer into which the processor places stored values before presenting them to the memory subsystem) and not be visible to other processors and mechanisms. as a result, if a subsequent store depends on the value returned by the load, the two stores need not be performed in program order with respect to other processors and mechanisms. because a store conditional instruction may complete before its store is performed, a conditional branch instruction that depends on the cr0 value set by a store conditional instruction does not order that store with respect to memory accesses caused by instructions that follow the branch. for example, in the following sequence, the stw is the bc instruction?s target: stwcx. bc stw to complete, the stwcx. must update the architected cr0 value, even though its store may not have been performed. the architecture does not require that the store generated by the stwcx. must be performed before the store generated by the stw . because processors may predict branch target addresses and branch condition resolution, control dependencies (branches, for example) do not order memory accesses except as described above. for example, when a subroutine returns to its caller, the return address may be predicted, with the result that loads caused by instructions at or after the return address may be performed before the load that obtains the return address is performed. some processors implement nonarchitected duplicates of architected resources such as gprs, cr fields, and the lr, so resource dependencies (for example, specification of the same target register for two load instructions) do not force ordering of memory accesses. examples of correct uses of dependencies, msync , and mbar to order memory accesses can be found in hi .? because the memory model is weakly consisten t, the sequential execution model as applied to instructions that cause memory accesses gu arantees only that those accesses appear to be performed in program order with respect to the processor executing the instructions. for example, an instruction may complete, and subsequent instructions may be executed, before memory accesses caused by the first instruction have been performed. however, for a sequence of atomic accesses to the same memory location for which memory coherence is required, the definition of coherence guarantees that the accesses are performed in program order with respect to any processor or mechanism that accesses the location coherently, and similarly if the location is one for which caching is inhibited. RM0004 storage architecture 294/1176 because caching-inhibited memory accesses are performed in main memory, memory barriers and dependencies on load instructions order such accesses with respect to any processor or mechanism even if the memory is not marked as requiring memory coherence. programming examples example 1 shows cumulative ordering of memory accesses preceding a memory barrier, example 2 shows cumulative ordering of memory accesses following a memory barrier. in both examples, assume that locations x, y, and z initially contain the value 0. in both, cumulative ordering dictates that the value loaded from location x by processor c is 1. e xample 1: processor a stores the value 1 to location x. processor b loads from location x obtaining the value 1, executes an msync , then stores the value 2 to location y. processor c loads from location y obtaining the value 2, executes an msync , then loads from location x. example 2: processor a stores the value 1 to location x, executes an msync , then stores the value 2 to location y. processor b loops, loading from location y until the value 2 is obtained, then stores the value 3 to location z. processor c loads from location z obtaining the value 3, executes an msync , then loads from location x. lock acquisition and import barriers an import barrier is an instruction or instruction sequence that prevents memory accesses caused by instructions following the barrier from being performed before memory accesses that acquire a lock have been performed. an import barrier can be used to ensure that a shared data structure protected by a lock is not accessed until the lock has been acquired. an msync can always be used as an import barrier, but the approaches shown below generally yield better performance because they order only the relevant memory accesses. acquire lock and import shared memory if lwarx and stwcx. are used to obtain the lock, an import barrier can be constructed by placing an isync immediately following the loop containing the lwarx and stwcx. . the following example uses the compare and swap primitive (see chapter c.1.1: synchronization primitives on page 1144 ? ) to acquire the lock. this example assumes that the address of the lock is in gpr 3, the value indicating that the lock is free is in gpr 4, the value to which th e lock should be set is in gpr 5, the old value of the lock is returned in gpr 6, and the address of the shared data structure is in gpr 9. loop:lwarxr6,0,r3 # load lock and reserve cmpw r4,r6 # skip ahead if bne- wait # lock not free stwcx. r5,0,r3 # try to set lock bne- loop # loop if lost reservation isync # import barrier lwz r7,data1(r9) # load shared data . . wait: ... #wait for lock to free storage architecture RM0004 295/1176 the second bne- does not complete until cr0 has been set by the stwcx. . the stwcx. does not set cr0 until it has comple ted (successfully or unsuccessfu lly). the lock is acquired when the stwcx. completes successfully . together, the second bne- and the subsequent isync create an import barrier that prevents the load from data1 from being performed until the branch is resolved to be not taken. obtain pointer and import shared memory if lwarx and stwcx. are used to obtain a pointer into a shared data structure, an import barrier is not needed if all the accesses to the shared data structure depend on the value obtained for the pointer. the following example uses the fetch and add primitive (see section c.1.1: synchr onization primitives ? ) to obtain and increment the pointer. in this example, it is assumed that the address of the pointer is in gpr 3, the value to be added to the pointer is in gpr 4, and the old value of the pointer is returned in gpr 5. loop: lwarx r5,0,r3 # load pointer and reserve add r0,r4,r5 # increment the pointer stwcx. r0,0,r3 # try to store new value bne- loop # loop if lost reservation lwz r7,data1(r5) # load shared data the load from data1 cannot be performed until the lwarx loads the pointer value into gpr 5. the load from data1 may be performed out of order before the stwcx. . but if the stwcx. fails, the branch is taken and the value returned by the load from data1 is discarded. if the stwcx. succeeds, the value returned by the load from data1 is valid even if the load is performed out of order, because the load uses the pointer value returned by the instance of the lwarx that created the reservation used by the successful stwcx. . an isync could be placed between the bne- and the subsequent lwz , but no isync is needed if all accesses to the shared data structure depend on the value returned by the lwarx . atomic memory references the book e architecture defines the load word and reserve indexed ( lwarx ) and the store word conditional indexed ( stwcx. ) instructions to provide an atomic update function for a single, aligned word of memory. these instructions can be used to develop a rich set of multiprocessor synchronization primitives. note that atomic memory references constructed using lwarx / stwcx. instructions depend on the presence of a coherent memory system for correct operation. these instructions should not be expected to provide atomic access to noncoherent memory. the lwarx instruction performs a load word from memory operation and creates a reservation for the same reservation granule that contains the accessed word. reservation granularity is implementation-dependent. the lwarx instruction makes a nonspecific reservation with respect to the executing processor and a specific reservation with respect to other masters. this means that any subsequent stwcx. executed by the same processor, regardless of address, cancels the reservation. also, any bus write or invalidate operation from another processor to an address that matches the reservation address cancels the reservation. RM0004 storage architecture 296/1176 5.3 cache model a cache model in which there is one cache for instructions and another cache for data is called a ?harvard-style? cache. this is the model assumed by book e, for example in the descriptions of the cache management instructions in chapter 3: instruction model on page 133 .? book e allows the following additional cache models are defined by the eis: unified cache, in which a cache is shared by both instructions and data multi-level caches, which must support t he programming model implied by a harvard- style cache. a processor is not required to maintain copies of storage locations in the instruction cache that are consistent with modifications to those storage locations (that is, modifications by store instructions). in general, a location in the data cache is considered to be modified in that cache if the location has been modified (for example, by a store instruction) and the modified data has not been written to main storage. the only exception to this rule is described in write- through attribute on page 284 .? cache management instructions are provided so that programs can manage the caches when needed. for example, program management of the caches is needed when a program generates or modifies code that will be executed (i.e., when the program modifies data in storage and then attempts to execute the modified data as instructions). cache management instructions are also useful in optimizing the use of memory bandwidth in such applications as graphics and numerically intensive computing. the functions performed by these instructions depend on the storage attributes associated with the specified storage location. cache management instructions allow the program to do the following. give a hint that a block of storage should be copied to the instruction cache, so that the copy of the block is more likely to be in the cache when subsequent accesses to the block occur, thereby reducing delays ( icbt ) invalidate the copy of storage in an instruction cache block ( icbi ) discard prefetched instructions ( isync ) invalidate the copy of storage in a data cache block ( dcbi ) give a hint that a block of storage should be copied to the data cache, so that the copy of the block is more likely to be in the cache when subsequent accesses to the block occur, thereby reducing delays ( dcbt , dcbtst ) allocate a data cache block and set the contents of that block to zeros, but no-operation if no access is allowed to the data cache block and do not cause any exceptions ( dcba ) set the contents of a data cache block to zeros ( dcbz ) copy the contents of a modified data cache block to main storage ( dcbst ) copy the contents of a modified data cache block to main storage and make the copy of the block in the data cache invalid ( dcbf ). 5.3.1 cache programming model this section summarizes the register and instructions defined to support the cache model. full descriptions of these resources are provided in chapter 2: register model on page 46 , and chapter 3: instruction model on page 133 . storage architecture RM0004 297/1176 cache model registers the eis cache model implements the following registers and register fields: machine state register (msr). defines the processor state (that is, enabling and disabling of interrupts and debugging exceptions, enabling and disabling of address translation for instruction and data memory accesses, enabling and disabling some apus, and specifying whether the processor is in supervisor or user mode). eis storage defines the user cache locking enable bit (msr[ucle]) as part of the cache line locking apu. book e and the eis define the msr fields described in table 183 . the msr is described in detail in chapter 2.6.1: machine state register (msr) on page 68 .? exception syndrome register (esr). the esr provides a syndrome to differentiate between different kinds of exceptions that can generate the same interrupt type. when such an interrupt is generated, bits corresponding to the exception that generated the interrupt are set and all other esr bits are cleared. other interrupt types do not affect esr contents. the esr does not need to be cleared by software. book e and the eis defines the storage-related esr fields described in table 184 . the esr is described in detail in exception syndrome register (esr) on page 84 .? table 183. storage related msr fields bits name description 37 ucle (eis-defined) user-mode cache lock enable. used to restrict user- mode cache-line locking by the operating system. 0any cache lock instruction executed in user-mode takes a cache- locking exception and data storage interrupt and sets either esr[dlk] or esr[ilk]. this allo ws the operating system to manage and track the locking/unlocking of cache lines by user- mode tasks. 1cache-locking instructions can be executed in user-mode and they do not take a dsi for cache-locking (they may still take a dsi for access violations though). 58 is (book e?defined) instruction address space 0the processor directs all instruction fetches to address space 0 (ts = 0 in the relevant tlb entry). 1the processor directs all instruction fetches to address space 1 (ts = 1 in the relevant tlb entry). 59 ds (book e?defined) data address space 0the processor directs data memory accesses to address space 0 (ts = 0 in the relevant tlb entry). 1the processor directs data memory accesses to address space 1 (ts = 1 in the relevant tlb entry). RM0004 storage architecture 298/1176 table 184. exception syndrome register (esr) definition bits name syndrome interrupt types 39 fp (book e?defined) floating-point operations alignment, data storage, data tlb, program 40 st (book e?defined) store operation alignment, data storage, data tlb error 42 dlk defined by cache line lock ing apu. instruction cache locking attempt. set when a dsi occurs because a dcbtls , dcbtstls , or dcblc was executed in user mode (msr[pr] = 1) while msr[ucle] = 0. 0default 1dsi occurred on an attempt to lock line in data cache when msr[ucle] = 0. data storage 43 ilk defined by cache line lock ing apu. instruction cache locking attempt. set when a dsi occurs because an icbtls or icblc was executed in user mode (msr[pr] = 1) while msr[ucle] = 0. 0default 1dsi occurred on an attempt to lock line in instruction cache when msr[ucle] = 0. data storage 44 apu (book e?defined) auxiliary processor operation. alignment, data storage, data tlb, program 46 bo byte-ordering exception. defined by book e and the vle extension. data storage, instruction storage storage architecture RM0004 299/1176 l1 cache control and status registers (l1csr0?l1csr1). ? l1csr0 provides general control and status for the processor?s primary data cache. if a processor implements a unified l1 cache, l1csr0 applies to the unified cache and l1csr1 is not implemented. see chapter 2.11.1: l1 cache control and status register 0 (l1csr0) on page 90 .? ? l1csr1 provides general control and status for the processor?s primary instruction cache. if a processor implements a unified l1 cache, l1csr0 applies 56 spe defined by spe, embedded floating-point apu. spe/embedded floa ting-point exception bit 0 default 1 any exception caused by an spe/embedded floating- point instruction occurred. data storage, data tlb error, alignment, spe unavailable, embedded fp unavailable, embedded fp data, embedded fp round 58 vlemi defined by vle extension. vlemi indicates that an interrupt was caused by a vle instruction. vlemi is set on an exception associated with execution or attempted execution of a vle instruction. 0 the instruction page associ ated with the instruction causing the exception does not have the vle attribute set or the vle extension is not implemented. 1 the instruction page associated with the instruction causing the exception has the vle attribute set and the vle extension is implemented. data storage, data tlb error, instruction storage, program, system call, alignment, spe unavailable, embedded fp unavailable, embedded fp data, embedded fp round 62 mif defined by the vle extension. mif indicates that an interrupt was caused by a misaligned instruction fetch (nia 62 != 0) and the vle attribute is cleared for the page or the second half of a 32-bit vle instruction caused an instruction tlb error. 0default. 1nia 62 != 0 and the instruction page associated with nia does not have the vle attribut e set or the second half of a 32-bit vle instruction caused an instruction tlb error. instruction tlb error, instruction storage 63 xte external transaction error. an external transaction reported an error but the error was handled precisely by the core. srr0 holds the address of the instruction that initiated the transaction. 0default. no external transaction error was precisely detected. 1an external transaction reported an error that was precisely detected. instruction storage, data storage table 184. exception syndrome register (esr) definition (continued) bits name syndrome interrupt types RM0004 storage architecture 300/1176 to the unified cache and l1csr1 is not implemented. see chapter 2.11.2: l1 cache control and status register 1 (l1csr1) on page 92 .? l1 cache configuration registers (l1cfg0) ? l1cfg0 provides configuration information for the processor?s primary data cache. if a processor implements a unified cache, l1cfg0 applies to the unified cache and l1cfg1 is not implemented. see chapter 2.11.3: l1 cache configuration register 0 (l1cfg0) on page 94 .? ? l1cfg1 provides configuration information for the processor?s primary instruction cache. if a processor implements a unified cache, l1cfg0 applies to the unified cache and l1cfg1 is not implemented. l1cfg1 allows software to identify the organization and capabilities of the primary instruction cache. chapter 2.11.4: l1 cache configuration register 1 (l1cfg1) on page 95 .? cache model instructions the book e powerpc architecture defines instructions for controlling both the instruction and data caches (when they exist). data cache block touch ( dcbt ) data cache block touch for store ( dcbtst ) data cache block zero ( dcbz ) data cache block store ( dcbst ) data cache block flush ( dcbf ) data cache block allocate ( dcba ) data cache block invalidate ( dcbi ) instruction cache block invalidate ( icbi ) instruction synchronize ( isync ) instruction cache block touch ( icbt ) these instructions are described in user-level cache instructions on page 180 ,? and supervisor-level cache instruction on page 183 .? note that the behavior of many of these instructions is determined by the value of the cache target operand (ct). see ct instruction field on page 301 .? permission control and cache management instructions on page 316 ,? describes conditions in which cache control instructions can generate protection violations. the cache block locking apu, defined by the eis, adds the following instructions: data cache block lock clear ( dcblc ) data cache block touch and lock set ( dcbtls ) data cache block touch for store and lock set ( dcbtstls ) instruction cache block lock clear ( icblc ) instruction cache block touch and lock set ( icbtls ) these instructions are described in chapter 8.1: cache line locking apu on page 848 .? storage architecture RM0004 301/1176 ct instruction field instructions having a ct (cache target) field for specifying a cache hierarchy use the value 0 to specify the primary cache. st devices interpret this operand as follows: ct = 0 indicates the l1 cache. ct = 1 indicates the i/o cache. (note that some versions of the e500 documentation refer to the i/o cache as a frontside l2 cache.) ct = 2 indicates a backside l2 cache. 5.3.2 primary (l1) cache model this section describes the l1 cache model defined by the eis. types primary caches may separate instruction and data caches into two separate structures (commonly known as harvard architecture), or they may provide a unified cache combining instructions and data. caches are physically tagged. storage attributes and coherency primary data caches must support the storage attributes defined by book e with the following advisory: note: the primary data cache may be implemented not to snoop (that is, not coherent with transactions outside the processor). system software is then responsible to maintain coherency. thus the setting of the m attribute is meaningless. the preferred implementation provides snooping for primary data caches. primary instruction caches must support the storage attributes defined by book e with the following advisory: the guarded attribute should be ignored for instruction fetch accesses. to prevent speculative fetch accesses to guarded memo ry, software should mark those pages as no-execute. the cache may be implemented not to snoop (that is, not coherent with transactions outside the processor). system software is then responsible to maintain coherency. the preferred implementation does not provide snooping for primary instruction caches. as with other memory-related instructions, the effects of cache management instructions on memory are weakly-ordered. if the programmer must ensure that cache or other instructions have been performed with respect to all other processors and system mechanisms, an msync must be placed after those instructions. 5.4 storage model this section describes the storage model as it is defined by book e and by the eis. 5.4.1 storage programming model this section summarizes the register and instructions defined to support the cache model. full descriptions of these resources are provided in chapter 2: register model on page 46 ,? and chapter 3: instruction model on page 133 .? RM0004 storage architecture 302/1176 storage model registers this section provides an overview of the registers used for programming the mmu. full descriptions are provided in chapter 2.12: mmu registers on page 97 .? these registers consist of the following: process id registers (pid0?pid2) are used by system software to identify tlb entries that are used by the processor to accomplish address translation for loads, stores, and instruction fetches. book e defines one pid register (pid synonymous with pid0). the eis defines 14 additional pid registers, pid1 through pid14. a implementation may choose to provide any number of pids up to a maximum of 15. the number of pids implemented is indicated by the value of mmucfg[npids] and the number of bits implemented in each pid register is indica ted by the value of mmucfg[pidsize]. pid values are used to construct virtual addresses for accessing memory (see chapter 5.4.6 ? ). mmu assist registers (mas0?mas7) are used to transfer data to and from the tlb arrays. software uses mfspr and mtspr to read and write mas registers. executing tlbre causes the tlb entry sp ecified by mas0[tlbsel,esel ] and mas2[epn] to be copied to the mas registers. conversely, execution of a tlbwe instruction causes the tlb entry specified by m as0[tlbsel,esel] and mas2[epn ] to be written with the mas register contents. hardware can also updated mas registers on the occurrence of an instruction or data tlb error interrupt or as the result of a tlbsx . all mas registers are supervisor level, and all except mas5 and mas7 must be implemented. mas7 is not required if the processor supports 32 bits or less of physical address. implementing mas5 is implementation dependent. processors are required to implement only the necessary bits of any multiple-bit mas register field such that only the resources supplied by the processor are represented. any non-implemented bits in a field should have no effect when writing and should storage architecture RM0004 303/1176 always read as zero. for example, a processor that implements only two tlb arrays would likely implement only the lower-order mas0[tlbsel] bits. ? mas0, contains fields for identifying and selecting a tlb entry. ? mas1, contains fields for selecting a tlb entry during translation. ? mas2, contains fields for specifying the effective page address and the storage attributes for a tlb entry. ? mas3, contains fields for specifying the real page address and the permission attributes for a tlb entry. ? mas4, contains fields for specifying de fault information to be pre-loaded on certain mmu-related exceptions. ? the optional mas5 register, contains fields for specifying pid values to be used when searching tlb entries with the tlbsx instruction. ? mas6, contains fields for specifying pid and as values used when the tlbsx instruction is used to search tlb entries. mas7, contains the high-order address bits of the rpn for implementations that support more than 32 bits of physical addres s. implementations that support 32 bits or fewer do not implement mas7. mmu configuration register (mmucfg), provides configuration information about the mmu. tlb configuration registers (tlb n cfg). one tlb n cfg register, is implemented to provide information about each tlb implemented. tlb0cfg corresponds to tlb0, tlb1cfg corresponds to tlb1, etc. mmu control and status register (mmucsr0), is used for general control of the mmu including flash invalidation of the tlb arrays and page sizes for programmable fixed size arrays. for tlb arrays with programmable fixed sizes, the tlb n _ps fields allow software to specify the page size. storage model instructions the address translation mechanism is defined in terms of tlbs and page table entries (ptes) book e processors use to locate the logical-to-physical address mapping for a particular access. table 103 on page 184 describes the operation of the tlb instructions, which are summarized as follows: tlb invalidate virtual address indexed ( tlbivax ) tlb read entry ( tlbre ) tlb search indexed ( tlbsx ) tlb synchronize ( tlbsync ) tlb write entry ( tlbwe ) 5.4.2 the storage architecture this section describes the storage model as it is defined by book e and by the st eis. book e storage architecture the memory management approach defined by the book e eis is suited for desktop applications and has the simp licity and flexibility necessary for embedded applications. book e supports demand-paged virtual memory as well as a variety of other management schemes that depend on precise control of effective-to-real address translation and flexible RM0004 storage architecture 304/1176 memory protection. address translation misses and protection faults cause precise exceptions. sufficient information is available to correct the fault and restart the faulting instruction. each program on a 32-bit implementation can access 2 32 bytes of effective address (ea) space, subject to limitations imposed by the operating system. in a typical book e system, each program?s ea space is a subset of a larger virtual address (va) space managed by the operating system. each effective (logical) address is translated to a real (physical) address before being used to access physical memory or an i/o device. hardware does this by using the address translation mechanism described in chapter 5.4.6 .? the operating system manages the physically addressed resources of the system by setting up the tables used by the address translation mechanism. the book e architecture divides the effective address space into pages. the page represents the granularity of effective ad dress translation, permission control, and memory/cache attributes. up to 12 page sizes (1, 4, 16, 64, or 256 kbytes; 1, 4, 16, 64, or 256 mbytes; or 1 gbyte) may be simultaneously supported. for an effective-to-real address translation to exist, a valid entry for the page containing the effective address must be in a translation lookaside buffer (tlb). addresses for which no tlb entry exists cause tlb miss exceptions (instruction or data tlb error interrupts). the instruction addresses generated by a program and the addresses used by load, store, and cache management instructions are effective addresses. however, in general, the physical memory space may not be large enough to map all the virtual pages used by the currently active applications. with support provided by hardware, the operating system can attempt to use the available real pages to map enough virtual pages for an application. if a sufficient set is maintained, paging activity is minimized, therefore maximizing performance. the operating system can restrict access to virtual pages by selectively granting permissions for user-state read, write, and execute, and supervisor-state read, write, and execute on a per-page basis. these permissions c an be set up for a particular system (for example, program code might be execute-only, data structures may be mapped as read/write/no-execute) and can also be changed by the operating system based on application requests and operating system policies. eis storage architecture the standard for book e mmus establishes a common way of implementing book e processors to provide a programming model that is consistent across all products in the family. having a standard reduces the software efforts required in porting to a new processor because the common programming model minimizes implementation differences. thus, the standard defines configuration information for features such as tlbs, caches, and other entities that have standard forms, but differing attributes (like cache sizes and associativity) such that a single software implementation can be created that works efficiently for all implementations of a class. storage architecture RM0004 305/1176 the book e mmu standard defines functions and structures that are visible to the execution model of the processor. these consist of the following definitions: the tlb, from a programming point of view, consists of zero or more tlb arrays, each of which may have differing characteristics. the logical-to-physical addre ss translation mechanism methods and effects of changing and manipulating tlb arrays configuration information available to the operating system that describes the structure and form of the tlb arrays and translation mechanism to assist or accelerate translation, implementations may contain other tlb structures not visible to the programming model. these structures and the methods for using them are not explicitly defined in the architecture or the st standard, but they may be considered at the operating system level because they may affect an implementation?s performance. 5.4.3 virtual address (va) book e defines a virtual address space composed of the effective address of an access, the 1-bit current address space (as) of the access and the 32-bit process id (pid) of an access, as shown in figure 16 . the following subsections describe the selection of as and pid for an effective address, both used to construct the virtual address for an access. figure 16. virtual address space in book e 5.4.4 address spaces instruction accesses are generated by sequential instruction fetches or due to a change in program flow (branches and interrupts). data accesses are generated by load, store, and cache management instructions. the book e architecture defines two address spaces for instruction accesses and two address spaces for data accesses. the current address space for instruction or data accesses is determined by the value of msr[ is] and msr[ds], respectively, as shown in figure 17 . figure 17. current address space effective address virtual address real address (logical) (physical) (program) 64-bit 1 + 32 + 64 bits 64-bit as pid ea msr[is] 0+ 1 msr[ds] 0+ 1 data effective address RM0004 storage architecture 306/1176 0 if the type of translation performed is an instruction fetch, the value of the as bit is taken from the contents of msr[is]. if the type of translation performed is a load, store, or other data translation including target addresses of software-initiated instruction fetch hints and locks ( icbt , icbtls , icbtlc ) the value of the as bit is taken from the contents of msr[ds]. the address space indicator (msr[is] or msr[ds], as appropriate) is used in addition to the effective address generated by the processor for translation into a physical address by the tlb mechanism. because msr[is] and msr[ds] are cleared when an interrupt occurs, an address space value of zero can be used to denote interr upt-related address spaces , or possibly all system software address spaces; an address space value of one can be used to denote non? interrupt-related address spaces, or possibly all user address spaces. software note: although system software is free to use address space bits as it sees fit, on an interrupt, the msr[is] and msr[ds] are cleared. this encourages software to use address space 0 for system software and address space 1 for user software. instruction address spaces the two effective instruction address spaces are defined by the value of msr[is], and instruction fetch addresses are translated from the effective address space specified by the current value of msr[is]. changing the value of msr[is] is considered a context-altering operation, requiring a context synchronizati on operation to follow it. when a context synchronizing event occurs, any prefetched instructions are discarded and instructions are refetched using the then-current state of msr[is] and the then-current program counter. see context synchronization on page 144 ,? for more information on the definition of context synchronizing events. instructions are not fetched from memory designated by the tlb mechanism as no-execute (ux = 0 or sx = 0). if the effective address of the current instruction is mapped to no- execute memory, an instruction storage interrupt (isi) is generated. note that mapping a page as no-execute does not affect instruction caches in the system (or any instructions resident in unified caches). thus, if an instruction is loaded into a cache when its effective address is mapped to execute permitted memory, and the execute permissions for that page are later changed to no-execute, any instructions fetched before the no-execute mapping remain in the cache until explicitly evicted by an icbi instruction or through the cache?s replacement policy. however, attempted execution of such instructions still results in an isi. thus, for example, the operating system can chan ge the designation of an application?s instruction pages to no-execute without having to first flush instruction cache blocks that map to these pages. data address spaces the two effective data address spaces are defined by the value of msr[ds] and data is accessed to/from the effective address space specified by the current value of msr[ds]. as is the case with msr[is], changing the value of msr[ds] is considered a context-altering operation, requiring a context synchronizati on operation to follow it. when a context synchronizing event occurs, subsequent accesses are made using the new state of msr[ds] (see context synchronization on page 144 ? ). data can be read from a page, provided the user read (ur) permission bit is set in the tlb for a user access, or the supervisor read (sr) bit is set for a supervisor access. likewise, data write access permissions are determined by the user write (uw) and supervisor write (sw) permission bits. if permissions are violated, the appropriate interrupt is taken. storage architecture RM0004 307/1176 5.4.5 process id as described in chapter 2.12.1: process id registers (pid0?pidn) on page 97 ,? book e defines that a pid value be associated with each effective address (instruction or data) generated by the processor. at the book e level, one 32-bit pid register maintains the pid value for the current process. this value is used to construct a virtual address for accessing memory. figure 18. current pid value system software uses pids to identify tlb entries that the processor uses to translate addresses for loads, stores, and instruction fetches. pid contents are compared to the tid field in tlb entries as part of selecting appropriate tlb entries for address translation. pid values are used to construct virtual addresses for accessing memory. note that individual processors may not implement all 14 bits of the process id field. book e defines one pid register that holds the pid value for the current process. st devices may implement from 1 to 15 pid registers. the number of pids implemented is indicated by the value of mmucfg[npids]. consult the user documentation for the implementation to determine if other pid registers are implemented. pid registers are more fully described in chapter 2.12.1: process id registers (pid0?pidn) on page 97 .? software note: the suggested pid usage is for pid0 to denote private mappings for a process and for other pids to handle mappings that may be common to multiple processes. this method allows for processes sharing addre ss space to also share tlb entries if the shared address space is mapped at the same virtual address in each process. process id (pid) registers the book e architecture specifies that a process id (pid) value be associated with each ea (instruction or data) generated by the processor. system software uses pids to identify tlb entries that the processor uses to translate addresses for loads, stores, and instruction fetches. pid contents are compared to the tid field in tlb entries as part of selecting appropriate tlb entries for address translation. pid values are used to construct virtual addresses for accessing memory. note that individual processors may not implement all 14 bits of the process id field. book e defines one pid register that holds the pid value for the current process. st devices may implement from 1 to 15 pid registers. the number of pids implemented is indicated by the value of mmucfg[npids]. consult the user documentation for the implementation to determine if other pid registers are implemented. the 15 pid registers supported by the eis are implemented as spr registers set by system software, and collectively reflect the process id of the currently executing context. the system maintains multiple pid values in order to allow the sharing of tlb entries for pages that are shared among multiple execution contexts. for example, system software may pid 0xnnnn_nnnn effective address RM0004 storage architecture 308/1176 assign pid0 to contain the unique process id (for private mappings for the current processes) and may assign pid1 to contain the unique process id for a common set of shared libraries. note that book e defines the value of all zeros for a tid field in a tlb entry as an entry that is globally shared. thus, when pid values (up to 12 bits for st devices) are compared to the tid fields in the tlb arrays for matches, if a tlb entry contains all zeros in the tid field, it globally matches all pid values. pid registers are more fully described in chapter 2.12.1: process id registers (pid0?pidn) on page 97 .? address space identifiers the as bit is the address space identifier. t hus there are two possible address spaces, 0 and 1. the value of the as bit is determined by the type of translation performed and from the contents of the msr when an address is translated. if the type of translation performed is an instruction fetch, the value of the as bit is taken from the contents of msr[is]. if the type of translation performed is a load, store, or other data translation including target addresses of software initiated instruction fetch hints and locks ( icbt , icbtls , icbtlc ) the value of the as bit is taken from the contents of msr[ds]. the as bit is defined by book e. note: although system software is free to use address space bits as it sees fit, it should be noted that on interrupt, the msr[is] and msr[ds] bits are cleared. this encourages software to use address space 0 for system software and address space 1 for user software. 5.4.6 address translation the effective address (ea) is the untranslated address for an instruction fetch address or for a data address that is calculated as a result of a load, store, or cache management instruction. the ea, concatenated with the msr[is] or msr[ds] address space (as) value, is compared to the appropriate number of bits of the epn field (depending on the page size) and the ts field of the tlb entry. if a match occurs, that tlb entry is a candidate for a translation match. in addition to a match in the epn field and ts, a matching tlb entry must match with the current process id of the access. figure 19 shows the translation match logic for the effective address plus its attributes (collectively called the virtual address) and how it is compared with the corresponding fields in the tlb entries. storage architecture RM0004 309/1176 figure 19. virtual address and tlb-entry comparison the generation of the physical address occurs as shown in figure 20 . figure 20. effective-to-real address translation the ea combines with the as and each pid register to form one virtual address for each unique pid register value. also . an implicit virtual address is formed using a pid value of 0. thus the following virtual addresses (vas) are formed: va0 as || 0 || ea va1 as || pid0 || ea ... van+1 as || pidn || ea tlb entry matches =0? private page shared page =? =? tlb_entry[v] tlb_entry[ts] as (from msr[is] process id tlb_entry[tid] tlb_entry[epn] ea page number bits =? virtual address or msr[ds]) 32-bit effective address 32-bit real address virtual address note: n = 32?log 2 (page size) pid effective page number (epn) offset 32 n 63 real page number (rpn) offset n63 32 tlb multiple-entry msr[is] for instruction fetch as msr[ds] for data access rpn field of matching entry n?1 n?1 RM0004 storage architecture 310/1176 note that a pid register containing a 0 value (or the same value as another pid register) forms a non-unique va. duplicate vas are ignored. each of the unique vas are compared to all the valid tlb entries by comparing specific fields of each tlb entry to each of the vas. the fields of each valid (tlb[v] = 1) tlb entry are combined to form a set of matching tlb address (tas): ta tlb ts || tlb tid || tlb epn || 12 0 each ta is compared to all vas under a mask based on the page size (tlb[size]) of the tlb entry. the mask of the comparison of the ea and epn portions of the virtual and translation addresses is computed as follows: mask ~(1024 << (2 * tlb size )) - 1) where the number of bits in the mask is equal to the number of bits in a ta (or va). if a ta matches any va the tlb entry is said to match. if more than one ta/va match occurs, it is considered a serious programming error and the results are undefined. the recommended behavior is that a machine check interrupt is taken. once a match occurs the matching tlb is used for access control, storage attributes, and effective to real address translation. access control, storage attributes, and address translation are defined by book e (additional storage attributes are defined within this document). 5.4.7 address transl ation and the st eis translating an effective address to a real address is defined by book e to require four elements: the address space value. depending on the ty pe of translation (instruction or data), msr[is] or msr[ds] is used. the tlb entries in the tlb arrays the effective address being translated the following subsections describe these elements as they are further defined by the eis. match criteria for tlb entries tlb arrays contain tlb entries that are used to match any address presented for translation. all tlb entries for any given implementation are candidates for any given translation. the tlb itself is unordered with respect to the various elements used in address translations, and regardless of implementation, should be considered to perform the translation comparison wit h all entries in parallel. there should be only one valid matching translation for a given effective address, pid value, and address space value. if the tlb contains more than one matching entry, it is considered a programming error, and the behavior of any such translation is undefined. in this case, the processor is likely to enter checkstop state or take a machine check interrupt. storage architecture RM0004 311/1176 the following fields are compared in the tlb entries: v?the matching entry must have the v bit set. ts?the address space identifier used for translation. the appropriate bit of msr[is] or msr[ds] must match the ts bit for a matching entry. tid?the contents of a pid register must match the tid field of a matching entry, or the tid field must be all zeros for a matching entry. epn?the appropriate number of bits (depending on the page size) of the effective address being translated is compared to the epn field of the tlb entry. if a match occurs on all the fields listed above, the physical address is formed by replacing the effective page number in the effective address with the value in the rpn field of the matching tlb entry. the number of bits in the page number depends on the page size for that tlb entry. translation algorithms the following algorithm describes how translation operates at the st book e level: ea = effective address if translation is an instruction address then as = msr[is] else // data address translation as = msr[ds] for all tlb entries if ! tlb v then next // compare next tlb entry if as != tlb ts then next if tlb tid == 0 then goto pid_match for all pid registers if this pid register == tlb tid then goto pid_match endfor next // no pids matched pid_match: // translation match mask = ~((1024 << (2 * tlb tsize )) - 01) if (ea & mask) != tlb epn then next // no address match real address = tlb rpn | (ea & ~mask) // real address computed end translation -- success endfor end translation -- tlbmiss the algorithm for the granting of permission is as follows: if msr pr == 0 then x = tlb sx r = tlb sr w = tlb sw else x = tlb ux r = tlb ur RM0004 storage architecture 312/1176 w = tlb uw if instruction fetch address then if x == 0 then instruction storage interrupt else // data access if data read (load) then if r == 0 then data storage interrupt else // write access (store) if w == 0 then data storage interrupt access control if address translation results in a match (hit), the matching tlb entry is used to perform access control (permission checks). these checks are based on the privilege level of the access (msr[pr]) and the type of access (fetch for execute, read for loads, and write for stores). the tlb entry?s permission bits (tlb[us,sx,uw,sw,ur,sr]) determine if the operation should succeed. if permission is denied, execution of the instruction is suppressed and an instruction storage interrupt or data storage interrupt occurs as defined in book e. software uses the esr, srr0, and the dear to determine the type of operation attempted and then must perform a tlb search if updating the tlb is desired. the algorithm for determining a ccess control is as follows: if msr pr = 0 then x tlb sx r tlb sr w tlb sw else x tlb ux r tlb ur w tlb uw if instruction_fetch & x = 0 then take instruction storage interrupt else if load & r = 0 then take data storage interrupt else if store & w = 0 then take data storage interrupt else access permitted physical (real) address generation if permission checking is successful, the real address is formed by combining the tlb[rpn] with the lower order offset bits of the ea based on the page size of the tlb entry. mask ~(1024 << (2 * tlb size )) - 1) real_address ((tlb rpn << 12) & mask) | (ea & ~mask) storage architecture RM0004 313/1176 where mask contains the same number of bits as a real address. the real address is then used to access the memory subsystem using the tlb[acm,vle,w,i,m,g,e] fields from the tlb entry to determine how the location should be accessed. page size and effective address bits compared the page size defined for a tlb entry determines how many bits of the effective address are compared with the corresponding epn field in the tlb entry as shown in ta b l e 1 8 5 . permission attribute comparison as part of the translation process, the selected tlb entry provides the access permission bits (ux, sx, uw, sw, ur, sr), and memory/cache attributes (u0, u1, u2, u3, w, i, m, g, and e) for the access. these bits specify whether or not the access is allowed and how the access is to be performed. if a matching tlb entry has been identified, book e provides an access permission mechanism that selectively grants shared access, grants execute access, grants read access, grants write access, and prohibits access to areas of memory based on a number of criteria. book e defines the permissi on bits in tlb entries as follows: sr?supervisor read permission sw?supervisor write permission sx?supervisor execute permission ur?user read permission uw?user write permission ux?user execute permission if the virtual address translation comparison with tlb entries was successful, the permission bits for the matching entry are checked as shown in figure 21 . if the access is not allowed by the access permission mechanism, the processor generates an instruction or data storage interrupt (isi or dsi). table 185. page size and epn field comparison size field page size (4 size kbytes) ea to epn comparison (bits 32?53; 2 size) 0b0000 1 kbyte ea[32?53] = ? epn[32?53] 0b0001 4 kbyte ea[32?51] = ? epn[32?51] 0b0010 16 kbyte ea[32?49] = ? epn[0?49] 0b0011 64 kbyte ea[32?47] = ? epn[32?47] 0b0100 256 kbyte ea[32?45] = ? epn[32?45] 0b0101 1 mbyte ea[32?43] = ? epn[32?43] 0b0110 4 mbyte ea[32?41] = ? epn[32?41] 0b0111 16 mbyte ea[32?39] = ? epn[32?39] 0b1000 64 mbyte ea[32?37] = ? epn[32?37] 0b1001 256 mbyte ea[32?35] = ? epn[32?35] 0b1010 1 gbyte ea[32?33] = ? epn[32?33] RM0004 storage architecture 314/1176 figure 21. granting of access permission the permission attributes defined by book e are defined in detail in chapter 5.4.8 .? page size and real address generation if no virtual address match occurs, the translation fails and a tlb miss exception occurs. depending on the access type (instruction or data address), either the instruction tlb error interrupt or the data tlb error interrupt is taken. otherwise, the real page number (rpn) field of the matching tlb entry provides the translation for the effective address of the access. based on the setting of the size field of the matching tlb entry, the rpn field replaces the corresponding most-significant n bits of the effective address where n = 32 - log 2 (page size). note that the untranslated bits must be zero in the rpn field. table 186. real address generation size field page size (4 size kbytes) rpn bits required to be equal to 0 real address 0b0000 1 kbyte none rpn[32?53] || ea[54?63] 0b0001 4 kbyte rpn[52?53] = 0 rpn[32?51] || ea[52?63] 0b0010 16 kbyte rpn[50?53] = 0 rpn[32?49] || ea[50?63] 0b0011 64 kbyte rpn[48?53] = 0 rpn[32?47] || ea[48?63] 0b0100 256 kbyte rpn[46?53] = 0 rpn[32?45] || ea[46?63] 0b0101 1 mbyte rpn[44?53] = 0 rpn[32?43] || ea[44?63] 0b0110 4 mbyte rpn[42?53] = 0 rpn[32?41] || ea[42?63] 0b0111 16 mbyte rpn[40?53] = 0 rpn[32?39] || ea[40?63] 0b1000 64 mbyte rpn[38?53] = 0 rpn[32?37] || ea[38?63] 0b1001 256 mbyte rpn[36?53] = 0 rpn[32?35] || ea[36?63] 0b1010 1 gbyte rpn[34?53] = 0 rpn[32?33] || ea[34?63] access instruction fetch msr[pr] tlb_entry[ux] tlb_entry[sx] load-class data access tlb_entry[ur] tlb_entry[sr] store-class data access tlb_entry[uw] tlb_entry[sw] tlb match (see figure 19 ) granted storage architecture RM0004 315/1176 5.4.8 permission attributes the permission attributes defined in book e are shown in ta b l e 1 8 7 and described in the following subsections. execute access permission the ux and sx bits of the tlb entry control execute access to the corresponding page. instructions may be fetched and executed from a page in memory if msr[pr] = 1 (user mode) if the ux access control bit for that page is set. if the ux access control bit is cleared, instructions from that page are not fetched and they are not placed into any cache while the processor is in user mode. instructions may be fetched and executed from a page in memory if msr[pr] = 0 (supervisor mode) and the sx acce ss control bit for that page is set. if the sx access control bit is cleared, instructions from that page are not fetched and are not placed into any cache while the processor is in supervisor mode. if the sequential execution model calls for the execution of an instruction from a page that is not enabled for execution (that is, ux = 0 when msr[pr] = 1 or sx = 0 when msr[pr] = 0), an execute access control exception-type instruction storage interrupt (isi) is taken. read access permission the ur and sr bits of the tlb entry control read access to the corresponding page. load operations (including load-class cache management instructions) are permitted from a page in memory while the processor is in us er mode (msr[pr] = 1) if the ur access control bit for that page is set. if the ur access control bit is cleared, execution of the load instruction is suppressed and a read access control exception-type data storage interrupt (dsi) is taken. similarly, load operations (including load-class cache management instructions) are permitted from a page in memory if msr[pr] = 0 (supervisor mode) and the sr access control bit for that page is set. if the sr access control bit is cleared, execution of the load instruction is suppressed and a read access control exception-type data storage interrupt (dsi) is taken. write access permission the uw and sw bits of the tlb entry control write access to the corresponding page. table 187. permission control for instruction, data read, and data write accesses access type msr[pr] tlb[ux] tlb[sx] tlb[ur] tlb[sr] tlb[uw] tlb[sw] 010101010101 instruction fetch 0??isi ???????? 1isi ?????????? data read (load) 0 ??????dsi ???? 1????dsi ?????? data write (store) 0 ??????????dsi 1 ????????dsi ?? RM0004 storage architecture 316/1176 store operations (including store-class cache management instructions) are permitted to a page in memory if msr[pr] = 1 (user mode) and the uw access control bit for that page is set. if the uw access control bit is cleared, ex ecution of the store instruction is suppressed and a write access control exception-type data storage interrupt (dsi) is taken. similarly, store operations (including st ore-class cache management instructions) are permitted to a page in memory if msr[pr] = 0 (supervisor mode) and the sw access control bit for that page is set. if the sw access control bit is cleared, execution of the store instruction is suppressed and a write access control exception-type data storage interrupt (dsi) is taken. permission control and cache management instructions the dcbi and dcbz instructions are treated as stores because they can change data (or cause loss of data by invalidating a modified line). as such, they both can cause write access control exception-type dsis. the dcba instruction is treated as a store because it can also change data. as such, it can also cause a write access control exception. however, these exceptions do not result in a data storage interrupt and if a permission violation occurs, the instruction execution completes, but the allocate operation is merely cancelled (essentially, a no-op). the icbi instruction is treated as a load with respect to permissions checking. as such, it can cause a read access control exception-type data storage interrupt. the dcbt , dcbtst , and icbt instructions are treated as loads with respect to permissions checking. as such, they can cause read access control exceptions. however, such exceptions do not result in data storage interrupts and if a permission violation occurs, the instruction execution completes, but the oper ation is cancelled (essentially, a no-op). the dcbf and dcbst instructions are treated as loads with respect to permissions checking. flushing or storing a line from the cache is not considered a store because the store has already been performed to update the cache and the dcbf or dcbst instruction is only updating the copy in main memory. like load instructions, these instructions can cause read access control exception-type data storage interrupts. table 188 summarizes exception cases caused by the cache management instructions due to permissions violations. table 188. permission control and cache instructions instruction can cause read perm ission violation exception? can cause write permission violation exception? dcba no yes (1) dcbf ye s n o dcbi no yes dcbst ye s n o dcbt ye s 1 no dcbtst ye s 1 no dcbz no yes icbi ye s n o icbt ye s 1 no storage architecture RM0004 317/1176 permissions control and string instructions when the string length is zero, neither lswx nor stswx can cause data storage interrupts due to permissions violations. use of permissions to maintain page history the book e architecture tlb entry definition does not define bits for maintaining page history information. the u0?u3 bits in the tlb entries can be used by software for storing history information, but implementations may ignore these bits internally. page changed bit status can be implemented in the system software by disabling write permissions to all pages. the first attempt to write to the page results in a data storage interrupt. at this point, system software can record the page changed bit in memory, update the tlb entry permission to allow writes to that page, and return to the user program allowing further writes to the page to proceed without exception. crossing page boundaries care must be taken with single instruction accesses (load/stores) that cross page boundaries. examples are lmw and stmw instructions and misaligned accesses on implementations that support misaligned load/stores. architecturally, each of the parts of the access that cross the natural boundary of the access size (half word, word, double word) are treated separately with respect to exception conditions. additionally, these types of instructions may optionally partially complete. for example, a store word instruction that crosses a page boundary because it is misaligned to the last half word of a page might actually store the first 16 bits because the a ccess was permitted, but produce a dsi or data tlb error exception because the second 16 bits in the next page were not valid or they were protected. an implementation may choose to suppress the first 16-bit store or perform it. 5.4.9 translation lookaside buffer (tlb) arrays the mmu contains up to four tlb arrays, which are on-chip storage areas for holding tlb entries. a tlb entry contains effective-to-physical address mappings for loads, stores, and instruction fetches. a tlb array must co ntain tlb entries that share the same characteristics and contains zero or more tlb entries. each tlb entry has specific fields that can be addressed by the corresponding fields in the mmu assist registers (see chapter 2.12.5: mmu assist registers (mas0?mas7) on page 101 ? ). each implemented tlb array has an associated configuration register (tlb n cfg) describing the size and attributes of the tlb entries in that array. see chapter 2.12.4: tlb configuration registers (tlbncfg) on page 100 .? the architected fields of a tlb entry are described in table 189 . 1. dcba , dcbt , dcbtst , and icbt may cause a read access control exception but does not result in a data storage interrupt (dsi). RM0004 storage architecture 318/1176 5.4.10 tlb management tlb entries are managed by software using the set of mas registers, which are used to move data between software and the tlb entries, to identify tlb entries, and to provide table 189. tlb entry name description v valid bit. a 1-bit entry that specifies whether this tlb entry is valid for translation. (1 = valid). tid translation id. identifies which process id (pid) that this tlb entry is valid for. translation ids are compared with process ids (pids) during translation to identify which tlb entry to use for translating an address. a tid value of 0 is considered global and matches all pid values. ts translation space. identifies which address sp ace that this tlb entry is valid for. the translation space field is compared with msr[is] for instruction accesses and the msr[ds] bit for data accesses. this allows for an efficient change of address space when a transition from user mode to supervisor mode occurs. this is a 1 bit field. size page size. describes the size of the pag e. an implementation is not required to support variable page sizes or any particular page size. if a tlb array does not support variable size pages (that is, tlb n cfg[avail] = 0) then this field is ignored. page sizes range from 4 kbytes to 1 tbyte in powers of 4. eis does not support 1- kbyte page sizes defined in book e. page size encoding is defined by book e. epn effective page number. describes the logica l or effective starting address of the page. the number of bits that are valid (used in translation) depends on the size of the page and if the processor is a 32- or 64-bit implementation. this field is used to compare with the ea being translated to identify which tlb entry to use for translation. for 32- bit implementations, this fi eld is 2 to 20 bits, depending on the page size (size). rpn real page number. describes the physical starting address of the page. the real page number is substituted for the effect ive page number from the address being translated which results in the real address. th is field is 2 to 52 bits depending on the page size and the number of bits of re al address supported by the implementation. wimge storage attributes. describe the characteristics of any memory/fetch accesses to the page and the subsequent treatm ent of those data items with respect to the memory subsystem (caches and bus transactions). the wimge bits are defined by book e. acm alternate coherency mode. optional. an implementation may optionally support additional coherency models. if such c oherency models are provided, they are encoded in this field. acm values ar e implementation dependent. the alternate coherence mode is used only when the m bit (from wimge) is set. vle variable length encoding. optional. if an implementation supports the vle extension, clearing vle causes instruction access to this page to decode and execute as powerpc book e (and eis apus) instructions, and setting vle causes instruction access to this page to decode and execute as vle (and eis apu) instructions. sr,sw,sx, ur,uw,ux permissions. user and supervisor read, write, and execute permission bits. supervisor and user permission bits are defined by book e. u0,u1,u2,u3 user bits. implementation dependent. consult the user?s manual for any implementation usage. it is strongly recommended to leave these as storage associated with a tlb entry to be used by system software. iprot invalidation protection. invalidation prot ection. this entry is protected from all tlb invalidation mechanisms except the ex plicit writing of a 0 to the v bit. storage architecture RM0004 319/1176 default values when translation or protection faults occur. see chapter 2.12.5: mmu assist registers (mas0?mas7) on page 101 .? tlb configuration information information about the configuration for a given tlb implementation is available to system software by reading the contents of the mmu configuration sprs. these sprs describe the architectural version of the mmu, the number of tlb arrays, and the characteristics of each tlb array. mmu architecture version number 1 is defined as these sprs with the field definitions as described in this section. mmu configuration register (mmucfg), implemented by all st book e processors, contains basic information about the mmu architecture for each device. tlb configuration registers (tlb n cfg). implemented by all st book e processors for each of the tlbs specified in mmucfg[ntlbs]. they contain configuration information about each particular tlb. see chapter 2.12.3: mmu configuration register (mmucfg) on page 99 .? the tlb n cfg number assignment is the same as the value in mas0[tlbsel]. for example, tlb0cfg provides configuration information about tlb0, and tlb1cfg provides configuration information about tlb1. see chapter 2.12.4: tlb configuration registers (tlbncfg) on page 100 .? tlb entries the software-visible tlb is su bdivided into zero or more tlb arrays. each array must contain tlb entries that share the same characteristics. each tlb array contains one or more tlb entries. each entry has specific fields that correspond to fields in the seven mmu assist (mas) registers, described in chapter 2.12.5: mmu assist registers (mas0?mas7) on page 101 .? some tlb fields are architected in book e and others are architected in the eis. note that book e architected fields may have restrictions or enhancements imposed by the eis for the book e implementations. the iprot tlb entry, architected by the eis, designates tlb entries as protected from certain kinds of invalidation. tlb invalidation and the iprot field are described further in invalidating tlb entries on page 321 .? reading and writing tlb entries all tlb entries are updated by executing tlbwe instructions. at the time of tlbwe execution, the mmu assist registers (mas0?mas6), a set of sprs defined by the eis, are used to index a specific tlb entry. the mas registers also contain the information that is written to the indexed entry, such that they serve as the ports into the tlbs, as shown in figure 22 . the contents of the mas registers are described in chapter 2.12.5: mmu assist registers (mas0?mas7) on page 101 . RM0004 storage architecture 320/1176 figure 22. tlbs accessed through mas registers and tlb instructions similarly, tlb entries are read by executing tlbre instructions. at the time of tlbre execution, the mas registers are used to index a specific tlb entry and upon completion of the tlbre instruction, the mas registers contain the contents of the indexed tlb entry. to read or write tlb entries, the mas registers are first loaded by system software using mtspr instructions and then the desired tlbre or tlbwe instructions must be executed. note that ra = 0 is a preferred form for tlbsx and that some book e implementations take an illegal instruction except ion program interrupt if ra 0. reading tlb entries tlb entries are read by executing tlbre instructions. at the time of tlbre execution, the mas registers are used to index a specific tlb entry and upon completion of the tlbre , the mas registers contain the contents of the indexed tlb entry. selection of the tlb entry to read is performed by setti ng mas0[tlbsel], mas0[esel] and mas2[epn] to indicate th e entry to read. mas0[tlbsel] selects which tlb the entry should be read from (0 to 3) and mas2[epn] selects the set of entries from which mas0[esel] selects an entry. fo r fully associative tlbs, mas2 [epn] is not required since the value in mas0[esel] fully identifies the tlb entry. valid values for mas0[esel] are from 0 to associativity - 1. the selected tlb entry is then used to update the following fields of the mas registers: v, iprot, tid, ts, tsize, epn, acm, vle, wimge, rpn, u0 ? u3, & permissions. if the tlb array supports nv, it is used to update the nv field in the mas registers, otherwise the contents of nv field are undefined. the update of mas registers as a result of a tlbre instruction is summarized in ta b l e 1 9 1 . no operands are given for the tlbre instruction and the book e defined implementation dependent field should be treated as a reserved field. specifying invalid values for mas0[t lbsel] and mas0[esel] produce boundedly undefined results. writing tlb entries tlb entries are written by executing tlbwe instructions. at the time of tlbwe execution, the mas registers are used to index a specific tlb entry and contain the contents to be written to the indexed tlb entry. upon completion of the tlbwe instruction, the tlb entry contents of the mas registers are written to the indexed tlb entry. tlbwe , tlbre , tlbsx, tlbivax mtspr mfspr gpr gpr tlb0 tlb1 tlb n mas registers storage architecture RM0004 321/1176 selection of the tlb entry to write is pe rformed by setting ma s0[tlbsel], mas0[esel] and mas2[epn] to indicate th e entry to write. mas0[tlbsel] selects which tlb the entry should be written from (0 to 3) and mas2[epn] selects the set of entries from which mas0[esel] selects an entry. fo r fully associative tlbs, mas2[ epn] is not used to identify a tlb entry since the value in mas0[esel] fully identifies the tlb entry. valid values for mas0[esel] are from 0 to associativity minus 1. the selected tlb entry is then written with following fields of the mas registers: v, iprot, tid, ts, tsize, epn, acm, vle, wimge, rpn, u0 ? u3, and permissions. if the tlb array supports nv, it is written with the nv value. the effects of updating the tlb entry are not guaranteed to be visible to the programming model until the completion of a context synchronizing operation. writing a tlb entry that is used by the programming model prior to a context synchronizing operation produces undefined behavior. no operands are given for the tlbwe instruction and the book e defined implementation dependent field should be treated as a reserved field. specifying invalid values for mas0[t lbsel] and mas0[esel] produce boundedly undefined results. note: writing tlb entries should be followed by an isync or an rfi before the new entries are to be used by the programming model. invalidating tlb entries tlb entries may be invalidated by any of the following methods: a tlb entry can be invalidated as the result of a tlbwe instruction that clears mas0[v] in the entry. as a result of a tlbivax instruction or from a received broadcast invalidation resulting from a tlbivax on another processor in an smp system. as a result of a flash invalidate. in both multiprocessor and uniprocessor systems, invalidations can occur on a wider set of tlb entries than intended. this are called generous invalidations that is, a virtual address presented for invalidation may invalidate not only the targeted tlb, but also may invalidate other tlb entries, depending on the implementation. this is because parts of the translation mechanism may not be fully specified to the hardware at invalidate time. this is especially true in smp systems where the invalidation address must be broadcast globally to all processors in the system. hardware may impose other limitations. the architecture ensures that the intended tlb is invalidated, but does not guarantee that it is the only one. a tlb entry invalidated by clearing the v bit of the tlb entry by use of a tlbwe is guaranteed to invalidate only the addressed tlb entry. however, invalidates occurring from tlbivax instructions or from the multiprocessor broadcasts as a result of tlbivax instructions may cause generous invalidates. the architecture provides a method to protect against generous invalidations. this is important, because certain virtual memory regions (most notably, the code memory region that serves as the exception handler for mmu faults) must be properly mapped to for forward progress to occur. if this region does not have a valid mapping, an mmu exception cannot be handled because the first address of the interrupt handler causes another mmu exception. to prevent this, the architecture specifies an iprot bit for tlb entries. setting the mas0[prot] protects the corresponding tlb entry from invalidations resulting from tlbivax instructions, as a result of broadcast invalidation from another processor in an smp RM0004 storage architecture 322/1176 system, or from flash invalidations. tlb entries with the iprot field set can be invalidated only by explicitly writing the tlb entry and specifying a 0 for mas1[v]. note: software note: not all tlb arrays in a given implementation implement the iprot attribute. it is likely that implementations that are suitable for demand page environments implement it for only a single array, while not implementing it for other arrays. software note: operating systems must use great care when using protected (iprot) tlb entries, particularly in smp systems. an sm p system that contains tlb entries on other processors requires a cross-processor interrupt or some other synchronization mechanism to assure that each processor performs the required invalidation by writing its own tlb entries. invalidations using tlbivax: the tlbivax instruction provides a virtual address as a target for invalidation. ea[0?51] are used to find a tlb entry with a matching epn field. the page size of the tlb entry is used to mask the low order bits in the comparison. the comparison is performed only for tlb entries in the specified tlb array, do not have the iprot attribute set (if supported by the tlb array), and are valid. the as bit does not participate in the comparison. the ea specified by the r a and r b operands in the tlbivax instruction contains fields in the lower order bits to augment the invalidation to specific tlb arrays and to flash invalidate those arrays. note that tlb entry invalidations resulting from tlbivax instructions do not invalidate any entry that has iprot = 1 unless the specified tlb array does not support the iprot attribute. the encoding of the ea used by tlbivax is shown in ta b l e 1 9 0 . note: software note: to ensure a tlb entry that is not protected by iprot is invalidated if software does not know which tlb array the entry is in, software should issue a tlbivax instruction targeting each tlb in the implementation with the ea to be invalidated. software note: the preferred form of the tlbivax instruction contains the entire ea in r b and zero in r a. some implementations may take an unimplemented instruction exception if r a is non-zero. ea format for tlbivax ia shown below . ea format for tlbivax table 190 describes ea fields for tlbivax . 0 51 52 58 59 60 61 62 63 ea for tlbivax ea 0:51 ?tlbia? storage architecture RM0004 323/1176 flash invalidations using mmucsr0: all entries in a tlb array may be flash invalidated using the mmucsr0 register. flash invalidation of an array is started when the corresponding flash invalidate bit is set in mmucsr0 (mmucsr0[tlb n _fi]). the flash invalidation is complete when the corresponding flash invalidate bit is cleared by the processor. writing a 0 to a flash invalidate bit in mmucsr0 has no effect. note that tlb entry invalidations resulting from mmucsr0 flash invalidations do not invalidate any entry that has iprot = 1 unless the specified tlb array does not support the iprot attribute. searching tlb entries software may search the mmu by using the tlbsx instruction that is provided by book e. the tlbsx instruction uses pid values and an as value from the mas registers instead of the pid registers and the msr. this allows software to search address spaces that differ from the current address space defined by the pid registers. this is useful for tlb fault handling. to properly execute a search for a tlb, software loads mas5 and mas6 registers with pid and as values to search for. these are mas6[spid0], mas6[spi d1], mas5[spid2], mas5[spid3], mas6 [sas]. software then executes a tlbsx instruction. the search performs the same ta to va comparison described in chapter 5.4.6 ,? except that the pid and as values are taken from the mas registers. if a matching, valid tlb entry is found, the mas register are loaded with the information from that tlb entry as if the tlb entry was read from a tlbre instruction. software can examine the mas1[v] bit to determine if the search was successfu l. successful searches cause the valid bit to be set. ta bl e 1 9 1 summarizes the update of mas registers as a result of a tlbsx instruction. the preferred form of the tlbsx is r a = 0. some implementations may take an unimplemented instruction exception or an illegal instruction exception if r a != 0. tlb replacement hardware assist the architecture provides mechanisms to accelerate software in creating and updating tlb entries when mmu related exceptions occur. this is called tlb replacement hardware assist. hardware updates the mas registers on the occurrence of a data tlb error interrupt or instruction tlb error interrupt. when a tlb error exception (miss) occurs, mas0, mas1, and mas2 are automatically updated using the defaults specified in mas4 as well as the as and epn values table 190. fields for ea format of tlbivax field name comments or function when set 0?51 ea 0:51 the upper bits of the address to invalidate. 52?58 ? reserved, should be cleared. 59?60 tlb selects tlb array for invalidation. 00tlb0 01tlb1 10tlb2 11tlb3 61 ia invalidate all entries in selected tlb array. 62?63 ? reserved, should be cleared. RM0004 storage architecture 324/1176 corresponding to the access that caused the exception. mas6 is updated to set mas6[spid0] to the value of pid0 and mas6 [sas] to the value of msr[ds] or msr[is] depending on the type of access that caused the tlb er ror. in addition, if mas4[tlbseld] identifies a tlb array that supports nv (next victim), mas0[esel] is loaded with a value that hardware believes represents the best tlb entry to victimize to create a new tlb entry and mas0[nv] is updated with the tlb entry index of what hardware believes to be the next victim. thus mas0[esel] identifies the current tlb entry to be re placed, and mas0[nv] points to the next victim. when software writes the tlb entry, mas0[nv] is written to the tlb array. the algorithm used by the hardware to determine which tlb entry should be targeted for replacement is implementation dependent. the automatic update of mas registers sets up all the necessary fields for creating a new tlb entry with the exception of rpn, the u0?u3 attribute bits, and the permission bits. with the exception of the upper 32 bits of rpn and the page attributes (should software desire to specify changes from the default attributes), all remaining fields are located in mas3, requiring only the single mas register manipula tion by software before writing the tlb entry. for isi and dsi related exceptions, the mas registers are not updated. software must explicitly search the tlb to find the appropriate entry. the update of mas registers through tlb replacement hardware assist is summarized in table 191 . table 191. mas register update summary mas field updated value loaded on event tlb error interrupt tlbsx hit tlbsx miss tlbre mas0[tlbsel] mas4[tlbseld] tlb ar ray that hit mas4[tlbseld] ? mas0[esel] if mas4[tlbseld] supports next victim then hardware hint, else undefined number of entry that hit if mas4[tlbseld] supports next victim then hardware hint, else undefined ? mas0[nv] if mas4[tlbseld] supports next victim then next hardware hint, else undefined if mas4[tlbseld] supports next victim then hardware hint, else undefined if mas4[tlbseld] supports next victim then next hardware hint, else undefined if mas4[tlbseld] supports next victim then hardware hint, else undefined mas1[v] 1 1 0 tlb[v] mas1i[prot] 0 tlb[iprot] 0 tlb[iprot] mas1[tid] if pid[mas4[tidseld]] implemented then pid[mas4[tidseld]] else 0 tlb[tid] mas6[spid0] tlb[tid] mas1[ts] msr[is] or msr[ds] tlb[ts] mas6[sas] tlb[ts] mas1[tsize] mas4[tsized] tlb[ size] mas4[tsized] tlb[size] mas2[epn] ea 0:51 tlb[epn] ? tlb[epn] mas2[acm] mas4[acmd] tlb[acm] mas4[acmd] tlb[acm] mas2[vle] mas4[vled] tlb[vle] mas4[vled] tlb[vle] storage architecture RM0004 325/1176 5.4.11 mas registers and exception handling when translation-related exceptions occur, hardware preloads the mas registers with information that the interrupt handler likely needs to handle the fault. for a tlb miss exception, some mas register fields are loaded with default information specified in mas4. system software should set up the default information in mas4 before allowing exceptions. in most cases, system software sets this up once depending on its scheme for handling page faults. this simplifies translation-relate d exception handling. the following subsections detail specific mas register fields and the contents loaded for each exception type. tlb miss exception types the book e architecture defines that a tlb miss exception is caused when a virtual address for an access does not match with that of any on-chip tlb entry. this condition causes one of the following: an instruction tlb error interrupt a data tlb error interrupt instruction tlb error interrupt settings an instruction tlb error interrupt occurs when the virtual address associated with an instruction address (fetch) does not match any valid entry in the tlb (that is, the address for the instruction cannot be translated). in addition to the values automatically written to the mas2[w] mas4[wd] tlb[ w] mas4[wd] tlb[w] mas2[i] mas4[id] tlb[i] mas4[id] tlb[i] mas2[m] mas4[md] tlb[m] mas4[md] tlb[m] mas2[g] mas4[gd] tlb[g] mas4[gd] tlb[g] mas2[e] mas4[ed] tlb[e] mas4[ed] tlb[e] mas3[rpn] 0 tlb[rpn] (bits 32:51) 0tlb[rpn] (bits 32:51) mas3[u0,u1,u 2,u3] ? tlb[u0,u1,u2,u3] ? tlb[u0,u1,u2,u 3] mas3[ux,sx,u w, sw,ur,sr] 0 tlb[ux,sx,uw, sw,ur,sr] 0 tlb[ux,sx,uw, sw,ur,sr] mas4 ? ? ? ? mas5 ? ? ? ? mas6[spid0] pid0 ? ? ? mas6[spid1] ? ? ? ? mas6[sas] msr[is] or msr[ds] ? ? ? mas7[rpn] 0 tlb[rpn] (bits 0?31) 0tlb[rpn] (bits 0?31) table 191. mas register update summary (continued) mas field updated value loaded on event tlb error interrupt tlbsx hit tlbsx miss tlbre RM0004 storage architecture 326/1176 mas registers (described in tlb miss exception mas register settings on page 326 ? ), srr0 contains the address of the instruction that caused the instruction tlb error. this srr0 value is used to identify the ea for handling the exception as well as the address to return to when system software has resolved the exception condition by writing a new tlb entry. data tlb error interrupt settings a data tlb error interrupt occurs when the virtual address associated with a data reference from a load, store, or cache management instruction does not match any valid entry in the tlb (that is, the address of the data item of a load or store instruction cannot be translated). in addition to the values automatically written to the mas registers (described in tlb miss exception mas register settings on page 326 ? ), the effective address of the data access that caused the exception is automatically loaded in the data exception address register (dear). also, srr0 contains the address of the instruction that caused the data tlb error and its value is used to identify the address to retu rn to when system software has resolved the exception condition (by writing a new tlb entry). tlb miss exception mas register settings when either an instruction or data tlb error interrupt occurs, the tlb information and selection fields of the mas registers are loaded with default values from other mas registers to assist in processing the exception. the intention is that the common case of a page fault generally requires only system software to load the rpn (corresponding to the physical address that will be used for th is page), and the access permiss ions and the def aults can be used for the remaining mas fields. the processor may use the next victim (nv) field from the tlb array to select which tlb entry should be used for the new translation. the method used to select the candidate tlb for replacement (the next victim) is implementation-dependent and may vary on different book e implementations. in any case, software is free to choose any tlb entry for the replacement (software can overwr ite the value in mas0[esel]). the eis defines the fields set in the mas registers at exception time for an instruction or data tlb error interrupt as shown in ta bl e 1 9 2 . storage architecture RM0004 327/1176 all other mas register values are unchanged. permissions violation exception types the book e architecture also defines that a pe rmissions violation exception is caused when an effective address for an access matches with a tlb entry but the permission attributes in the matching tlb entry do not allow the access to proceed, as described in chapter 5.4.8 .? this condition causes an instruction storage interrupt (isi) or a data storage interrupt (dsi) instruction storage interrupt settings an instruction storage interrupt occurs when the effective address associated with an instruction address (fetch) matches a valid entry in the tlb but one of the permission bits in the tlb does not allow the instruction fetch. in addition to the values automatically written to the mas registers (described in permissions violation mas register settings on page 328 ? ), srr0 contains the address of the instruction that caused the instruction tlb error and this value is used to identify the effective address for handling the exception as well as the address to return to when system software has resolved the exception condition (by writing a new tlb entry). table 192. mas settings for an instruction or data tlb error interrupt mas field value tlbsel set to value in tlbseld (defaul t). this defines the tlb array to be used for the new tlb entry that will be written. esel may be set to an implementation-dependent value, usually based on the nv field of the array selected by tlbseld, if that tlb supports the nv function. if the selected tlb does not support nv, the value loaded into esel is undefined. nv set to an implementation-dependent value to select which tlb entry to replace on the next tlb miss. the nv field of the tlb array is updated by the value of nv in the mas registers when tlbwe is executed. vset iprot cleared tid set to the contents of the pi d register referenced by tidseld. that is, if tid seld contains the value 1, the contents of pid1 are written to the tid field. ts set to the value of the is or ds bit in the msr at the time of the except ion (that is, the msr that described the context that was running when the exception occurred). tsize set to tsized epn set to the effective page number of the instru ction or data address ca using the exception. the number of bits of the page number is implementa tion-dependent, but should be consistent with the tlb array selected if the tlb has a fixed page size. if the tlb array selected by tlbseld contains variable-sized pages, the value for epn is undefined. wimge and x bits set to corresponding default values in the mas registers rpn cleared permissions sr, ur, uw, sw, ux, sx cleared to 0 (no permissions); note that u0?u3 are unchanged. RM0004 storage architecture 328/1176 data storage interrupt settings a data storage interrupt occurs when the ea associated with a data reference from a load or store instruction matches with a valid entry in the tlb but one of the permission bits in the tlb does not allow the data access. in addition to the values automatically written to the mas registers (described in permissions violation mas register settings on page 328 ? ), the effective address of the data access that caused the exception is contained in the data exception address register (dear). this address is used by system software to identify the address that caused the exception. also, srr0 contains the address of the instruction that caused the data storage interrupt and its value is used to identify the address to return to when system software has resolved the exception condition by writing a new tlb entry. permissions violation mas register settings when either an instruction or data storage interrupt occurs, only the spidx and the sas fields are automatically loaded into the mas registers to assist in processing the interrupt. system software is required to then execute a tlbsx instruction to load the mas registers with the tlb entry associated with the instruction address. system software may then make any desired changes to the tlb entry prior to writing it. ta b l e 1 9 3 describes the fields set in the mas registers at exception time for instruction or data storage interrupts. all other mas register values are unchanged. mas register updates for exceptions, tlbsx, and tlbre table 194 summarizes mas register fields updates from the perspective of the eis as a result of various events. note that the implementations further define how certain mas fields are set on exceptions. table 193. mas settings for permissions violation isi or dsi field setting spid0 set to pid0 spid1 set to pid1 spid2 set to pid2 spid3 set to pid3 sas set to the value of msr[is] (for an inst ruction storage interrupt) or msr[ds] (for a data storage interrupt) at the time of t he exception (that is, the msr that described the context that was running when the exception occurred). storage architecture RM0004 329/1176 table 194. mmu assist register field updates?eis definition mas n bit/field value loaded for each case itlb/dtlb error tlbsx hit tlbsx miss isi dsi tlbre tlbwe tlbsel tlbseld which tlb hit tlbseld ? ? ? ? esel if tlbseld supports nv: tlb0[nv] else, undefined number of entry that hit if tlbseld supports nv: tlb0[nv] else, undefined ?? ? ? nv if tlbseld supports nv: next nv (array) else, undefined if tlbsel supports nv: nv (array) else, undefined if tlbseld supports nv: next nv (array) else, undefined ? ? if tlbsel supports nv: nv (array) else, undefined ? v 1 1 0 ? ? v (array) ? iprot 0 if tlb that hits supports iprot: matched iprot value; else, 0 0 ? ? if tlb that hits supports iprot: matched iprot value; else, 0 ? tid pid n values selected by tidseld tid (array) spid0 ? ? tid(array) ? ts msr[is/ds] sas sas ? ? ts (array) ? tsize[0?3] tsized tsize (array) tsized ? ? tsize (array) ? epn[32?51] if tlbseld has fixed page size: epn of access else, undefined epn (array) ? ? ? epn (array) ? x0, x1 wimge x0d, x1d wimged x0, x1 (array) wimge (array) x0d, x1d wimged ? ? x0, x1 (array) wimge (array) ? rpn[32?51] zeros rpn(array) zeros ? ? rpn (array) ? permis zeros permis (array) zeros ? ? permis (array) ? tlbseld ? ? ? ? ? ? ? tidseld? ?????? tsized ? ? ? ? ? ? ? wimged ? ? ? ? ? ? ? RM0004 instruction set 330/1176 6 instruction set this chapter describes the following instructions: book e instructions defined for 32-bit implementations. this includes instructions not implemented in all book e devices. instructions defined by the eis, except for the instructions defined by the vle extension. full descriptions of these instructions are provided in chapter 13: vle instruction set on page 891 .? 6.1 notation the following definitions and notation are used throughout this chapter in the instruction descriptions. table 195. notation conventions symbol meaning x p bit p of register/field x x field the bits composing a defined field of x. for example, x sign , x exp , and x frac represent the sign, exponent, and fractional value of a floating-point number x x p:q bits p through q of register/field x x p q ... bits p, q,... of register/field x ? x the one?s complement of the contents of x field i bits 4 i through 4 i+3 of a register . as the last character of an instruction m nemonic, this character indicates that the instruction records status information in cert ain fields of the condition register as a side effect of execution, as described in chapter 2.5.1: condition register (cr) on page 61 .? || describes the concatenation of two values. for example, 010 || 111 is the same as 010111. x n x raised to the n th power n x the replication of x, n times (i.e., x concatenated to itself n?1 times). n 0 and n 1 are special cases: n 0 means a field of n bits with each bit equal to 0. thus 5 0 is equivalent to 0b0_0000. n 1 means a field of n bits with each bit equal to 1. thus 5 1 is equivalent to 0b1_1111. /, //, ///, a reserved field in an instruction or in a regist er. each bit and field in instructions, in status and control registers (such as the xer or fpscr), and in sprs is either defined, allocated, or reserved, as described in chapter 3.2.1: classes of instructions on page 135 .? instruction set RM0004 331/1176 6.2 instruction fields table 196 describes instruction fields. table 196. instruction field descriptions field description aa (30) absolute address bit. 0 the immediate field represents an address relative to the current instruction address. for i-form branch instructions the effect ive address of the branch target is the value 32 0 || (cia+exts(li||0b00)) 32?63 . for b-form branch instructions the effect ive address of the branch target is the value 32 0 || (cia+exts(bd||0b00)) 32?63 . for i-form branch extended instructions the effective address of the branch target is the value cia+exts(li||0b00). for b-form branch extended instructions the effective address of the branch target is the value cia+exts(bd||0b00). 1 the immediate field repres ents an absolute address. for i-form branch instructions the effect ive address of the branch target is the value 32 0 || exts(li||0b00) 32?63 . for b-form branch instructions the effect ive address of the branch target is the value 32 0 || exts(bd||0b00) 32?63 . for i-form branch extended instructions the effective address of the branch target is the value exts(li||0b00). for b-form branch extended instructions the effective address of the branch target is the value exts(bd||0b00). crb a (11?15) used to specify a condition register bit to be used as a source crb b (16?20) used to specify a condition register bit to be used as a source cr d (6?8) used to specify a cr or fpscr field to be used as a target cr s (11?13) used to specify a cr or fpscr field to be used as a source bi (11?15) used to specify a condition register bit to be used as the condition of a branch conditional instruction bo (6?10) used to specify options for branch conditional instructions. see branch and flow control instructions on page 163 .? crb d (6?10) used to specify a cr or fpscr bit to be used as a target ct (6?10) used by cache touch instructions ( dcbt , dcbtst , and icbt ) to specify the target portion of the cache facility to place t he prefetched data or instructions and is implementation-dependent d (16?31) immediate field used to specify a 16-bit signed two?s complement integer that is sign-extended to 64 bits dcrn(16?20||11? 15) used to specify a device control register for the mtdcr and mfdcr instructions e (15) immediate field used to specify a 1-bit value used by wrteei to place in msr[ee] (external input enable bit) fm (7?14) field mask used to identify fpscr fiel ds that are to be updated by the mtfsf instruction RM0004 instruction set 332/1176 fr a (11?15) used to specify an fpr to be used as a source fr b (16?20) used to specify an fpr to be used as a source fr c (21?25) used to specify an fpr to be used as a source fr s (6?10) used to specify an fpr to be used as a source fr d (6?10) used to specify an fpr to be used as a target crm (12?19) field mask used to identify the condition register fields to be updated by the mtcrf instruction li (6?29) immediate field specifying a 24-bit signed two?s complement integer that is concatenated on the right with 0b00 and sign-extended to 64 bits lk (31) link bit. indicates whether the link register (lr) is set. 0do not set the lr. 1set the lr. the sum of the value 4 and t he address of the branch instruction is placed into the lr. mb (21?25) and me (26?30) fields used in m-form rotate instructions to specify a 64-bit mask consisting of 1 bits from bit mb+32 through bit me+32 inclusive and 0 bits elsewhere. mo (6?10) used to specify the subset of memory accesses ordered by a memory barrier instruction ( mbar ). nb (16?20) used to specify the number of bytes to move in an immediate move assist instruction opcd (0?5) primary opcode field r a (11?15) used to specify a gpr to be used as a source or as a target r b (16?20) used to specify a gpr to be used as a source rc (31) record bit. 0do not alter the condition register. 1set condition register field 0 or field 1. rs (6?10) used to specify a gpr to be used as a source rd (6?10) used to specify a gpr to be used as a target sh (16?20) used to specify a shift amount in rotate word immediate and shift word immediate instructions simm (16?31) immediate field used to specify a 16-bit signed integer sprn (16?20||11? 15) used to specify an spr for mtspr and mfspr instructions to (6?10) used to specify the conditions on whic h to trap. the encoding is described in table 92: trap instructions on page 170 .? u (16?19) immediate field used as the data to be placed into a field in the fpscr uimm (16?31) immediate field used to specify a 16-bit unsigned integer xo (21?29, 21? 30, 22?30, 26?30, 27?29, 27?30, 28? 31) extended opcode field table 196. instruction field descriptions (continued) field description instruction set RM0004 333/1176 6.3 description of instruction operations the operation of most instructions is described by a series of statements using a semiformal language at the register transfer level (rtl), which uses the general notation given in table 195 and ta bl e 1 9 6 and the rtl-specific conventions in ta b l e 1 9 7 . see the example in figure 23 . some of this notation is used in the formal descriptions of instructions. the rtl descriptions cover the normal execution of the instruction, except that ?standard? setting of the condition register, integer exception register, and floating-point status and control register are not always shown. (non-standard setting of these registers, such as the setting of condition register field 0 by the stwcx. instruction, is shown.) the rtl descriptions do not cover all cases in which e xceptions may occur, or for which the results are boundedly undefined, and may not cover all invalid forms. rtl descriptions specify the architectural transformation performed by the execution of an instruction. they do not imply any particular implementation. table 197. rtl notation notation meaning assignment f assignment in which the data may be reformatted in the target location ? not logical operator (one?s complement) + two?s complement addition ? two?s complement subtraction, unary minus multiplication division (yielding quotient) + dp floating-point addition, double precision ? dp floating-point subtraction, double precision dp floating-point multiplication, double precision dp floating-point division quotient, double precision + sp floating-point addition, single precision ? sp floating-point subtraction, single precision sf signed fractional multiplication. re sult of multiplying two quantities having bit lengths x and y taking the least significant x+y?1 bits of the product and concatenating a 0 to th e least significant bit forming a signed fractional result of x+y bits. si signed integer multiplication sp floating-point multiplication, single precision sp floating-point division, single precision fp floating-point multiplication to infinite precision (no rounding) ui unsigned integer multiplication fpsquareroot- double(x) floating-point , result rounded to double-precision x RM0004 instruction set 334/1176 fpsquareroot- single(x) floating-point , result rounded to single-precision fpreciprocal- estimate(x) floating-point estimate of fpreciprocal-squareroot- estimate(x) floating-point estimate of allocate-datacache- block(x) if the block containing the byte addressed by x does not exist in the data cache, allocate a block in the data cache and set the contents of the block to 0. flush-datacache- block(x) if the block containing the byte addre ssed by x exists in the data cache and is dirty, the block is written to main memory and is removed from the data cache. invalidate-datacache- block(x) if the block containing the byte addressed by x exists in the data cache, the block is removed from the data cache. store-datacache- block(x) if the block containing the byte addressed by x exists the data cache and is dirty, the block is written to main memory but may remain in the data cache. prefetch-datacache- block(x,y) if the block containing the byte addressed by x does not exist in the portion of the data cache specified by y, the block in memory is copied into the data cache. prefetch-forstore- datacache-block(x,y) if the block containing the byte addressed by x does not exist in the portion of the data cache specified by y, the block in memory is copied into the data cache and made exclusive to the processor executing the instruction. zerodatacache- block(x) the contents of the block containing the byte addressed by x in the data cache is cleared. invalidate-instruction- cacheblock(x) if the block containing the byte addressed by x is in the instruction cache, the block is removed from the instruction cache. prefetch-instruction- cacheblock(x,y) if the block containing the byte addressed by x does not exist in the portion of the instruction cache specified by y, the block in memory is copied into the instruction cache. =, equals, not equals relations <, , >, signed comparison relations < u , > u unsigned comparison relations ? unordered comparison relation &, | and, or logical operators , exclusive or, equivalence logical operators ((a b) = (a ? b)) >>, << shift right or left logical abs(x) absolute value of x apid(x) returns an implementation-dependen t information on the presence and status of the auxiliary proce ssing extensions specified by x ceil(x) least integer x table 197. rtl notation (continued) notation meaning x 1 x -- - 1 x ------ - instruction set RM0004 335/1176 dcreg(x) device control register x double(x) result of converting x from floating- point single format to floating-point double format exts(x) result of extending x on the left with signed bits extz(x) result of extending x on the left with zeros fpr(x) floating-point register x gpr(x) general-purpose register x mask(x, y) mask having 1s in bit positions x through y (wrapping if x>y) and 0s elsewhere mem(x,1) contents of the byte of memory located at address x mem(x,y) (for y={2,4,8}) contents of y bytes of memory starting at address x. if big-endian memory, the byte at address x is the msb and the byte at address x+y?1 is the lsb of the value being accessed. if little-endian memory, the byte at address x is the lsb and the byte at address x+y?1 is the msb of the value being accessed. mod(x,y) modulo y of x (rema inder of x divided by y) rotl32(x, y) result of rotating the value x left y positions, where x is 32 bits long single(x) result of converting x from floating- point double format to floating-point single format spreg(x) special-purpose register x trap invoke a trap-type program interrupt characterization reference to the setting of status bits in a standard way that is explained in the text undefined an undefined value. the value may vary between implementations and between different executions on the same implementation. cia current instruction address, the address of the instruction being described in rtl. used by relative branches to set the next instruction address (nia) and by branch instructions with lk=1 to set the lr. cia does not correspond to any architected register. nia next instruction address, the addre ss of the next instruction to be executed. for a successful branch, th e next instruction address is the branch target address: in rtl, this is indicated by assigning a value to nia. for other instructions that cause non-sequential instruction fetching, the rtl is similar. for instructions that do not branch, and do not otherwise cause instruction fetc hing to be non-sequential, the next instruction address is cia+4. nia does not correspond to any architected register. if ? then ? else ? conditional execution, indenting shows range; else is optional table 197. rtl notation (continued) notation meaning RM0004 instruction set 336/1176 precedence rules for rtl operators are summarized in ta b l e 1 9 8 . operators higher in the table are applied before those lower in the table. operators at the same level in the table associate from left to right, from right to left, or not at all, as shown. (for example, ? associates from left to right, so a?b?c = (a?b)?c.) parentheses are used to override the evaluation order implied by the table or to increase clarity; parenthesized expressions are evaluated before serving as operands. 6.3.1 spe apu saturati on and bit-reverse models for saturation and bit reversal, the pseudo rtl is provided here to more accurately describe those functions that are referenced in the instruction pseudo rtl. saturation saturate(overflow, carry, saturated_underflow, saturated_overflow, value) if overflow then if carry then return saturated_underflow else return saturated_overflow else return value do do loop, indenting shows range. ?to? and/or ?by? clauses specify incrementing an iteration variable, and a ?while? clause gives termination conditions. leave leave innermost do loop, or do loop described in leave statement. table 198. operator precedence operators associativity subscript, function evaluation left to right pre-superscript (replication), post-superscript (exponentiation) right to left unary ?, ? right to left , left to right +, ? left to right || left to right =, , <, , >, , < u , > u , ? left to right &, , left to right | left to right : (range) none none table 197. rtl notation (continued) notation meaning instruction set RM0004 337/1176 bit reverse bitreverse(value) result 0 mask 1 shift 31 cnt 32 while cnt > 0 then do t data & mask if shift >= 0 then result ( t << shift) | result else result ( t >> -shift) | result cnt cnt - 1 shift shift - 2 mask mask << 1 return result 6.3.2 embedded floating- point conversion models the embedded floati ng-point instructions defined by the signal processing engine (spe) apu and the single-precision floating-point (spf p) apus contain floating-point conversion to and from integer and fractional type instructions. the floating-point to-and-from non? floating-point conversion model pseudo rtl is provided here as a group of functions that is called from the individual instruction pseudo rtl descriptions. table 199. conversion models function name reference common functions round a 32-bit value round32(fp,guard,sticky) on page 339 round a 64-bit value round64(fp,guard,sticky) chapter signal floating-point error signalfperror on page 339 is a 32-bit value a nan or infinity? isa32nanorinfinity(fp) on page 339 floating-point conversions convert from single-precision floating-point to integer word with saturation cnvtfp32toi32sat(fp,signed,upper_lower,rou nd,fractional) on page 351 convert from double-precision floating-point to integer word with saturation cnvtfp64toi32sat(fp,si gned,round,fractional) on page 353 convert from double-precision floating-point to integer double word with saturation cnvtfp64toi64sat(fp,signed,round) on page 355 convert to single-precision floating- point from integer word with saturation cnvti32tofp32sat(v,signed,upper_lower,fracti onal) on page 356 RM0004 instruction set 338/1176 convert to double-precision floating- point from integer double word with saturation cnvti64tofp64sat(v,signed) on page 358 integer saturate integer saturate saturate(ovf,carry,neg_sat,pos_sat,value) chapter table 199. conversion models function name reference instruction set RM0004 339/1176 common embedded float ing-point functions this section includes common functions used by the functions in subsequent sections. 32-bit nan or infinity test // determine if fp value is a nan or infinity isa32nanorinfinity(fp) return (fp exp = 255) isa32nan(fp) return ((fp exp = 255) & (fp frac 0)) isa32infinity(fp) return ((fp exp = 255) & (fp frac = 0)) // determine if fp value is denormalized isa32denorm(fp) return ((fp exp = 0) & (fp frac 0)) // determine if fp value is a nan or infinity isa64nanorinfinity(fp) return (fp exp = 2047) isa64nan(fp) return ((fp exp = 2047) & (fp frac 0)) isa64infinity(fp) return ((fp exp = 2047) & (fp frac = 0)) // determine if fp value is denormalized isa64denorm(fp) return ((fp exp = 0) & (fp frac 0)) signal floating-point error // signal a floating-point error in the spefscr signalfperror(upper_lower, bits) if (upper_lower = upper) then bits bits << 15 spefscr spefscr | bits bits (fg | fx) if (upper_lower = upper) then bits bits << 15 spefscr spefscr & ? bits round a 32-bit value // round a result round32(fp, guard, sticky) fp32format fp; if (spefscr finxe = 0) then if (spefscr frmc = 0b00) then // nearest if (guard) then if (sticky | fp frac[22] ) then v[0:23] fp frac + 1 if v[0] then if (fp exp >= 254) then // overflow fp fp sign || 0b11111110 || 23 1 else RM0004 instruction set 340/1176 fp exp fp exp + 1 fp frac v 1:23 else fp frac v[1:23] else if ((spefscr frmc & 0b10) = 0b10) then // infinity modes // implementation dependent return fp round a 64-bit value // round a result round64(fp, guard, sticky) fp32format fp; if (spefscr finxe = 0) then if (spefscr frmc = 0b00) then // nearest if (guard) then if (sticky | fp frac[51] ) then v[0:52] fp frac + 1 if v[0] then if (fp exp >= 2046) then // overflow fp fp sign || 0b11111111110 || 52 1 else fp exp fp exp + 1 fp frac v 1:52 else fp frac v 1:52 else if ((spefscr frmc & 0b10) = 0b10) then // infinity modes // implementation dependent return fp convert from single-precision fl oating-point to integer word with saturation // convert 32-bit floating point to integer/factional // signed = sign or unsign // upper_lower = upper or lower // round = round or trunc // fractional = f (fractional) or i (integer) cnvtfp32toi32sat(fp, signed, upper_lower, round, fractional) fp32format fp; if (isa32nanorinfinity(fp)) then // snan, qnan, +-inf signalfperror(upper_lower, finv) if (isa32na n(fp)) then return 0x00000000 // all nans if (signed = sign) then if (fp sign = 1) then return 0x80000000 else return 0x7fffffff else instruction set RM0004 341/1176 if (fp sign = 1) then return 0x00000000 else return 0xffffffff if (isa32denorm(fp)) then signalfperror(upper_lower, finv) return 0x00000000 // regardless of sign if ((signed = unsign) & (fp sign = 1)) then signalfperror(upper_lower, fovf) // overflow return 0x00000000 if ((fp exp = 0) & (fp frac = 0)) then return 0x00000000 // all zero values if (fractional = i) then // convert to integer max_exp 158 shift 158 - fp exp if (signed = sign) then if ((fp exp 158) | (fp frac 0) | (fp sign 1)) then max_exp max_exp - 1 else // fractional conversion max_exp 126 shift 126 - fp exp if (signed = sign) then shift shift + 1 if (fp exp > max_exp) then signalfperror(upper_lower, fovf) // overflow if (signed = sign) then if (fp sign = 1) then return 0x80000000 else return 0x7fffffff else return 0xffffffff result 0b1 || fp frac || 0b00000000 // add u to frac guard 0 sticky 0 for (n 0; n < shift; n n + 1) do sticky sticky | guard guard result & 0x00000001 result result > 1 // report sticky and guard bits if (upper_lower = upper) then spefscr fgh guard spefscr fxh sticky else spefscr fg guard spefscr fx sticky RM0004 instruction set 342/1176 if (guard | sticky) then spefscr finxs 1 // round the integer result if ((round = round) & (spefscr finxe = 0)) then if (spefscr frmc = 0b00) then // nearest if (guard) then if (sticky | (result & 0x00000001)) then result result + 1 else if ((spefscr frmc & 0b10) = 0b10) then // infinity modes // implementation dependent if (signed = sign) then if (fp sign = 1) then result ? result + 1 return result convert from double-precision fl oating-point to integer word with saturation // convert 64-bit floating point to integer/fractional // signed = sign or unsign // round = round or trunc // fractional = f (fractional) or i (integer) cnvtfp64toi32sat(fp, signed, round, fractional) fp64format fp; if (isa64nanorinfinity(fp)) then // snan, qnan, +-inf signalfperror(lower, finv) if (isa64na n(fp)) then return 0x00000000 // all nans if (signed = sign) then if (fp sign = 1) then return 0x80000000 else return 0x7fffffff else if (fp sign = 1) then return 0x00000000 else return 0xffffffff if (isa64denorm(fp)) then signalfperror(lower, finv) return 0x00000000 // regardless of sign if ((signed = unsign) & (fp sign = 1)) then signalfperror(lower, fovf) // overflow return 0x00000000 if ((fp exp = 0) & (fp frac = 0)) then return 0x00000000 // all zero values instruction set RM0004 343/1176 if (fractional = i) then // convert to integer max_exp 1054 shift 1054 - fp exp if (signed sign) then if ((fp exp 1054) | (fp frac 0) | (fp sign 1)) then max_exp max_exp - 1 else // fractional conversion max_exp 1022 shift 1022 - fp exp if (signed = sign) then shift shift + 1 if (fp exp > max_exp) then signalfperror(lower, fovf) // overflow if (signed = sign) then if (fp sign = 1) then return 0x80000000 else return 0x7fffffff else return 0xffffffff result 0b1 || fp frac[0:30] // add u to frac guard fp frac[31] sticky (fp frac[32:63] 0) for (n 0; n < shift; n n + 1) do sticky sticky | guard guard result & 0x00000001 result result > 1 // report sticky and guard bits spefscr fg guard spefscr fx sticky if (guard | sticky) then spefscr finxs 1 // round the result if ((round = round) & (spefscr finxe = 0)) then if (spefscr frmc = 0b00) then // nearest if (guard) then if (sticky | (result & 0x00000001)) then result result + 1 else if ((spefscr frmc & 0b10) = 0b10) then // infinity modes // implementation dependent if (signed = sign) then if (fp sign = 1) then result ? result + 1 return result RM0004 instruction set 344/1176 convert from double-precision fl oating-point to integer double word with saturation // convert 64-bit floating point to integer/fractional // signed = sign or unsign // round = round or trunc cnvtfp64toi64sat(fp, signed, round) fp64format fp; if (isa64nanorinfinity(fp)) then // snan, qnan, +-inf signalfperror(lower, finv) if (isa64na n(fp)) then return 0x00000000_00000000 // all nans if (signed = sign) then if (fp sign = 1) then return 0x80000000_00000000 else return 0x7fffffff_ffffffff else if (fp sign = 1) then return 0x00000000_00000000 else return 0xffffffff_ffffffff if (isa64denorm(fp)) then signalfperror(lower, finv) return 0x00000000_00000000 // regardless of sign if ((signed = unsign) & (fp sign = 1)) then signalfperror(lower, fovf) // overflow return 0x00000000_00000000 if ((fp exp = 0) & (fp frac = 0)) then return 0x00000000_00000000 // all zero values max_exp 1086 shift 1086 - fp exp if (signed = sign) then if ((fp exp 1086) | (fp frac 0) | (fp sign 1)) then max_exp max_exp - 1 if (fp exp > max_exp) then signalfperror(lower, fovf) // overflow if (signed = sign) then if (fp sign = 1) then return 0x80000000_00000000 else return 0x7fffffff_ffffffff else return 0xffffffff_ffffffff result 0b1 || fp frac || 0b00000000000 // add u to frac guard 0 sticky 0 for (n 0; n < shift; n n + 1) do instruction set RM0004 345/1176 sticky sticky | guard guard result & 0x00000000_00000001 result result > 1 // report sticky and guard bits spefscr fg guard spefscr fx sticky if (guard | sticky) then spefscr finxs 1 // round the result if ((round = round) & (spefscr finxe = 0)) then if (spefscr frmc = 0b00) then // nearest if (guard) then if (sticky | (result & 0x00000000_00000001)) then result result + 1 else if ((spefscr frmc & 0b10) = 0b10) then // infinity modes // implementation dependent if (signed = sign) then if (fp sign = 1) then result ? result + 1 return result convert to single-precision float ing-point from integer word with saturation // convert from integer/factional to 32-bit floating point // signed = sign or unsign // upper_lower = upper or lower // fractional = f (fractional) or i (integer) cnvti32tofp32sat(v, signed, upper_lower, fractional) fp32format result; result sign 0 if (v = 0) then result 0 if (upper_lower = upper) then spefscr fgh 0 spefscr fxh 0 else spefscr fg 0 spefscr fx 0 else if (signed = sign) then if (v 0 = 1) then v ? v + 1 result sign 1 if (fractional = f) then // fractional bit pos alignment maxexp 127 if (signed = unsign) then RM0004 instruction set 346/1176 maxexp maxexp - 1 else maxexp 158 // integer bit pos alignment sc 0 while (v 0 = 0) v v << 1 sc sc + 1 v 0 0 // clear u bit result exp maxexp - sc guard v 24 sticky (v 25:31 0) // report sticky and guard bits if (upper_lower = upper) then spefscr fgh guard spefscr fxh sticky else spefscr fg guard spefscr fx sticky if (guard | sticky) then spefscr finxs 1 // round the result result frac v 1:23 result round32(result, guard, sticky) return result convert to double-precision floa ting-point from integer word with saturation // convert from integer/factional to 64-bit floating point // signed = sign or unsign // fractional = f (fractional) or i (integer) cnvti32tofp64sat(v, signed, fractional) fp64format result; result sign 0 if (v = 0) then result 0 spefscr fg 0 spefscr fx 0 else if (signed = sign) then if (v[0] = 1) then v ? v + 1 result sign 1 if (fractional = f) then // fractional bit pos alignment maxexp 1023 if (signed = unsign) then maxexp maxexp - 1 instruction set RM0004 347/1176 else maxexp 1054 // integer bit pos alignment sc 0 while (v 0 = 0) v v << 1 sc sc + 1 v 0 0 // clear u bit result exp maxexp - sc // report sticky and guard bits spefscr fg 0 spefscr fx 0 result frac v 1:31 || 21 0 return result convert to double-precision floati ng-point from integer double word with saturation // convert from 64 integer to 64-bit floating point // signed = sign or unsign cnvti64tofp64sat(v, signed) fp64format result; result sign 0 if (v = 0) then result 0 spefscr fg 0 spefscr fx 0 else if (signed = sign) then if (v 0 = 1) then v ? v + 1 result sign 1 maxexp 1054 sc 0 while (v 0 = 0) v v << 1 sc sc + 1 v 0 0 // clear u bit result exp maxexp - sc guard v 53 sticky (v 54:63 0) // report sticky and guard bits spefscr fg guard spefscr fx sticky if (guard | sticky) then spefscr finxs 1 RM0004 instruction set 348/1176 // round the result result frac v 1:52 result round64(result, guard, sticky) return result 6.3.3 integer saturation models // saturate after addition saturate(ovf, carry, neg_sat, pos_sat, value) if ovf then if carry then return neg_sat else return pos_sat else return value 6.3.4 embedded floating-point results appendix e: embedded floating-point results on page 1156 ,? summarizes results of various types of spe and spfp floating-point operations on various combinations of input operands. 6.4 instruction set the rest of this chapter describes individual instructions, which are listed in alphabetical order by mnemonic. figure 23 shows the format for instruction description pages. instruction set RM0004 349/1176 figure 23. instruction description note: the execution unit that executes the instruction may not be the same for all processors. add add add add r d ,r a ,r b (oe=0, rc=0) add. r d ,r a ,r b (oe=0, rc=1) addo r d ,r a ,r b (oe=1, rc=0) addo. r d ,r a ,r b (oe=1, rc=1) carry 0?63 carry(ra + rb) sum 0?63 ra + rb if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32?63 < 0 gt sum 32?63 > 0 eq sum 32?63 = 0 cr0 lt || gt || eq || so rd sum the sum of the contents of r a and r b is placed into r d. other registers altered: ? cr0 (if rc=1) so ov (if oe=1) 0 5 6 1011 1516 2021 3031 011111 rd ra rb oe 100001010rc book e user instruction mnemonic instruction name instruction syntax instruction encoding rtl description of text description of registers altered by instruction operation instruction operation user/supervisor access architecture key: instruction RM0004 instruction set 350/1176 add add add add r d ,r a ,r b(oe=0, rc=0) add. r d ,r a ,r b(oe=0, rc=1) addo r d ,r a ,r b(oe=1, rc=0) addo. r d ,r a ,r b(oe=1, rc=1) carry 0:63 carry(ra + rb) sum 0:63 ra + rb if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum carry 0:63 carry(ra + rb) sum 0:63 ra + rb if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum the sum of the contents of r a and r b is placed into r d. other registers altered: cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b oe100001010rc instruction set RM0004 351/1176 _add x _add x add se_add ? r x ,r y sum 32:63 gpr(rx) + gpr(ry) gpr(rx) sum 32:63 the sum of the contents of gpr( r x) and the contents of gpr( r y) is placed into gpr( r x). special registers altered: none 056101115 000001 0 0 ry rx vle user RM0004 instruction set 352/1176 addc addc add carrying addc r d ,r a ,r b(oe=0, rc=0) addc. r d ,r a ,r b(oe=0, rc=1) addco r d ,r a ,r b(oe=1, rc=0) addco. r d ,r a ,r b(oe=1, rc=1) carry 0:63 carry(ra + rb) sum 0:63 ra + rb if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 the sum of the contents of r a and r b is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b oe000001010rc instruction set RM0004 353/1176 adde adde add extended adde r d ,r a ,r b(oe=0, rc=0) adde. r d ,r a ,r b(oe=0, rc=1) addeo r d ,r a ,r b(oe=1, rc=0) addeo. r d ,r a ,r b(oe=1, rc=1) if e=0 then cin ca carry 0:63 carry(ra + rb + cin) sum 0:63 ra + rb + cin if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 for adde [ o ][ . ], the sum of the contents of r a, the contents of r b, and ca is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b oe010001010rc RM0004 instruction set 354/1176 addi addi add immediate [shifted] addi r d ,r a , simm (s=0) addis r d ,r a , simm (s=1) if ra=0 then a 64 0 else a ra if s=0 then b exts(simm) if s=1 then b exts(simm || 16 0) rd a + b if addi and r a=0, the sign-extended value of the simm field is placed into r d. if addi and r a 0, the sum of the contents of r a and the sign-extended value of field simm is placed into r d. if addis and r a=0, the sign-extended value of the simm field, concatenated with 16 zeros, is placed into r d. if addis and r a 0, the sum of the contents of r a and the sign-extended value of the simm field concatenated with 16 zeros, is placed into r d. other registers altered: none book e user 0 4 5 6 10 11 15 16 31 00111s rd ra simm instruction set RM0004 355/1176 _addi x _addi x add [2 operand] immediate [shifted] [and record] e_add16i r d ,r a , si a gpr(ra) b exts(si) gpr(rd) a + b the sum of the contents of gpr( r a) and the sign-extended value of field si is placed into gpr( r d). special registers altered: none e_add2i. r a , si si si 0:4 || si 5:15 sum 32:63 gpr(ra) + exts(si) lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(ra) sum 32:63 the sum of the contents of gpr( r a) and the sign-extended value of si is placed into gpr( r a). special registers altered: cr0 e_add2is r a , si si si 0:4 || si 5:15 sum 32:63 gpr(rd) + (si || 16 0) gpr(ra) sum 32:63 the sum of the contents of gpr( r a) and the value of si concatenated with 16 zeros is placed into gpr( r aarav2006). special registers altered: none e_addi r d ,r a , sci8 (rc = 0) e_addi. r d ,r a , sci8 (rc = 1) vle user 0 5 6 1011 1516 31 000111 rd ra si 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0001 si 5:15 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0010 si 5:15 0 5 6 1011 1516 2021222324 31 000110 rd ra 1000rcf scl ui8 RM0004 instruction set 356/1176 imm sci8(f,scl,ui8) sum 32:63 gpr(ra) + imm if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rd) sum 32:63 the sum of the contents of gpr( r a) and the value of sci8 is placed into gpr( r d). special registers altered: cr0 (if rc = 1) se_addi r x , oimm gpr(rx) gpr(rx) + ( 27 0 || offset(oim5)) the sum of the contents of gpr( r x) and the zero-extended offset value of oim5 (a final value in the range 1?32), is placed into gpr( r x). special registers altered: none 0 5 6 7 11 12 15 0010000 oim5 (1) 1. oimm = oim5 +1 rx instruction set RM0004 357/1176 addic addic add immediate carrying [and record] addic r d ,r a , simm (rc=0) addic. r d ,r a , simm (rc=1) carry 0:63 carry(ra + exts(simm)) sum 0:63 ra + exts(simm) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd ra+exts(simm) ca carry 32 the sum of the contents of r a and the sign-extended value of the simm field is placed into r d. other registers altered: ca cr0 (if rc=1) book e user 0 4 5 6 10 11 15 16 31 00110rc r d r asimm RM0004 instruction set 358/1176 _ addic x _addic x add immediate carrying [and record] e_addic r d ,r a , sci8 (rc = 0) e_addic. r d ,r a , sci8 (rc = 1) imm sci8(f,scl,ui8) carry 32:63 carry(gpr(ra) + imm) sum 32:63 gpr(ra) + imm if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rd) sum 32:63 ca carry 32 the sum of the contents of gpr( r a) and the value of sci8 is placed into gpr( r d). special registers altered: ca, cr0 (if rc=1) vle user 0 5 6 1011 1516 192021222324 31 000110 rd ra 1001rcf scl ui8 instruction set RM0004 359/1176 addme addme add to minus one extended addme r d ,r a(oe=0, rc=0) addme. r d ,r a(oe=0, rc=1) addmeo r d ,r a(oe=1, rc=0) addmeo. r d ,r a(oe=1, rc=1) if e=0 then cin ca carry 0:63 carry(ra + cin + 0xffff_ffff_ffff_ffff) sum 0:63 ra + cin + 0xffff_ffff_ffff_ffff if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 for addme [ o ][ . ], the sum of the contents of r a, ca, and 64 1 is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a /// oe011101010rc RM0004 instruction set 360/1176 addze addze add to zero extended addze r d ,r a(oe=0, rc=0) addze. r d ,r a(oe=0, rc=1) addzeo r d ,r a(oe=1, rc=0) addzeo. r d ,r a(oe=1, rc=1) if e=0 then cin ca carry 0:63 carry(ra + cin) sum 0:63 ra + cin if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 for addze [ o ][ . ], the sum of the contents of r a and ca is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a /// oe011001010rc instruction set RM0004 361/1176 and and and [immediate [shifted ] | with complement] and r a ,r s ,r b(rc=0) and. r a ,r s ,r b(rc=1) andi. r a ,r s , uimm (s=0, rc=1) andis. r a ,r s , uimm (s=1, rc=1) andc r a ,r s ,r b(rc=0) andc. r a ,r s ,r b(rc=1) if ?andi.? then b 48 0 || uimm if ?andis.? then b 32 0 || uimm || 16 0 if ?and[.]? then b rb if ?andc[.]? then b ? rb result 0:63 rs & b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result for andi. , the contents of r s are anded with 48 0 || uimm. for andis. , the contents of r s are anded with 32 0 || uimm || 16 0. for and [ . ], the contents of r s are anded with the contents of r b. for andc [ . ], the contents of r s are anded with the one?s complement of the contents of r b. the result is placed into r a. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0000011100rc 0 4 5 6 10 11 15 16 31 01110s r s r auimm 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0000111100rc RM0004 instruction set 362/1176 _ and x _and x and [2 operand] [immediate | with complement] [and record] se_and r x ,r y(rc=0) se_and. r x ,r y(rc=1) e_and2i. r d , ui e_and2is. r d , ui e_andi r a ,r s , sci8 (rc = 0) e_andi. r a ,r s , sci8 (rc = 1) se_andi r x , ui5 se_andc r x ,r y if ?e_andi[ . ]? then b sci8(f,scl,ui8) if ?se_andi? then b ui5 if ?se_and[ . ]? then b gpr(ry) if ?se_andc? then b ? gpr(ry) if ?e_and2i.? then b 16 0 || ui 0:4 || ui 5:15 if ?e_and2is.? then b ui 0:4 || ui 5:15 || 16 0 result 32:63 gpr(rs or rd or rx) & b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so if ?se_and[ci]? then gpr(rx) result 32:63 else gpr(ra or rd) result 32:63 for e_andi [ . ], the contents of gpr( r s) are anded with the value of sci8. for e_and2i. , the contents of gpr( r d) are anded with 16 0 || ui. for e_and2is. , the contents of gpr( r d) are anded with ui || 16 0. for se_andi , the contents of gpr( r x) are anded with the value of ui5. for se_and [ . ], the contents of gpr( r x) are anded with the contents of gpr( r y). 05678111215 0100011rc ry rx vle user 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11001 ui 5:15 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11101 ui 5:15 0 5 6 1011 1516 2021222324 31 000110 rs ra 1100rcf scl ui8 0 5 6 7 11 12 15 0010111 ui5 rx 05678111215 01000101 ry rx instruction set RM0004 363/1176 for se_andc , the contents of gpr( r x) are anded with the one?s complement of the contents of gpr( r y). the result is placed into gpr( r a) or gpr( r x) ( se_and [ ic ][ . ]) special registers altered: cr0 (if rc = 1) RM0004 instruction set 364/1176 b b branch [and link] [absolute] b li (aa=0, lk=0) ba li (aa=1, lk=0) bl li (aa=0, lk=1) bla li (aa=1, lk=1) if aa=1 then a 64 0 else a cia if e=0 then nia 32 0 || (a + exts(li||0b00)) 32:63 if lk=1 then lr cia + 4 the branch target effective address (btea) is calculated as follows: for 32-bit implementations, btea is bits 32?63 of the sum of the current instruction address (cia), or 32 zeros if aa=1, and the sign-extended value of the li instruction field concatenated with 0b00 btea is the address of the next instruction to be executed. if lk=1, the sum cia+4 is placed into the lr. other registers altered: lr (if lk=1) book e user 056 29 30 31 010010 li aalk instruction set RM0004 365/1176 _ b x _b x branch [and link] e_b bd24 (lk = 0) e_bl bd24 (lk = 1) a cia nia (a + exts(bd24||0b0)) 32:63 if lk=1 then lr cia + 4 let the btea be calculated as follows: for e_b [ l ], let btea be the sum of the cia and the sign-extended value of the bd24 instruction field concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia+4 is placed into the lr. special registers altered: lr (if lk = 1) se_b bd8 (lk = 0) se_bl bd8 (lk = 1) a cia nia (a + exts(bd8||0b0)) 32:63 if lk=1 then lr cia + 2 let the btea be calculated as follows: for se_b [ l ], let btea be the sum of the cia and the sign-extended value of the bd8 instruction field concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia+2 is placed into the lr. special registers altered: lr (if lk = 1) vle user 0 567 30 31 0111100 bd24 lk 05678 15 1110100lk bd8 RM0004 instruction set 366/1176 bc bc branch conditional [and link] [absolute] bc bo , bi , bd (aa=0, lk=0) bca bo , bi , bd (aa=1, lk=0) bcl bo , bi , bd (aa=0, lk=1) bcla bo , bi , bd (aa=1, lk=1) if ? bo 2 then ctr 32:63 ctr 32:63 : 1 ctr_ok bo 2 | ((ctr 32:63 0) bo 3 ) cond_ok bo 0 | (cr bi+32 bo 1 ) if ctr_ok & cond_ok then if aa=1 then a 64 0 else a cia if e=0 then nia 32 0 || (a + exts(bd||0b00)) 32:63 else nia cia + 4 if lk=1 then lr cia + 4 the branch target effective address (btea) is calculated as follows: for 32-bit implementations, btea is bits 32?63 of the sum of the current instruction address (cia), or 32 zeros if aa=1, and the sign-extended value of the li instruction field concatenated with 0b00 the bo instruction field specifies any conditions that must be met for the branch to be taken, as defined in conditional branch control on page 167 .? the sum bi+32 specifies the cr bit to be used. the bi field specifies the cr bit used as the condition of the branch, as shown in ta b l e 2 0 0 . book e user 0 5 6 1011 1516 293031 010000 bo bi bd aalk instruction set RM0004 367/1176 if the branch conditions are met, the btea is the address of the next instruction to be executed. if lk=1, the sum cia + 4 is placed into the lr. other registers altered: ctr(if bo 2 =0) lr(if lk=1) table 200. bi operand settings for cr fields cr n bits cr bits bi description cr0[0] 32 00000 negative (lt)?set when the result is negative. cr0[1] 33 00001 positive (gt)?set when t he result is positive (and not zero). cr0[2] 34 00010 zero (eq)?set when the result is zero. cr0[3] 35 00011 summary overflow (so). co py of xer[so] at the instruction?s completion. cr1[0] 36 00100 copy of fpscr[fx] at the instruction?s completion. cr1[1] 37 00101 copy of fpscr[fex] at the instruction?s completion. cr1[2] 38 00110 copy of fpscr[vx] at the instruction?s completion. cr1[3] 39 00111 copy of fpscr[ox] at the instruction?s completion. cr n [0] 40 44 48 52 56 60 01000 01100 10000 10100 11000 11100 less than or floating-point less than (lt, fl). for integer compare instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). for floating-point compare instructions: fr a < fr b. cr n [1] 41 45 49 53 57 61 01001 01101 10001 10101 11001 11101 greater than or floating-poi nt greater than (gt, fg). for integer compare instructions: r a > simm or r b (signed comparison) or r a > uimm or r b (unsigned comparison). for floating-point compare instructions: fr a > fr b. cr n [2] 42 46 50 54 58 62 01010 01110 10010 10110 11010 11110 equal or floating-point equal (eq, fe). for integer compare instructions: r a = simm, uimm, or r b. for floating-point compare instructions: fr a = fr b. cr n [3] 43 47 51 55 59 63 01011 01111 10011 10111 11011 11111 summary overflow or floating-point unordered (so, fu). for integer compare instructions, this is a copy of xer[so] at the completion of the instruction. for floating-point compare instructions, one or both of fr a and fr b is a nan. RM0004 instruction set 368/1176 _ bc x _bc x branch conditional [and link] e_bc bo32 , bi32 , bd15 (lk = 0) e_bcl bo32 , bi32 , bd15 (lk = 1) if bo32 0 then ctr 32:63 ctr 32:63 ? 1 ctr_ok ? bo32 0 | ((ctr 32:63 0) bo32 1 ) cond_ok bo32 0 | (cr bi32+32 bo32 1 ) if ctr_ok & cond_ok then nia (cia + exts(bd15 || 0b0)) 32:63 else nia cia + 4 if lk=1 then lr cia + 4 let the btea be calculated as follows: for e_bc [ l ], let btea be the sum of the cia and the sign-extended value of the bd15 instruction field concatenated with 0b0. bo32 specifies any conditions that must be met for the branch to be taken, as defined in chapter 12.2.2: branch instructions on page 864 .? the sum bi32+32 specifies the cr bit. only cr[32?47] may be specified. if the branch conditions are met, the btea is the address of the next instruction to be executed. if lk = 1, the sum cia + 4 is placed into the lr. special registers altered: ctr (if bo32 0 =1) lr (if lk = 1) se_bc bo16,bi16,bd8 cond_ok (cr bi16+32 bo16) if cond_ok then nia (cia + exts(bd8 || 0b0)) 32:63 else nia cia + 2 let the btea be calculated as follows: for se_bc , btea is the sum of the cia and the sign-extended value of the bd8 instruction field concatenated with 0b0. bo16 specifies any conditions that must be met for the branch to be taken, as defined in chapter 12.2.2: branch instructions .? the sum bi16+32 specifies cr bit; only cr[32?35] may be specified. if the branch conditions are met, the btea is the address of the next instruction to be executed. special registers altered: none vle user 0 5 6 9 10 11 12 15 16 30 31 011110 1 0 0 0 bo32 bi32 bd15 lk 0 4 5 678 15 11100bo16bi16 bd8 instruction set RM0004 369/1176 bcctr bcctr branch conditional to count register [and link] bcctr bo , bi (lk=0) bcctrl bo , bi (lk=1) cond_ok bo 0 | (cr bi+32 bo 1 ) if cond_ok & e=0 then nia 32 0 || ctr 32:61 || 0b00 if ? cond_ok then nia cia + 4 if lk=1 then lr cia + 4 the branch target effective address (btea) is calculated as follows: for bcctr [ l ], btea is the contents of ctr[32?61] concatenated with 0b00. bo specifies conditions that must be met for the branch to be taken. bi+32 specifies the cr bit to be used; see ta b l e 2 0 1 . book e user 0 5 6 1011 1516 2021 3031 010011 bo bi /// 1000010000lk RM0004 instruction set 370/1176 if the condition is met, the btea is the address of the next instruction to be executed. if lk=1, the sum cia + 4 is placed into the lr. if the decrement and test ctr option is specifie d (bo[2]=0), the instruction form is invalid. other registers altered: lr (if lk=1) table 201. bi operand settings for cr fields cr n bits cr bits bi description cr0[0] 32 00000 negative (lt)?set when the result is negative. cr0[1] 33 00001 positive (gt)?set when t he result is positive (and not zero). cr0[2] 34 00010 zero (eq)?set when the result is zero. cr0[3] 35 00011 summary overflow (so). copy of xer[so] at the instruction?s completion. cr1[0] 36 00100 copy of fpscr[fx] at the instruction?s completion. cr1[1] 37 00101 copy of fpscr[fex] at the instruction?s completion. cr1[2] 38 00110 copy of fpscr[vx] at the instruction?s completion. cr1[3] 39 00111 copy of fpscr[ox] at the instruction?s completion. cr n [0] 40 44 48 52 56 60 01000 01100 10000 10100 11000 11100 less than or floating-point less than (lt, fl). for integer compare instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). for floating-point compare instructions: fr a < fr b. cr n [1] 41 45 49 53 57 61 01001 01101 10001 10101 11001 11101 greater than or floating-point greater than (gt, fg). for integer compare instructions: r a > simm or r b (signed comparison) or r a > uimm or r b (unsigned comparison). for floating-point compare instructions: fr a > fr b. cr n [2] 42 46 50 54 58 62 01010 01110 10010 10110 11010 11110 equal or floating-point equal (eq, fe). for integer compare instructions: r a = simm, uimm, or r b. for floating-point compare instructions: fra = frb. cr n [3] 43 47 51 55 59 63 01011 01111 10011 10111 11011 11111 summary overflow or floating-point unordered (so, fu). for integer compare instructions, this is a copy of xer[so] at the completion of the instruction. for floating-point compare instructions, one or both of fr a and fr b is a nan. instruction set RM0004 371/1176 bclr bclr branch conditional to link register [and link] bclr bo , bi (lk=0) bclrl bo , bi (lk=1) if ? bo 2 then ctr 32:63 ctr 32:63 - 1 ctr_ok bo 2 | ((ctr 32:63 0) bo 3 ) cond_ok bo 0 | (cr bi+32 bo 1 ) if ctr_ok & cond_ok & e=0 then nia 32 0 || lr 32:61 || 0b00 if ? (ctr_ok & cond_ok) then nia cia + 4 if lk=1 then lr cia + 4 the branch target effective address (btea) is calculated as follows: for bclr [ l ], btea is the contents of lr[32?61] concatenated with 0b00. the bo field specifies any conditio ns that must be met for the br anch to be taken, as defined in conditional branch control on page 167 .? the sum bi+32 specifies the cr bit to be used. the bi field specifies the cr bit used as the condition of the branch, as shown in ta b l e 2 0 2 . book e user 0 5 6 1011 1516 2021 3031 010011 bo bi /// 0000010000lk RM0004 instruction set 372/1176 if the condition is met, the btea is the address of the next instruction to be executed. if lk=1, the sum cia + 4 is placed into the lr. other registers altered: ctr (if bo 2 =0) lr (if lk=1) table 202. bi operand settings for cr fields cr n bits cr bits bi description cr0[0] 32 00000 negative (lt)?set when the result is negative. cr0[1] 33 00001 positive (gt)?set when the result is positive (and not zero). cr0[2] 34 00010 zero (eq)?set when the result is zero. cr0[3] 35 00011 summary overflow (so). copy of xer[so] at the instruction?s completion. cr1[0] 36 00100 copy of fpscr[fx] at the instruction?s completion. cr1[1] 37 00101 copy of fpscr[fex] at the instruction?s completion. cr1[2] 38 00110 copy of fpscr[vx] at the instruction?s completion. cr1[3] 39 00111 copy of fpscr[ox] at the instruction?s completion. cr n [0] 40 44 48 52 56 60 01000 01100 10000 10100 11000 11100 less than or floating-po int less than (lt, fl). for integer compare instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). for floating-point compare instructions: fr a < fr b. cr n [1] 41 45 49 53 57 61 01001 01101 10001 10101 11001 11101 greater than or floating-poi nt greater than (gt, fg). for integer compare instructions: r a > simm or r b (signed comparison) or r a > uimm or r b (unsigned comparison). for floating-point compare instructions: fr a > fr b. cr n [2] 42 46 50 54 58 62 01010 01110 10010 10110 11010 11110 equal or floating-point equal (eq, fe). for integer compare instructions: r a = simm, uimm, or r b. for floating-point compare instructions: fr a = fr b. cr n [3] 43 47 51 55 59 63 01011 01111 10011 10111 11011 11111 summary overflow or floating-point unordered (so, fu). for integer compare instructions, this is a copy of xer[so] at the completion of the instruction. for floating-point compare instructions, one or both of fr a and fr b is a nan. instruction set RM0004 373/1176 _ bclri _bclri bit clear immediate se_bclri r x,ui5 a ui5 b a 1 || 0 || 31- a 1 result 32:63 gpr(rx) & b gpr(rx) result 32:63 for se_bclri , the bit of gpr( r x) specified by the value of ui5 is cleared and all other bits in gpr( r x) remain unaffected. special registers altered: none 0 5 6 7 11 12 15 0110000 ui5 rx vle user RM0004 instruction set 374/1176 _ bctr x _bctr x branch to count register [and link] se_bctr (lk = 0) se_bctrl (lk = 1) nia ctr 32:62 || 0b0 if lk=1 then lr cia + 2 let the btea be calculated as follows: for se_bctr [ l ], let btea be bits 32?62 of the contents of the ctr concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia + 2 is placed into the lr. special registers altered: lr (if lk = 1) 01415 000000000000011lk vle user instruction set RM0004 375/1176 _ bgeni _bgeni bit generate immediate se_bgeni r x,ui5 a ui5 b a 0 || 1 || 31- a 0 gpr(rx) b for se_bgeni , a constant value consisting of a single ?1? bit surrounded by ?0?s is generated and the value is placed into gpr( r x). the position of the ?1? bit is specified by the ui5 field. special registers altered: none 0 5 6 7 11 12 15 0110001 ui5 rx vle user RM0004 instruction set 376/1176 _ blr x _blr x branch to link register [and link] se_blr (lk = 0) se_blrl (lk = 1) nia lr 32:62 || 0b0 if lk=1 then lr cia + 2 let the btea be calculated as follows: for se_blr [ l ], let btea be bits 32?62 of the contents of the lr concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia + 2 is placed into the lr. special registers altered: lr (if lk = 1) 01415 000000000000010lk vle user instruction set RM0004 377/1176 _ bmaski _bmaski bit mask generate immediate se_bmaski r x , ui5 a ui5 if a = 0 then b 32 1 else b 32-a 0 || a 1 gpr(rx) b for se_bmaski , a constant value consisting of a mask of low-order ?1? bits that is zero- extended to 32 bits is generated, and the value is placed into gpr( r x). the number of low- order ?1? bits is specified by the ui5 field. if ui5 is 0b00000, a value of all ?1?s is generated special registers altered: none 0 5 6 7 11 12 15 0010110 ui5 rx vle user RM0004 instruction set 378/1176 brinc brinc bit reversed increment brinc r d ,r a ,r b n maskbits // imp dependent # of mask bits mask rb 64-n:63 // least sig. n bits of register a ra 64-n:63 d bitreverse(1 + bitreverse(a | ( ? mask))) rd ra 0:63-n || (d & mask) brinc provides a way for software to access fft data in a bit-reversed manner. r a contains the index into a buffer that contains data on which fft is to be performed. r b contains a mask that allows the index to be updated with bit-reversed addressing. typically this instruction precedes a load with index instruction; for example, brinc r2, r3, r4 lhax r8, r5, r2 r b contains a bit-mask that is based on the number of points in an fft. to access a buffer containing n byte sized data that is to be accessed with bit-reversed addressing, the mask has log 2 n 1s in the least significant bit positions a nd 0s in the remaining most significant bit positions. if, however, the data size is a multiple of a half word or a word, the mask is constructed so that the 1s are shifted left by log 2 (size of the data) and 0s are placed in the least significant bit positions. ta bl e 2 0 3 shows example values of masks for different data sizes and number of data. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 0 1000001111 table 203. data samples and sizes number of data samples data size byte half word word double word 8 000...00000111 000...00001110 000...000011100 000...0000111000 16 000...00001111 000...00011110 000...000111100 000...0001111000 32 000...00011111 000...00111110 000...001111100 000...0011111000 64 000...00111111 000...01111110 000...011111100 000...0111111000 instruction set RM0004 379/1176 _ bseti _bseti bit set immediate se_bseti r x,ui5 a ui5 b a 0 || 1 || 31- a 0 result 32:63 gpr(rx) | b gpr(rx) result 32:63 for se_bseti , the bit of gpr( r x) specified by the value of ui5 is set, and all other bits in gpr( r x) remain unaffected. special registers altered: none 0 5 6 7 11 12 15 0110010 ui5 rx vle user RM0004 instruction set 380/1176 _ btsti _btsti bit test immediate se_btsti r x , ui5 a ui5 b a 0 || 1 || 31- a 0 c gpr(rx) & b if c = 32 0 then d 0b001 else d 0b010 cr 0:3 d || xer so for se_btsti , the bit of gpr( r x) specified by the value of ui5 is tested for equality to ?1?. the result of the test is recorded in the cr. eq is set if the tested bit is clear, lt is cleared, and gt is set to the inverse value of eq. special registers altered: cr[0?3] 0 5 6 7 11 12 15 0110011 ui5 rx vle user instruction set RM0004 381/1176 cmp cmp compare [immediate] cmp cr d , l ,r a ,r b cmpi cr d , l ,r a , simm if l=0 then a exts(ra 32:63 ) else a ra if ?cmpi? then b exts(simm) if ?cmp? & l=0 then b exts(rb 32:63 ) if ?cmp? & l=1 then b rb if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 4 cr d+32:4 cr d+35 c || xer so if cmp and l=0, the contents of r a[32?63] are compared with the contents of r b[32?63], treating the operands as signed integers. if cmpi and l=0, the contents of r a[32?63] are compared with the sign-extended value of the simm field, treating the operands as signed integers. the result of the comparison is placed into cr field cr d. other registers altered: cr field cr d book e user 0 5 6 8 9 1011 1516 2021 3031 011111 cr d/l r a r b 0000000000 / 0568910111516 31 001011 cr d/l r asimm RM0004 instruction set 382/1176 _ cmp cmp compare [immediate] e_cmp16i r a , si e_cmpi cr d32 ,r a , sci8 a gpr(ra) 32:63 if ?e_cmpi? then b sci8(f,scl,ui8) if ?e_cmp16i? then b exts(si 0:4 || si 5:15 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 if ?e_cmpi? then cr 4 crd32+32:4 crd32+35 c || xer so // only cr0-cr3 if ?e_cmp16i? then cr 32:35 c || xer so // only cr0 if e_cmpi , gpr( r a) contents are compared with the value of sci8, treating operands as signed integers. if e_cmp16i , gpr( r a) contents are compared with the sign-extended value of the si field, treating operands as signed integers. the result of the comparison is placed into cr field cr d ( cr d32). for e_cmpi , only cr0? cr3 may be specified. for e_cmp16i , only cr0 may be specified. special registers altered: cr field cr d ( cr d32) (cr0 for e_cmp16i ) se_cmp r x ,r y se_cmpi r x , ui5 a gpr(rx) 32:63 if ?se_cmpi? then b 27 0 || ui5 if ?se_cmp? then b gpr(ry) 32:63 if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 0:3 c || xer so if se_cmp , the contents of gpr( r x) are compared with the contents of gpr( r y), treating the operands as signed integers. the result of the comparison is placed into cr field 0. if se_cmpi , the contents of gpr( r x) are compared with the value of the zero-extended ui5 field, treating the operands as signed integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] vle user 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0011 si 5:15 0 5 6 8 9 1011 1516 2021222324 31 0001100 00crd32 ra 10101f scl ui8 05678111215 00001100 ry rx 0 5 6 7 11 12 15 0010101 ui5 rx instruction set RM0004 383/1176 _ cmph _cmph compare halfword [immediate] e_cmph cr d ,r a ,r b a exts(gpr(ra) 48:63 ) b exts(gpr(rb) 48:63 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 4 crd+32:4 crd+35 c || xer so for e_cmph , the contents of the low-order 16 bits of gpr( r a) and gpr( r b) are compared, treating the operands as signed integers. the result of the comparison is placed into cr field crd. special registers altered: cr field crd se_cmph r x ,r y a exts(gpr(rx) 48:63 ) b exts(gpr(ry) 48:63 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 0:3 c || xer so for se_cmph , the contents of the low-order 16 bits of gpr( r x) and gpr( r y) are compared, treating the operands as signed integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] e_cmph16i r a , si a exts(gpr(ra) 48:63 ) b exts(si 0:4 || si 5:15 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 32:35 c || xer so // only cr0 the contents of the lower 16-bits of gpr( r a) are sign-extended and compared with the sign-extended value of the si field, treating the operands as signed integers. the result of the comparis on is placed into cr0. special registers altered: cr0 vle user 0 5 6 1011 1516 2021 3031 011111 crd / ra rb 0000001110 / 05678111215 00001110 ry rx 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0110 si 5:15 RM0004 instruction set 384/1176 _ cmphl _cmphl compare halfword logical [immediate] e_cmphl cr d ,r a ,r b a extz(gpr(ra) 48:63 ) b extz(gpr(rb) 48:63 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 4 crd+32:4 crd+35 c || xer so for e_cmphl , the contents of the low-order 16 bits of gpr( r a) and gpr( r b) are compared, treating the operands as unsigned integers. the result of the comparison is placed into cr field crd. special registers altered: cr field crd se_cmphl r x ,r y a gpr(rx) 48:63 b gpr(ry) 48:63 if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 0:3 c || xer so for se_cmphl , the contents of the low-order 16 bits of gpr( r x) and gpr( r y) are compared, treating the operands as unsigned integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] e_cmphl16i r a , ui a 16 0 || gpr(ra) 48:63) b 16 0 || ui 0:4 || ui 5:15 if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 32:35 c || xer so // only cr0 the contents of the lower 16-bits of gpr( r a) are zero-extended and compared with the zero-extended value of the ui field, treating the operands as unsigned integers. the result of the comparis on is placed into cr0. special registers altered: cr0 vle user 0 5 6 1011 1516 2021 3031 011111 crd / ra rb 0000101110 / 05678111215 00001111 ry rx 0 5 6 1011 1516 2021 31 011100 ui 0:4 ra 1 0111 ui 5:15 instruction set RM0004 385/1176 cmpl cmpl compare logical [immediate] cmpl cr d , l ,r a ,r b cmpli cr d , l ,r a , uimm if l=0 then a 32 0 || ra 32:63 else a ra if ?cmpli? then b 48 0 || uimm if ?cmpl? & l=0 then b 32 0 || rb 32:63 if ?cmpl? & l=1 then b rb if a < u b then c 0b100 if a > u b then c 0b010 if a = b then c 0b001 cr 4 cr d+32:4 cr d+35 c || xer so if cmpl and l=0, the contents of r a[32?63] are compared with the contents of r b[32?63], treating the operands as unsigned integers. if cmpli and l=0, the contents of r a[32?63] are compared with the zero-extended value of the uimm field, treating the operands as unsigned integers. the result of the comparison is placed into cr field cr d. other registers altered: cr field cr d book e user 0 5 6 8 9 1011 1516 2021 31 011111 cr d/l r a r b 0000100000 / 0568910111516 31 001010 cr d/l r auimm RM0004 instruction set 386/1176 _ cmpl _cmpl compare logical [immediate] e_cmpl16i r a , ui e_cmpli cr d32 ,r a , sci8 a gpr(ra) 32:63 if ?e_cmpli? then b sci8(f,scl,ui8) if ?e_cmpl16i? then b 16 0 || ui 0:4 || ui 5:15 if a < u b then c 0b100 if a > u b then c 0b010 if a = b then c 0b001 if ?e_cmpli? then cr 4 crd32+32:4 crd32+35 c || xer so // only cr0-cr3 if ?e_cmp16i? then cr 32:35 c || xer so // only cr0 if e_cmpi , the contents of bits 32?63 of gpr( r a) are compared with the value of sci8, treating the operands as unsigned integers. l must be 0 for 32-bit implementations if e_cmpl16i , the contents of gpr( r a) are compared with the zero-extended value of the ui field, treating the operands as unsigned integers. the result of the comparison is placed into cr field crd (crd32). for e_cmpli , only cr0? cr3 may be specified. for e_cmpl16i , only cr0 may be specified. special registers altered: cr field crd (crd32) (cr0 for e_cmpl16i ) se_cmpl r x ,r y se_cmpli r x , oimm a gpr(rx) 32:63 if ?se_cmpli? then b 27 0 || offset(oim5) if ?se_cmpl? then b gpr(ry) 32:63 if a < u b then c 0b100 if a > u b then c 0b010 if a = b then c 0b001 cr 0:3 c || xer so if se_cmpl , the contents of gpr( r x) are compared with the contents of gpr( r y), treating the operands as unsigned integers. the result of the comparison is placed into cr field 0. vle user 0 5 6 1011 1516 2021 31 011100 ui 0:4 ra 1 0101 ui 5:15 0 5 6 8 9 1011 1516 2021222324 31 0001100 01crd32 ra 10101f scl ui8 05678111215 00001101 ry rx 0 5 6 7 11 12 15 0010001 oim5 (1) 1. oimm = oim5 +1 rx instruction set RM0004 387/1176 if se_cmpli , the contents of gpr( r x) are compared with the value of the zero-extended offset value of the oim5 field (a final value in the range 1?32), treating the operands as unsigned integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] RM0004 instruction set 388/1176 cntlzw cntlzw count leading zeros (word) cntlzw r a ,r s(z=0, rc=0) cntlzw. r s(z=0, rc=1) if ?cntlzd? then n 0 else n 32 i 0 do while n < 64 if rs n = 1 then leave n n + 1 i i + 1 ra i if rc=1 then do gt i > 0 eq i = 0 cr0 0b0 || gt || eq || so for cntlzw [ . ], a count of the number of consecutive zero bits starting at r s[32] is placed into r a. this number ranges from 0 to 32, inclusive. if rc=1, cr field 0 is set to reflect the result. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 242526 3031 011111 r s r a /// 0000z11010rc instruction set RM0004 389/1176 crand crand condition register and crand crb d ,crb a ,crb b cr crb d+32 cr crb a+32 & cr crb b+32 the content of bit crb a+32 of cr is anded with the content of bit crb b+32 of cr, and the result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0100000001 / RM0004 instruction set 390/1176 _ crand _crand condition register and e_crand crb d ,crb a ,crb b cr bt+32 cr ba+32 & cr bb+32 the content of bit crba+32 of the cr is anded with the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr condition register and with complement e_crandc crb d ,crb a ,crb b cr bt+32 cr ba+32 & ? cr bb+32 the content of bit crba+32 of the cr is anded with the one?s complement of the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr cr equivalent e_creqv crb d ,crb a ,crb b cr bt+32 cr ba+32 cr bb+32 the content of bit crba+32 of the cr is xored with the content of bit crbb+32 of the cr, and the one?s complement of result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0100000001 / 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0010000001 / 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0100100001 / instruction set RM0004 391/1176 crandc crandc condition register and with complement crandc crb d ,crb a ,crb b cr crb d+32 cr crb a+32 & ? cr crb b+32 the content of bit crb a+32 of cr is anded with the one?s complement of the content of bit crb b+32 of cr, and the result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0010000001 / RM0004 instruction set 392/1176 creqv creqv condition register equivalent creqv crb d ,crb a ,crb b cr crb d+32 cr crb a+32 cr crb b+32 the content of bit crb a + 32 of cr is xored with the content of bit crb b + 32 of cr, and the one?s complement of result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0100100001 / instruction set RM0004 393/1176 crnand crnand condition register nand crnand crb d ,crb a ,crb b cr crb d+32 ? (cr crb a+32 & cr crb b+32 ) the content of bit crb a+32 of cr is anded with the content of bit crb b+32 of cr, and the one?s complement of the result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0011100001 / RM0004 instruction set 394/1176 _ crnand _crnand condition register nand e_crnand crb d ,crb a ,crb b cr bt+32 ? (cr ba+32 & cr bb+32 ) the content of bit crba+32 of the cr is anded with the content of bit crbb+32 of the cr, and the one?s complement of the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0011100001 / instruction set RM0004 395/1176 crnor crnor condition register nor crnor crb d ,crb a ,crb b cr crb d+32 ? (cr crb a+32 | cr crb b+32 ) the content of bit crb a+32 of cr is ored with the content of bit crb b+32 of cr, and the one?s complement of the result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0000100001 / RM0004 instruction set 396/1176 _ crnor _crnor condition register nor e_crnor crb d ,crb a ,crb b cr bt+32 ? (cr ba+32 | cr bb+32 ) the content of bit crba+32 of the cr is ored with the content of bit crbb+32 of the cr, and the one?s complement of the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0000100001 / instruction set RM0004 397/1176 cror cror condition register or cror crb d ,crb a ,crb b cr crb d+32 cr crb a+32 | cr crb b+32 the content of bit crb a+32 of cr is ored with the content of bit crb b+32 of cr, and the result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0111000001 / RM0004 instruction set 398/1176 _ cror _cror condition register or e_cror crb d ,crb a ,crb b cr bt+32 cr ba+32 | cr bb+32 the content of bit crba+32 of the cr is ored with the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0111000001 / instruction set RM0004 399/1176 crorc crorc condition register or with complement crorc crb d ,crb a ,crb b cr crb d+32 cr crb a+32 | ? cr crb b+32 the content of bit crb a+32 of cr is ored with the one?s complement of the content of bit crb b+32 of cr, and the result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0110100001 / RM0004 instruction set 400/1176 _ crorc _crorc condition register or with complement e_crorc crb d ,crb a ,crb b cr bt+32 cr ba+32 | ? cr bb+32 the content of bit crba+32 of the cr is ored with the one?s complement of the content of bit crbb+32 of the cr, and the result is placed into bit crbd +32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0110100001 / instruction set RM0004 401/1176 crxor crxor condition register xor crxor crb d ,crb a ,crb b cr crb d+32 cr crb a+32 cr crb b+32 the content of bit crb a+32 of cr is xored wit h the content of bit crb b+32 of cr, and the result is placed into bit crb d+32 of cr. other registers altered: cr book e user 0 5 6 1011 1516 2021 3031 010011 crb d crb a crb b 0011000001 / RM0004 instruction set 402/1176 _ crxor _crxor condition register xor e_crxor crb d ,crb a ,crb b cr crbd+32 cr ba+32 cr bb+32 the content of bit crba+32 of the cr is xored with the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0011000001 / instruction set RM0004 403/1176 dcba dcba data cache block allocate dcba r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 allocatedatacacheblock(ea) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 dcba is a hint that performance would likely improve if the block containing the byte addressed by ea is established in the data cache without fetching the block from main memory, because the program is likely to soon store into a portion of the block and the contents of the rest of the block are not meaningful to the program. if the hint is honored, the contents of the block are undefined when the instruction completes. the hint is ignored if the block is caching-inhibited. if the block containing the byte addressed by ea is in memory that is memory-coherence required and the block exists in a data cache of any other processors, it is kept coherent in those caches. this instruction is treated as a storeexcept that an interrupt is not taken for a translation or protection violation. this instruction may establish a block in the data cache without verifying that the associated real address is valid. this can cause a delayed machine check interrupt. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 /// r a r b 1011110110 / RM0004 instruction set 404/1176 dcbf dcbf data cache block flush dcbf r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 flushdatacacheblock( ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 if the block containing the byte addressed by ea is in memory that is memory-coherence required, a block containing the byte addressed by ea is in the data cache of any processor, and any locations in the block are considered to be modified there, then those locations are written to main memory. additional locations in the block may also be written to main memory. the block is invalidated in the data caches of all processors. if the block containing the byte addressed by ea is in memory that is not memory-coherence required, a block containing the byte addressed by ea is in the data cache of this processor and any locations in the block are considered to be modified there, then those locations are written to main memory. additional locations in the block may also be written to main memory. the block is invalidated in the data cache of this processor. on some implementations, hi d1[abe] must be set to allo w management of external l2 caches (for implementations with l2 caches) as well as other l1 caches in the system. the function of this instruction is independent of whether the block containing the byte addressed by ea is in memory that is write-through required or caching-inhibited. this instruction is tr eated as a load. see cache management instructions on page 216 .? other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 /// r a r b 0001010110 / instruction set RM0004 405/1176 dcbi dcbi data cache block invalidate dcbi r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 invalidatedatacacheblock( ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 if the block containing the byte addressed by ea is in is coherence-required memory and any block containing the addressed byte is any processors? data cache is invalidated in those caches. on some implementations, before the block is invalidated, if any locations in the block are considered to be modified in any such data cache, those locations are written to main memory and additional locations in the block may be written to main memory. if the block containing the byte addressed by ea is not coherence-required memory and a block containing the byte addressed by ea is in the data cache of this processor, then the block is invalidated in that data cache. on some implementations, before the block is invalidated, any locations in the block considered modified in that data cache are written to main memory; additional locations in the block may be written to main memory. dcbi is treated as a store on implementations that invalidate a block without first writing to main memory all locations in the block that are considered to be modified in the data cache, except that the invalidation is not ordered by mbar . on other implementations this instruction is treated as a load. additional information about this instruction is as follows. the data cache block size for dcbi is the same as for dcbf . if a processor holds a reservation and some other processor executes a dcbi to the same reservation granule, whether the reservation is lost is undefined. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 /// r a r b 0111010110 / RM0004 instruction set 406/1176 dcblc dcblc data cache block lock clear dcblc ct, r a, r b form: x if r a = 0 then a 64 0 else a gpr( r a) if mode32 then ea 32 0 || (a + gpr( r b)) 32:63 if mode64 then ea a + gpr( r b) datacacheblockclearlock(ct, ea) ea calculation: ea for r a=0ea for r a 0 32 0 || gpr(rb) 32:63 32 0 || (gpr(ra)+gpr(rb)) 32:63 the data cache specified by ct has the cache line corresponding to ea unlocked allowing the line to participate in the normal replacement policy. cache lock clear instructions remove locks pr eviously set by cache lock set instructions. user-level cache instructions on page 180 ,? lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. the instruction is treated as a load with respect to translation and memory protection and can cause dsi and dtlb error interrupts accordingly. an unable-to-unlock condition is said to oc cur any of the following conditions exist: the target address is marked cache-inhibited, or the storage attributes of the address uses a coherency protocol th at does not support locking. the target cache is disabled or not present. the ct field of the instructions contains a value not supported by the implementation. the target address is not in the cache or is present in the cache but is not locked. if an unable-to-unlock condition occurs, no cache operation is performed. eis specifics clearing and then setting l1csr0[clfr] allows system software to clear all l1 data cache locking bits without knowing the addresses of the lines locked. cache locking apu user 0 56 101115162021 3031 011111 ct r a r b 0 11000011 0 / instruction set RM0004 407/1176 dcbst dcbst data cache block store dcbst r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 storedatacacheblock( ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 if the block containing the byte addressed by ea is in memory that is memory-coherence required and a block containing the byte addressed by ea is in the data cache of any processor, and any locations in the block are considered to be modified there, those locations are written to main memory. additional locations in the block may be written to main memory. the block ceases to be considered to be modified in that data cache. if the block containing the byte addressed by ea is in memory that is not memory-coherence required and a block containing the byte addressed by ea is in the data cache of this processor and any locations in the block are considered to be modified there, those locations are written to main memory. additional locations in the block may be written to main memory. the block ceases to be considered to be modified in that cache. the function of this instruction is independent of whether the block containing the byte addressed by ea is in memory that is write-through required or caching-inhibited. this instruction is treated as a load. on some implementations, hi d1[abe] must be set to allo w management of external l2 caches (for implementations with l2 caches) as well as other l1 caches in the system. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 /// r a r b 0000110110 / RM0004 instruction set 408/1176 dcbt dcbt data cache block touch dcbt ct ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 prefetchdatacacheblock( ct, ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 user-level cache instructions on page 180 ,? lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. implementations should perform no operation when ct specifies a value not supported by the implementation. the hint is ignored if the block is caching-inhibited. this instruction is treated as a load except that an interrupt is not taken for a translation or protection violation. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 ct r a r b 0100010110 / instruction set RM0004 409/1176 dcbtls dcbtls data cache block touch and lock set dcbtls ct, r a, r b form: x if r a = 0 then a 64 0 else a gpr( r a) if mode32 then ea 32 0 || (a + gpr( r b)) 32:63 if mode64 then ea a + gpr( r b) prefetchdatacacheblocklockset(ct, ea) ea calculation: ea for r a=0ea for r a 0 32 0 || gpr(rb) 32:63 32 0 || (gpr(ra)+gpr(rb)) 32:63 the data cache specified by ct has the cache line corresponding to ea loaded and locked into the cache. if the line already exists in the cache, it is locked without being refetched. cache touch and lock set instructions let softwar e lock cache lines into the cache to provide lower latency for critical cache accesses and more deterministic behavior. locked lines do not participate in the normal replacement policy when a line must be victimized for replacement. user-level cache instructions on page 180 ,? lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. the instruction is treated as a load with respect to translation and memory protection and can cause dsi and dtlb error interrupts accordingly. an unable to lock condition is said to occur any of the follo wing conditions exist: the target address is marked cache-inhibited, or the storage attributes of the address uses a coherency protocol th at does not support locking. the target cache is disabled or not present. the ct field of the instructions contains a value not supported by the implementation. if an unable to lock condition occurs, no cache operation is performed and licsr0[dcul] is set appropriately. overlocking is said to exist is all available ways for a given cache index are already locked. if overlocking occurs for dcbtls and if the lock was targeted for the primary cache (ct = 0), the requested line is not locked into the cach e. when overlock occurs, l1csr1[dclo] is set. if l1csr1[dcloa] is set, the requested line is locked into the cache and implementation dependent line currently locked in the cache is evicted. the results of overlocking and unable to lock conditions for caches other than the primary cache and secondary cache are defined as part of the architecture for the specific cache hierarchy designated by ct. other registers altered: l1csr0[dcul] if unab le to lock occurs l1csr0[dclo] (l2csr[l2clo]) if lock overflow occurs cache locking apu user 0 56 101115162021 3031 011111 ct r a r b 0 01010011 0 / RM0004 instruction set 410/1176 dcbtst dcbtst data cache block touch for store dcbtst ct ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 prefetchforstoredataca cheblock( ct, ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 if ct=0, this instruction is a hint that performance would likely be improved if the block containing the byte addressed by ea is fetched into the data cache, because the program will probably soon store in to the addressed byte. user-level cache instructions on page 180 ,? lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. implementations should perform no operation when ct specifies a value not supported by the implementation. the hint is ignored if the block is caching-inhibited. this instruction is treated as a load , except that an interrupt is not taken for a translation or protection violation. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 ct r a r b 0011110110 / instruction set RM0004 411/1176 dcbtstls dcbtstls data cache block touch for store and lock set dcbtstls ct, r a, r b form: x if r a = 0 then a 64 0 else a gpr( r a) if mode32 then ea 32 0 || (a + gpr( r b)) 32:63 if mode64 then ea a + gpr( r b) prefetchdatacacheblocklockset(ct, ea) ea calculation: ea for r a=0ea for r a 0 32 0 || gpr(rb) 32:63 32 0 || (gpr(ra)+gpr(rb)) 32:63 the data cache specified by ct has the cache line corresponding to ea loaded and locked into the cache. if the line already exists in the cache, it is locked without refetching from memory. cache touch and lock set instructions allow software to lock lines into the cache to shorten latency for critical cache accesses and more deterministic behavior. lines locked in the cache do not participate in the normal replacement policy when a line must be victimized for replacement. user-level cache instructions on page 180 ,? lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. table 114 describes how this instruction is treated with respect to translation and memory protection. for unable-to-lock conditions, described in unable-to-lock conditions on page 849 ,? no cache operation is performed and licsr0[dcul] is set. overlocking occurs when all available ways for a given cache index are already locked. if an overlocking condition occurs for a dcbtstls instruction and if the lock was targeted for the primary cache or secondary cache (ct = 0 or ct = 2), the requested line is not locked into the cache. when overlock occurs, l1csr1[dclo] (l2csr[l2clo] for ct = 2) is set. if l1csr1[dcloa] is set (or l2csr[l2cloa] for ct = 2), the requested line is locked into the cache and implementation dependent line currently locked in the cache is evicted. if system software wants to precisely determine if an overlock event has occurred in the l1 data cache, it must perform the following code sequence: dcbtstls msync mfspr (l1csr0) (check l1csr0[dcul] bit for data ca che index unable-to -lock condition) (check l1csr0[dclo] bit for data cache index overlock condition) results of overlocking and unable-to-lock conditions for caches other than the primary and secondary cache are defined as part of the architecture for the cache hierarchy designated by ct. other registers altered: l1csr0[dcul] if unab le to lock occurs l1csr0[dclo] (l2csr[l2clo]) if lock overflow occurs cache locking apu user 0 56 101115162021 3031 011111 ct r a r b 0 01000011 0 / RM0004 instruction set 412/1176 eis specifics: clearing and then setting l1csr0[clfr] allows system software to clear all data cache locking bits without knowing the addresses of the lines locked. instruction set RM0004 413/1176 dcbz dcbz data cache block set to zero dcbz r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 zerodatacacheblock( ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 if the block containing the addressed byte is in the data cache, all bytes of the block are cleared. if the block containing the byte addressed by ea is not in the data cache and is in memory that is not caching-inhibited, the block is es tablished in the data cache without fetching the block from main memory, and all bytes of the block are cleared. if the block containing the byte addressed by ea is not in the data cache and is in storage that is not caching inhibited and cannot be established in the cache, then one of the following occurs: all bytes of the area of main storage that corresponds to the addressed block are set to zero an alignment interrupt is taken if the block containing the byte addressed by ea is in storage that is caching inhibited or write through required, one of the following occurs: all bytes of the area of main storage that corresponds to the addressed block are set to zero an alignment interrupt is taken. if the block containing the byte addressed by ea is in memory-coherence required memory and the block exists in any other processors? data cache, it is kept coherent in those caches. dcbz may establish a block in the data cache without verifying that the associated real address is valid. this can cause a delayed machine check interrupt. dcbz is treated as a store. on some implementations, hi d1[abe] must be set to allow management of external l2 caches (for implementations with l2 caches) as well as other l1 caches in the system. dcbz may cause a cache-locking exception on some implementations. see the user documentation. other registers altered: none programming note: if the block containing the byte addressed by ea is in memory that is caching-inhibited or write-through required, the alignment interrupt handler should clear all bytes of the area of main memory that corresponds to the addressed block. book e user 0 5 6 1011 1516 2021 3031 011111 /// r a r b 1111110110 / RM0004 instruction set 414/1176 divw divw divide word divw r d ,r a ,r b(oe=0, rc=0) divw. r d ,r a ,r b(oe=0, rc=1) divwo r d ,r a ,r b(oe=1, rc=0) divwo. r d ,r a ,r b(oe=1, rc=1) dividend 0:31 ra 32:63 divisor 0:31 rb 32:63 quotient 0:31 dividend divisor if oe=1 then do ov ( (ra 32:63 =-2 31 ) & (rb 32:63 =-1) ) | (rb 32:63 =0) so so | ov if rc=1 then do lt quotient < 0 gt quotient > 0 eq quotient = 0 cr0 lt || gt || eq || so rd 32:63 quotient rd 0:31 undefined the 32-bit quotient of the contents of r a[32?63] divided by the contents of r b[32?63] is placed into r d[32?63]. r d[0?31] are undefined. the remainder is not supplied as a result. both operands and the quotient are interpreted as signed integers. the quotient is the unique signed integer that satisfies the following: dividend = (quotient divisor) + r here, 0 r < |divisor| if the dividend is nonnegative and ?|divisor| < r 0 if it is negative. if any of the following divisions is attempted, the contents of r d are undefined as are (if rc=1) the contents of the cr0[lt,gt,eq]. in these cases, if oe=1, ov is set. 0x8000_0000 ?1 instruction set RM0004 415/1176 divwu divwu divide word unsigned divwu r d ,r a ,r b(oe=0, rc=0) divwu. r d ,r a ,r b(oe=0, rc=1) divwuo r d ,r a ,r b(oe=1, rc=0) divwuo. r d ,r a ,r b(oe=1, rc=1) dividend 0:31 ra 32:63 divisor 0:31 rb 32:63 quotient 0:31 dividend divisor if oe=1 then do ov (rb 32:63 =0) so so | ov if rc=1 then do lt quotient < 0 gt quotient > 0 eq quotient = 0 cr0 lt || gt || eq || so rd 32:63 quotient rd 0:31 undefined the 32-bit quotient of the contents of r a[32?63] divided by the contents of r b[32?63] is placed into r d[32?63]. r d[0?31] are undefined. the remainder is not supplied as a result. both operands and the quotient are interpreted as unsigned integers, except that if rc=1 the first three bits of cr field 0 are set by signed comparison of the result to zero. the quotient is the unique unsigned integer that satisfies the following: dividend = (quotient divisor) + r here, 0 r < divisor. if an attempt is made to perform the following division, the contents of r d are undefined as are (if rc=1) the contents of the lt, gt, and eq bits of cr0. in this case, if oe=1 ov is set. RM0004 instruction set 416/1176 efdabs efdabs floating-point double-precision absolute value efdabs r d ,r a rd 0:63 0b0 || ra 1:63 the sign bit of r a is set to 0 and the result is placed into r d. exceptions: exception detection for embedded floating-point absolute value operations is implementation dependent. an implementation may choose to not detect exceptions and carry out the sign bit operation. if the implementation does not detect exceptions, or if exception detection is disabled, the computation can be carried out in one of two ways, as a sign bit operation ignoring the rest of the contents of the source register, or by examining the input and appropriately saturating the input prior to performing the operation. if an implementation chooses to handle exceptions, the exception is handled as follows: if r a is infinity, denorm, or nan, spefscr[finv] is set, and fg and fx are cleared. if floating- point invalid input exceptions are enabled, an interrupt is taken and the destination register is not updated. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0 00000 1011100100 instruction set RM0004 417/1176 efdadd efdadd floating-point double-precision add efdadd r d ,r a ,rb rd 0:63 ra 0:63 + dp rb 0:63 r a is added to rb and the result is stored in r d. if r a is nan or infinity, the result is either pmax ( a sign ==0 ), or nmax ( a sign ==1 ). otherwise, if rb is nan or infinity, the result is either pmax ( b sign ==0 ), or nmax ( b sign ==1 ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in r d. if an underflow occurs, +0 (for rounding modes rn, rz, rp) or - 0 (for rounding mode rm) is stored in r d. exceptions: if the contents of r a or rb are infinity, denorm, or na n, spefscr[finv] is set. if spefscr[finve] is set, an interrupt is taken, and the destinat ion register is not updated. otherwise, if an overflow occurs, spefscr[fo vf] is set, or if an underflow occurs, spefscr[funf] is set. if eith er underflow or overflow ex ceptions are en abled and the corresponding bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if the result of this instruction is inexact or if an overflow occurs but overflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs] is set. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx are cleared if an overflow, underflow, or invalid operation/input error is signaled, regardless of enabled exceptions. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 0 1011100000 RM0004 instruction set 418/1176 efdcfs efdcfs floating-point double-precision convert from single-precision efdcfs r d ,rb fp32format f; fp64format result; f rb 32:63 if (f exp = 0) & (f frac = 0)) then result f sign || 63 0 // signed zero value else if isa32nanorinfinity(f) | isa32denorm(f) then spefscr finv 1 result f sign || 0b11111111110 || 52 1// max value else if isa32denorm(f) then spefscr finv 1 result f sign || 63 0 else result sign f sign result exp f exp - 127 + 1023 result frac f frac || 29 0 rd 0:63 = result the single-precision floating-point value in the low element of rb is converted to a double- precision floating-point value and the result is placed into r d. the rounding mode is not used since this conversion is always exact. exceptions: if the low element of rb is infinity, denorm, or nan, spefscr[finv] is set. if spefscr[finve] is set, an interrupt is taken, and the destinat ion register is not updated. fg and fx are always cleared. note: architecture note: this instruction is optional if neither the embedded scalar single- precision floating-point apu or the embedded vector single-precision floating-point apu are implemented. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011101111 instruction set RM0004 419/1176 efdcfsf efdcfsf convert floating-point double-precision from signed fraction efdcfsf rd,rb rd 0:63 cnvti32tofp64(rb 32:63 , sign, f) the signed fractional low element in rb is converted to a double-precision floating-point value using the current rounding mode and the result is placed into r d. exceptions: none. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011110011 RM0004 instruction set 420/1176 efdcfsi efdcfsi convert floating-point double-precision from signed integer efdcfsi rd,rb rd 0:63 cnvtsi32tofp64(rb 32:63 , sign, i) the signed integer low element in rb is converted to a double-precision floating-point value using the current rounding mode and the result is placed into r d. exceptions: none. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011110001 instruction set RM0004 421/1176 efdcfsid efdcfsid convert floating-point double-precision from signed integer doubleword efdcfsid rd,rb rd 0:63 cnvti64tofp64(rb 0:63 , sign) the signed integer doubleword in rb is converted to a double-precision floating-point value using the current rounding mode and the result is placed into r d. exceptions: this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. this instruction may only be implem ented for 64-bit implementations. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011100011 RM0004 instruction set 422/1176 efdcfuf efdcfuf convert floating-point double-precision from unsigned fraction efdcfuf rd,rb rd 0:63 cnvti32tofp64(rb 32:63 , unsign, f) the unsigned fractional low element in rb is converted to a double-precision floating-point value using the current rounding mode and the result is placed into r d. exceptions: none. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 rb 0 1011110010 instruction set RM0004 423/1176 efdcfui efdcfui convert floating-point double-precision from unsigned integer efdcfui rd,rb rd 0:63 cnvtsi32tofp64(rb 32:63 , unsign, i) the unsigned integer low element in rb is converted to a double-precision floating-point value using the current rounding mode and the result is placed into r d. exceptions: none. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011110000 RM0004 instruction set 424/1176 efdcfuid efdcfuid convert floating-point double-precision from unsigned integer doubleword efdcfuid rd,rb rd 0:63 cnvti64tofp64(rb 0:63 , unsign) the unsigned integer doubleword in rb is converted to a double-precision floating-point value using the current rounding mode and the result is placed into r d. exceptions: this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. this instruction may only be implem ented for 64-bit implementations. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011100010 instruction set RM0004 425/1176 efdcmpeq efdcmpeq floating-point double-precision compare equal efdcmpeq crf d ,ra,rb al ra 0:63 bl rb 0:63 if (al = bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined r a is compared against rb . if r a is equal to rb , the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = -0). exceptions: if the contents of r a or rb are infinity, denorm, or nan, spefscr[finv] is set, and the fgh fxh, fg and fx bits are cleared. if floating-point invalid input exceptions are enabled, an interrupt is taken and the condition register is not updated. otherwise, the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. scalar dpfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1011101110 RM0004 instruction set 426/1176 efdcmpgt efdcmpgt floating-point double-precision compare greater than efdcmpgt crf d ,r a ,rb al ra 0:63 bl rb 0:63 if (al > bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined r a is compared against rb . if r a is greater than rb , the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = -0). exceptions: if the contents of r a or rb are infinity, denorm, or nan, spefscr[finv] is set, and the fgh fxh, fg and fx bits are cleared. if floating-point invalid input exceptions are enabled, an interrupt is taken and the condition register is not updated. otherwise, the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. scalar dpfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1011101100 instruction set RM0004 427/1176 efdcmplt efdcmplt f loating-point double-precision compare less than efdcmplt crf d ,r a ,rb al ra 0:63 bl rb 0:63 if (al < bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined r a is compared against rb . if r a is less than rb , the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = -0). exceptions: if the contents of r a or rb are infinity, denorm, or nan, spefscr[finv] is set, and the fgh fxh, fg and fx bits are cleared. if floating-point invalid input exceptions are enabled, an interrupt is taken and the condition register is not updated. otherwise, the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1011101101 RM0004 instruction set 428/1176 efdctsf efdctsf convert floating-point double-precision to signed fraction efdctsf rd,rb rd 32:63 cnvtfp64toi32sat( rb 0:63 , sign, round, f) the double-precision floating-point value in rb is converted to a signed fraction using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit fraction. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, and the destination register is not updated. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 rb 0 1011110111 instruction set RM0004 429/1176 efdctsi efdctsi convert floating-point double-precision to signed integer efdctsi rd,rb rd 32:63 cnvtfp64toi32sat( rb 0:63 , sign, round, i) the double-precision floating-point value in rb is converted to a signed integer using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, the destination register is not updated, and no other status bits are set. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011110101 RM0004 instruction set 430/1176 efdctsidz efdctsidz convert floating-point double-precision to signed integer doubleword with round toward zero efdctsidz rd,rb rd 0:63 cnvtfp64toi64sat( rb 0:63 , sign, trunc) the double-precision floating-point value in rb is converted to a signed integer doubleword using the rounding mode round toward zero and the result is saturated if it cannot be represented in a 64-bit integer. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, the destination register is not updated, and no other status bits are set. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. this instruction may only be implem ented for 64-bit implementations. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011101011 instruction set RM0004 431/1176 efdctsiz efdctsiz convert floating-point double-precision to signed integer with round toward zero efdctsiz rd,rb rd 32:63 cnvtfp64toi32sat( rb 0:63 , sign, trunc, i the double-precision floating-point value in rb is converted to a signed integer using the rounding mode round toward zero and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, the destination register is not updated, and no other status bits are set. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011111010 RM0004 instruction set 432/1176 efdctuf efdctuf convert floating-point double-precision to unsigned fraction efdctuf rd,rb rd 32:63 cnvtfp64toi32sat( rb 0:63 , unsign, round, f) the double-precision floating-point value in rb is converted to an unsigned fraction using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit unsigned fraction. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, and the destination register is not updated. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011110110 instruction set RM0004 433/1176 efdctui efdctui convert floating-point double-precision to unsigned integer efdctui rd,rb rd 32:63 cnvtfp64toi32sat( rb 0:63 , unsign, round, i the double-precision floating-point value in rb is converted to an unsigned integer using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, and the destination register is not updated. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011110100 RM0004 instruction set 434/1176 efdctuidz efdctuidz convert floating-point double-precision to unsigned integer doubleword with round toward zero efdctuidz rd,rb rd 0:63 cnvtfp64toi64sat( rb 0:63 , unsign, trunc) the double-precision floating-point value in rb is converted to an unsigned integer doubleword using the rounding mode round toward zero and the result is saturated if it cannot be represented in a 64-bit integer. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, and the destination register is not updated. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. this instruction may only be implem ented for 64-bit implementations. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011101010 instruction set RM0004 435/1176 efdctuiz efdctuiz convert floating-point double-precision to unsigned integer with round toward zero efdctuiz rd,rb rd 32:63 cnvtfp64toi32sat( rb 0:63 , unsign, trunc, i) the double-precision floating-point value in rb is converted to an unsigned integer using the rounding mode round toward zero and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if the contents of rb are infinity, denorm, or nan, or if an overflow occurs, spefscr[finv] is set, and the fg, and fx bits are cleared. if spefscr[finve] is set, an interrupt is taken, and the destination register is not updated. this instruction can signal an inexact status and set spefscr[ finxs] if the conversion is not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011111000 RM0004 instruction set 436/1176 efddiv efddiv floating-point doub le-precision divide efddiv r d ,r a ,rb rd 0:63 ra 0:63 dp rb 0:63 r a is divided by rb and the result is stored in r d. if rb is a nan or infinity, the result is a properly signed zero. otherwise, if rb is a zero (or a denormalized number optionally transformed to zero by the implementation), or if r a is either nan or infinity, the result is either pmax ( a sign ==b sign ), or nmax ( a sign !=b sign ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in r d. if an underflow occurs, +0 or -0 (as appropriate) is stored in r d. exceptions: if the contents of r a or rb are infinity, denorm, or nan, or if both r a and rb are +/-0, spefscr[finv] is set. if spefscr[ finve] is set, an interrupt is taken, and the destination register is not updated. otherwise, if the content of rb is +/-0 and the content of r a is a finite normalized non-zero number, spefscr[fdbz] is set. if floating-point divide by zero exceptions are enabled, an interrupt is then taken. otherwise, if an overflow occurs, spefscr[fovf] is set, or if an underflow occurs, spef scr[funf] is set. if either underflow or overflow exceptions are enabled and the corresponding bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if the result of this instruction is inexact or if an overflow occurs but overflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs] is set. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx are cleared if an overflow, underflow, divide by zero, or invalid operation/input error is signaled, regardless of enabled exceptions. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 0 1011101000 instruction set RM0004 437/1176 efdmul efdmul floating-point double-precision multiply efdmul r d ,r a ,rb rd 0:63 ra 0:63 dp rb 0:63 r a is multiplied by rb and the result is stored in r d. if r a or rb are zero (or a denormalized number optionally transformed to zero by the implementation), the result is a properly signed zero. otherwise, if r a or rb are either nan or infini ty, the result is either pmax ( a sign ==b sign ), or nmax ( a sign !=b sign ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in r d. if an underflow occurs, +0 or -0 (as appropriate) is stored in r d. exceptions: if the contents of r a or rb are infinity, denorm, or na n, spefscr[finv] is set. if spefscr[finve] is set, an interrupt is taken, and the destinat ion register is not updated. otherwise, if an overflow occurs, spefscr[fo vf] is set, or if an underflow occurs, spefscr[funf] is set. if eith er underflow or overflow ex ceptions are en abled and the corresponding bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if the result of this instruction is inexact or if an overflow occurs but overflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs] is set. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx are cleared if an overflow, underflow, or invalid operation/input error is signaled, regardless of enabled exceptions. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 0 1011101000 RM0004 instruction set 438/1176 efdnabs efdnabs floating-point double-precision negative absolute value efdnabs r d ,r a rd 0:63 0b1 || ra 1:63 the sign bit of r a is set to 1 and the result is placed into r d. exceptions: exception detection for embedded floating-point absolute value operations is implementation dependent. an implementation may choose to not detect exceptions and carry out the sign bit operation. if the implementation does not detect exceptions, or if exception detection is disabled, the computation can be carried out in one of two ways, as a sign bit operation ignoring the rest of the contents of the source register, or by examining the input and appropriately saturating the input prior to performing the operation. if an implementation chooses to handle exceptions, the exception is handled as follows: if r a is infinity, denorm, or nan, spefscr[finv] is set, and fg and fx are cleared. if floating- point invalid input exceptions are enabled, an interrupt is taken and the destination register is not updated. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0 00000 1011100101 instruction set RM0004 439/1176 efdneg efdneg floating-point double-precision negate efdneg r d ,r a rd 0:63 ? ra 0 || ra 1:63 the sign bit of r a is complemented and the result is placed into r d. exceptions: exception detection for embedded floating-point absolute value operations is implementation dependent. an implementation may choose to not detect exceptions and carry out the sign bit operation. if the implementation does not detect exceptions, or if exception detection is disabled, the computation can be carried out in one of two ways, as a sign bit operation ignoring the rest of the contents of the source register, or by examining the input and appropriately saturating the input prior to performing the operation. if an implementation chooses to handle exceptions, the exception is handled as follows: if r a is infinity, denorm, or nan, spefscr[finv] is set, and fg and fx are cleared. if floating- point invalid input exceptions are enabled, an interrupt is taken and the destination register is not updated. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0 00000 1011100110 RM0004 instruction set 440/1176 efdsub efdsub floating-point double-precision subtract efdsub r d ,r a ,rb rd 0:63 ra 0:63 - dp rb 0:63 rb is subtracted from ra and the result is stored in r d. if r a is nan or infinity, the result is either pmax ( a sign ==0 ), or nmax ( a sign ==1 ). otherwise, if rb is nan or infinity, the result is either nmax ( b sign ==0 ), or pmax ( b sign ==1 ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in r d. if an underflow occurs, +0 (for rounding modes rn, rz, rp) or -0 (for rounding mode rm) is stored in r d. exceptions: if the contents of ra or rb are infinity, denorm, or nan, spefscr[finv] is set. if spefscr[finve] is set, an interrupt is taken, and the destinat ion register is not updated. otherwise, if an overflow occurs, spefscr[fo vf] is set, or if an underflow occurs, spefscr[funf] is set. if eith er underflow or overflow ex ceptions are en abled and the corresponding bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if the result of this instruction is inexact or if an overflow occurs but overflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs] is set. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result, the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx are cleared if an overflow, underflow, or invalid operation/input error is signaled, regardless of enabled exceptions. scalar dpfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 0 1011100001 instruction set RM0004 441/1176 efdtsteq efdtsteq floating-point double-precision test equal efdtsteq crf d ,r a ,rb al ra 0:63 bl rb 0:63 if (al = bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined r a is compared against rb . if r a is equal to rb , the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = -0). the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. no exceptions are generated during the execution of efdtsteq if strict ieee 754 compliance is required, the program should use efdcmpeq . implementation note: in an implementation, the execution of efdtsteq is likely to be faster than the execution of efdcmpeq . scalar dpfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1011111110 RM0004 instruction set 442/1176 efdtstgt efdtstgt floating-point double-precision test greater than efdtstgt crf d ,r a ,rb al ra 0:63 bl rb 0:63 if (al > bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined r a is compared against r b. if r a is greater than r b, the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = -0). the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. no exceptions are generated during the execution of efdtstgt . if strict ieee 754 compliance is required, the program should use efdcmpgt . note: implementation note: in an implementation, the execution of efdtstgt is likely to be faster than the execution of efdcmpgt . scalar dpfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1011111100 instruction set RM0004 443/1176 efdtstlt efdtstlt floating-point double-precision test less than efdtstlt crf d ,r a ,rb al ra 0:63 bl rb 0:63 if (al < bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined r a is compared against r b. if r a is less than r b, the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = -0). the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. no exceptions are generated during the execution of efdtstlt . if strict ieee 754 compliance is required, the program should use efdcmplt . implementation note: in an implementation, the execution of efdtstlt is likely to be faster than the execution of efdcmplt . scalar dpfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1011111101 RM0004 instruction set 444/1176 efsabs efsabs floating-point absolute value efsabs r d ,r a rd 32:63 0b0 || ra 33:63 the sign bit of r a is cleared and the result is placed into r d. it is implementation dependent if invalid values for ra (nan, denorm, infinity) are detected and exceptions are taken. scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 000000 1011000100 instruction set RM0004 445/1176 efsadd efsadd floating-point add efsadd r d ,r a ,r b rd 32:63 ra 32:63 + sp rb 32:63 the single-precision floating-point value of r a is added to r b and the result is stored in r d. if an overflow condition is detected or the contents of r a or r b are nan or infinity, the result is an appropriately signed maximum floating-point value. if an underflow condition is detected, the result is an appropriately signed floating-point 0. the following status bits are set in the spefscr: finv if the contents of r a or r b are +infinity, ?infinity, denorm, or nan fofv if an overflow occurs funf if an underflow occurs finxs, fg, fx if the result is inexact or overflow occurred and overflow exceptions are disabled scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 0 1011000000 RM0004 instruction set 446/1176 efscfsf efscfsf convert floating-point from signed fraction efscfsf r d ,r b rd 32:63 cnvti32tofp32sat(rb 32:63 , sign, lower, f) the signed fractional value in r b is converted to the nearest single-precision floating-point value using the current rounding mode and placed into r d. the following status bits are set in the spefscr: finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 01011010011 instruction set RM0004 447/1176 efscfsi efscfsi convert floating-point from signed integer efscfsi r d ,r b rd 32:63 cnvtsi32tofp32sat(rb 32:63 , sign, lower, i) the signed integer value in r b is converted to the nearest single-precision floating-point value using the current rounding mode and placed into r d. the following status bits are set in the spefscr: finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011010001 RM0004 instruction set 448/1176 efscfuf efscfuf convert floating-point from unsigned fraction efscfuf r d ,r b rd 32:63 cnvti32tofp32sat(rb 32:63 , unsign, lower, f) the unsigned fractional value in r b is converted to the nearest single-precision floating-point value using the current rounding mode and placed into r d. the following status bits are set in the spefscr: finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011010010 instruction set RM0004 449/1176 efscfui efscfui convert floating-point from unsigned integer efscfui r d ,r b rd 32:63 cnvti32tofp32sat(rb 32:63 , unsign, lower, i) the unsigned integer value in r b is converted to the nearest single-precision floating-point value using the current rounding mode and placed into r d. the following status bits are set in the spefscr: finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1011010000 RM0004 instruction set 450/1176 efscmpeq efscmpeq floating-point compare equal efscmpeq cr d ,r a ,r b al ra 32:63 bl rb 32:63 if (al = bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined the value in r a is compared against r b. if r a equals r b, the cr d bit is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). if either operand contains a nan, infinity, or a denorm and floating-point invalid exceptions are enabled in the spefscr, the exception is taken. if the exception is not enabled, the comparison treats nans, infinities, and denorms as normalized numbers. the following status bits are set in spefscr: finv if the contents of r a or r b are +infinity, ?infinity, denorm or nan scalar spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d0 0 r a r b 0 1011001110 instruction set RM0004 451/1176 efscmpgt efscmpgt floating-point compare greater than efscmpgt cr d ,r a ,r b al ra 32:63 bl rb 32:63 if (al > bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined the value in r a is compared against r b. if r a is greater than r b, the bit in the cr d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). if either operand contains a nan, infinity, or a denorm and floating-point invalid exceptions are enabled in the spefscr, the exception is taken. if the exception is not enabled, the comparison treats nans, infinities, and denorms as normalized numbers. the following status bits are set in spefscr: finv if the contents of r a or r b are +infinity, ?infinity, denorm or nan scalar spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 0 1011001100 RM0004 instruction set 452/1176 efscmplt efscmplt floating-point compare less than efscmplt cr d ,r a ,r b al ra 32:63 bl rb 32:63 if (al < bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined the value in r a is compared against r b. if r a is less than r b, the bit in the cr d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). if either operand contains a nan, infinity, or a denorm and floating-point invalid exceptions are enabled in the spefscr, the exception is taken. if the exception is not enabled, the comparison treats nans, infinities, and denorms as normalized numbers. the following status bits are set in spefscr: finv if the contents of r a or r b are +infinity, ?infinity, denorm or nan scalar spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 0 1011001101 instruction set RM0004 453/1176 efsctsf efsctsf convert floating-point to signed fraction efsctsf r d ,r b rd 32:63 cnvtfp32toisat(rb 32:63 , sign, lower, round, f) the single-precision floating-point value in r b is converted to a signed fraction using the current rounding mode. the result saturates if it cannot be represented in a 32-bit fraction. nans are converted to 0. the following status bits are set in the spefscr: finv if the contents of r b are +infinity., ?infinity, denorm, or nan, or r b cannot be represented in the target format finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 01011010111 RM0004 instruction set 454/1176 efsctsi efsctsi convert floating-point to signed integer efsctsi r d ,r b rd 32:63 cnvtfp32toisat(rb 32:63 , sign, lower, round, i) the single-precision floating-point value in r b is converted to a signed integer using the current rounding mode. the result saturates if it cannot be represented in a 32-bit integer. nans are converted to 0. the following status bits are set in the spefscr: finv if the contents of r b are +infinity, ?infinit y, denorm, or nan, or r b cannot be represented in the target format finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 01011010101 instruction set RM0004 455/1176 efsctsiz efsctsiz convert floating-point to signed integer with round toward zero efsctsiz r d ,r b rd 32?63 cnvtfp32toisat(rb 32:63 , sign, lower, trunc, i) the single-precision floating-point value in r b is converted to a signed integer using the rounding mode round towards zero. the result saturates if it cannot be represented in a 32- bit integer. nans are converted to 0. scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 01011011010 RM0004 instruction set 456/1176 efsctuf efsctuf convert floating-point to unsigned fraction efsctuf r d ,r b rd 32:63 cnvtfp32toisat(rb 32:63 , unsign, lower, round, f) the single-precision fl oating-point value in r b is converted to an unsigned fraction using the current rounding mode. the result saturates if it cannot be represented in a 32-bit unsigned fraction. nans are converted to 0. the following status bits are set in the spefscr: finv if the contents of r b are +infinity, ?infinit y, denorm, or nan, or r b cannot be represented in the target format finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 01011010110 instruction set RM0004 457/1176 efsctui efsctui convert floating-point to unsigned integer efsctui r d ,r b rd 32:63 cnvtfp32toisat(rb 32:63 , unsign, lower, round, i) the single-precision floating-point value in r b is converted to an unsigned integer using the current rounding mode. the result saturates if it cannot be represented in a 32-bit unsigned integer. nans are converted to 0. the following status bits are set in the spefscr: finv if the contents of r b are +infinity, ?infinit y, denorm, or nan, or r b cannot be represented in the target format finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 01011010100 RM0004 instruction set 458/1176 efsctuiz efsctuiz convert floating-point to unsigned integer with round toward zero efsctuiz r d ,r b rd 32:63 cnvtfp32toisat(rb 32:63 , unsign, lower, trunc, i) the single-precision floating-point value in r b is converted to an unsigned integer using the rounding mode round toward zero. the result saturates if it cannot be represented in a 32- bit unsigned integer. nans are converted to 0. the following status bits are set in the spefscr: finv if the contents of r b are +infinity, ?infinit y, denorm, or nan, or r b cannot be represented in the target format finxs, fg, fx if the result is inexact scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 01011011000 instruction set RM0004 459/1176 efsdiv efsdiv floating-point divide efsdiv r d ,r a ,r b rd 32:63 ra 32:63 sp rb 32:63 the single-precision floating-point value in r a is divided by r b and the result is stored in r d. if an overflow is detected, or r b is a denorm (or 0 value), or r a is a nan or infinity and r b is a normalized number, the result is an appropriately signed maximum floating-point value. if an underflow is detected or rb is a nan or infinity, the result is an appropriately signed floating-point 0. the following status bits are set in the spefscr: finv if the contents of r a or r b are +infinity, ?infinity, denorm, or nan fofv if an overflow occurs funv if an underflow occurs fdbzs, fdbz if a divide by zero occurs finxs, fg, fx if the result is inexact or overflow occurred and overflow exceptions are disabled scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01011001001 RM0004 instruction set 460/1176 efsmul efsmul floating-point multiply efsmul r d ,r a ,r b rd 32:63 ra 32:63 sp rb 32:63 the single-precision floating-point value in r a is multiplied by r b and the result is stored in r d. if an overflow is detected the result is an appropriately signed maximum floating-point value. if one of r a or r b is a nan or an infinity and the other is not a denorm or zero, the result is an appropriately signed maximum floating-point value. if an underflow is detected, or r a or r b is a denorm, the result is an appropriately signed floating-point 0. the following status bits are set in the spefscr: finv if the contents of r a or r b are +infinity, ?infinity, denorm, or nan fofv if an overflow occurs funv if an underflow occurs finxs, fg, fx if the result is inexact or overflow occurred and overflow exceptions are disabled scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01011001000 instruction set RM0004 461/1176 efsnabs efsnabs floating-point negative absolute value efsnabs r d ,r a rd 32:63 0b1 || ra 33:63 the sign bit of r a is set and the result is stored in r d. it is implementation dependent if invalid values for r a (nan, denorm, infinity) are detected and exceptions are taken. scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001011000101 RM0004 instruction set 462/1176 efsneg efsneg floating-point negate efsneg r d ,r a rd 32:63 ?ra 32 || ra 33:63 the sign bit of r a is complemented and the result is stored in r d. it is implementation dependent if invalid values for r a (nan, denorm, infinity) are detected and exceptions are taken. scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001011000110 instruction set RM0004 463/1176 efssub efssub floating-point subtract efssub r d ,r a ,r b rd 32:63 ra 32:63 - sp rb 32:63 the single-precision floating-point value in r b is subtracted from that in r a and the result is stored in r d. if an overflow condition is detected or the contents of r a or r b are nan or infinity, the result is an appropriately signed maximum floating-point value. if an underflow condition is detected, the result is an appropriately signed floating-point 0. the following status bits are set in the spefscr: finv if the contents of r a or r b are +infinity, ?infinity, denorm, or nan fofv if an overflow occurs funf if an underflow occurs finxs, fg, fx if the result is inexact or overflow occurred and overflow exceptions are disabled scalar spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01011000001 RM0004 instruction set 464/1176 efststeq efststeq floating-point test equal efststeq cr d ,r a ,r b al ra 32:63 bl rb 32:63 if (al = bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined the value in r a is compared against r b. if r a equals r b, the bit in cr d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). the comparison treats nans, infinities, and denorms as normalized numbers. no exceptions are taken during execution of efststeq . if strict ieee 754 compliance is required, the program should use efscmpeq . scalar spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 01011011110 instruction set RM0004 465/1176 efststgt efststgt floating-point test greater than efststgt cr d ,r a ,r b al ra 32:63 bl rb 32:63 if (al > bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined if r a is greater than r b, the bit in cr d is set, otherwise it is cl eared. comparison ignores the sign of 0 (+0 = ?0). the comparison treats nans, infinities, and denorms as normalized numbers. no exceptions are taken during the execution of efststgt . if strict ieee 754 complia nce is required, the program should use efscmpgt . scalar spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 01011011100 RM0004 instruction set 466/1176 efststlt efststlt floating-point test less than efststlt cr d ,r a ,r b al ra 32:63 bl rb 32:63 if (al < bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 undefined || cl || undefined || undefined if r a is less than r b, the bit in the cr d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). the comparison treats nans, infinities, and denorms as normalized numbers. no exceptions are taken during the execution of efststlt . if strict ieee 754 compliance is required, the program should use efscmplt . scalar spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 01011011101 instruction set RM0004 467/1176 eqv eqv equivalent eqv r a ,r s ,r b(rc=0) eqv. r a ,r s ,r b(rc=1) result 0:63 rs rb if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result the contents of r s are xored with the contents of r b and the one?s complement of the result is placed into r a. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0100011100rc RM0004 instruction set 468/1176 evabs evabs vector absolute value evabs r d ,r a rd 0:31 abs( ra 0:31 ) rd 32:63 abs( ra 32:63 ) the absolute value of each element of r a is placed in the corresponding elements of r d. an absolute value of 0x8000_0000 (most negative number) returns 0x8000_0000. no overflow is detected. figure 24. vector absolute value (evabs) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001000001000 0313263 r a r d abs abs instruction set RM0004 469/1176 evaddiw evaddiw vector add immediate word evaddiw r d ,r b , uimm rd 0:31 rb 0:31 + extz(uimm ) // modulo sum rd 32:63 rb 32:63 + extz(uimm) // modulo sum uimm is zero-extended and added to both the high and low elements of r b and the results are placed in r d. note that the same value is added to both elements of the register. uimm is 5 bits. figure 25. vector add immediate word (evaddiw) spe apu user 0 5 6 1011 1516 2021 31 000100 r duimm r b 01000000010 0313263 r b uimm + + r d uimm RM0004 instruction set 470/1176 evaddsmiaaw evaddsmiaaw vector add signed, modulo, integer to accumulator word evaddsmiaaw r d ,r a rd 0:31 acc 0:31 + ra 0:31 rd 32:63 acc 32:63 + ra 32:63 acc 0:63 rd 0:63 each word element in r a is added to the corresponding element in the accumulator and the results are placed in r d and into the accumulator. other registers altered: acc figure 26. vector add signed, modulo, integer to accumulator word (evaddsmiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011001 001 0313263 r a accumulator + + r d and accumulator instruction set RM0004 471/1176 evaddssiaaw evaddssiaaw vector add signed, saturate, integer to accumulator word evaddssiaaw r d ,r a // high temp 0:63 exts(acc 0:31 ) + exts(ra 0:31 ) ovh temp 31 temp 32 rd 0:31 saturate(ovh, temp 31 , 0x80000000, 0x7fffffff, temp 32:63 ) // low temp 0:63 exts(acc 32:63 ) + exts(ra 32:63 ) ovl temp 31 temp 32 rd 32:63 saturate(ovl, temp 31 , 0x80000000, 0x7fffffff, temp 32:63 ) acc 0:63 rd 0:63 spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl each signed integer word element in r a is sign-extended and added to the corresponding sign-extended element in the accumulator, saturating if overflow or underflow occurs, and the results are placed in r d and the accumulator. any overflow or underflow is recorded in the spefscr overflow and summary overflow bits. other registers altered: spefscr acc figure 27. vector add signed, saturate, integer to accumulator word (evaddssiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011000001 0313263 r a accumulator + + rd and accumulator RM0004 instruction set 472/1176 evaddumiaaw evaddumiaaw vector add unsigned, modulo, integer to accumulator word evaddumiaaw r d ,r a rd 0:31 acc 0:31 + ra 0:31 rd 32:63 acc 32:63 + ra 32:63 acc 0:63 rd 0:63 each unsigned integer word element in r a is added to the corresponding element in the accumulator and the results are placed in r d and the accumulator. other registers altered: acc figure 28. vector add unsigned, modulo, integer to accumulator word (evaddumiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011001000 0313263 r a accumulator + + r d and accumulator instruction set RM0004 473/1176 evaddusiaaw evaddusiaaw vector add unsigned, saturate, integer to accumulator word evaddusiaaw r d ,r a // high temp 0:63 extz(acc 0:31 ) + extz(ra 0:31 ) ovh temp 31 rd 0:31 saturate(ovh, temp 31 , 0xffffffff, 0xffffffff, temp 32:63 ) // low temp 0:63 extz(acc 32:63 ) + extz(ra 32:63 ) ovl temp 31 rd 32:63 saturate(ovl, temp 31 , 0xffffffff, 0xffffffff, temp 32:63 ) acc 0:63 rd 0:63 spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl each unsigned integer word element in r a is zero-extended and added to the corresponding zero-extended element in the accumulator, saturating if overflow occurs, and the results are placed in r d and the accumulator. any overflow is recorded in the spefscr overflow and summary overflow bits. other registers altered: spefscr acc figure 29. vector add unsigned, saturate, integer to accumulator word (evaddusiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011000000 0313263 r a accumulator + + r d and accumulator RM0004 instruction set 474/1176 evaddw evaddw vector add word evaddw r d ,r a ,r b rd 0:31 ra 0:31 + rb 0:31 // modulo sum rd 32:63 ra 32:63 + rb 32:63 // modulo sum the corresponding elements of r a and r b are added and the results are placed in r d. the sum is a modulo sum. figure 30. vector add word (evaddw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000000000 0313263 r a r b + + r d instruction set RM0004 475/1176 evand evand vector and evand r d ,r a ,r b rd 0:31 ra 0:31 & rb 0:31 // bitwise and rd 32:63 ra 32:63 & rb 32:63 // bitwise and the corresponding elements of r a and r b are anded bitwise and the results are placed in the corresponding element of r d. figure 31. vector and (evand) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000010001 0313263 r a r b & & r d RM0004 instruction set 476/1176 evandc evandc vector and with complement evandc r d ,r a ,r b rd 0:31 ra 0:31 & (?rb 0:31 ) // bitwise andc rd 32:63 ra 32:63 & (?rb 32:63 ) // bitwise andc the word elements of r a and are anded bitwise with the complement of the corresponding elements of r b. the results are placed in the corresponding element of r d. figure 32. vector and with complement (evandc) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000010010 0313263 r a r b and and r d ? ? instruction set RM0004 477/1176 evcmpeq evcmpeq vector compare equal evcmpeq cr d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah = bh) then ch 1 else ch 0 if (al = bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) the most significant bit in cr d is set if the high-order element of r a is equal to the high-order element of r b; it is cleared otherwise. the next bit in cr d is set if the low-order element of r a is equal to the low-order element of r b and cleared otherwise. the last two bits of cr d are set to the or and and of the result of the compare of the high and low elements. figure 33. vector compare equal (evcmpeq) spe apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 01000110100 0313263 r a r b = = cr d or and RM0004 instruction set 478/1176 evcmpgts evcmpgts vector compare greater than signed evcmpgts cr d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah > bh) then ch 1 else ch 0 if (al > bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) the most significant bit in cr d is set if the high-order element of r a is greater than the high- order element of r b; it is cleared otherwise. the next bit in cr d is set if the low-order element of r a is greater than the low-order element of r b and cleared otherwise. the last two bits of cr d are set to the or and and of the result of the compare of the high and low elements. figure 34. vector compare greater than signed (evcmpgts) spe apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 01000110001 0313263 r a r b > > cr d or and instruction set RM0004 479/1176 evcmpgtu evcmpgtu vector compare greater than unsigned evcmpgtu cr d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah >u bh) then ch 1 else ch 0 if (al >u bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) the most significant bit in cr d is set if the high-order element of r a is greater than the high- order element of r b; it is cleared otherwise. the next bit in cr d is set if the low-order element of r a is greater than the low-order element of r b and cleared otherwise. the last two bits of cr d are set to the or and and of the result of the compare of the high and low elements. figure 35. vector compare greater than unsigned (evcmpgtu) spe apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 01000110000 0313263 r a r b > > cr d or and RM0004 instruction set 480/1176 evcmplts evcmplts vector compare less than signed evcmplts cr d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah < bh) then ch 1 else ch 0 if (al < bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) the most significant bit in cr d is set if the high-order element of r a is less than the high- order element of r b; it is cleared otherwise. the next bit in cr d is set if the low-order element of r a is less than the low-order element of r b and cleared otherwise. the last two bits of cr d are set to the or and and of the result of the compare of the high and low elements. figure 36. vector compare less than signed (evcmplts) spe apu user 0 5 6 8 9 1011 1516 2021 31 000100 cr d00 r a r b 01000110011 0313263 r a r b < < cr d or and instruction set RM0004 481/1176 evcmpltu evcmpltu vector compare less than unsigned evcmpltu cr d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah RM0004 instruction set 482/1176 evcntlsw evcntlsw vector count leading signed bits word evcntlsw r d ,r a the leading sign bits in each element of r a are counted, and the respective count is placed into each element of r d. evcntlzw is used for unsigned operands; evcntlsw is used for signed operands. figure 38. vector count leading signed bits word (evcntlsw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001000001110 0313263 r a r d ssss_sss... ssss_sss... count of leading signed bits count of leading signed bits instruction set RM0004 483/1176 evcntlzw evcntlzw vector count leading zeros word evcntlzw r d ,r a the leading zero bits in each element of r a are counted, and the respective count is placed into each element of r d. figure 39. vector count leading zeros word (evcntlzw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001000001101 0313263 r a r d 0000_000... 0000_000... count of leading zeros count of leading zeros RM0004 instruction set 484/1176 evdivws evdivws vector divide word signed evdivws r d ,r a ,r b dividendh ra 0:31 dividendl ra 32:63 divisorh rb 0:31 divisorl rb 32:63 rd 0:31 dividendh divisorh rd 32:63 dividendl divisorl ovh 0 ovl 0 if ((dividendh < 0) & (divisorh = 0)) then rd 0:31 0x80000000 ovh 1 else if ((dividendh >= 0) & (divisorh = 0)) then rd 0:31 0x7fffffff ovh 1 else if ((dividendh = 0x80000000) & (divisorh = 0xffff_ffff)) then rd 0:31 0x7fffffff ovh 1 if ((dividendl < 0) & (divisorl = 0)) then rd 32:63 0x80000000 ovl 1 else if ((dividendl >= 0) & (divisorl = 0)) then rd 32:63 0x7fffffff ovl 1 else if ((dividendl = 0x80000000) & (divisorl = 0xffff_ffff)) then rd 32:63 0x7fffffff ovl 1 spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the two dividends are the two elements of the contents of r a. the two divisors are the two elements of the contents of r b. the resulting two 32-bit quotients on each element are placed into r d. the remainders are not supplied. the operands and quotients are interpreted as signed integers. if overflow, underflow, or divide by zero occurs, the overflow and summary overflow spefscr bits are set. note that any overflow indication is always set as a side effect of this instruction. no form is defined that disables the setting of the overflow bits. in case of overflow, a saturated value is delivered into the destination register. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10011000110 instruction set RM0004 485/1176 figure 40. vector divide word signed (evdivws) 0313263 r a (dividends) rb (divisors) r a/rb r a/rb rd RM0004 instruction set 486/1176 evdivwu evdivwu vector divide word unsigned evdivwu r d ,r a ,r b dividendh ra 0:31 dividendl ra 32:63 divisorh rb 0:31 divisorl rb 32:63 rd 0:31 dividendh divisorh rd 32:63 dividendl divisorl ovh 0 ovl 0 if (divisorh = 0) then rd 0:31 = 0xffffffff ovh 1 if (divisorl = 0) then rd 32:63 0xffffffff ovl 1 spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the two dividends are the two elements of the contents of r a. the two divisors are the two elements of the contents of r b. two 32-bit quotients are formed as a result of the division on each of the high and low elements and the quotients are placed into r d. remainders are not supplied. operands and quotients are interpreted as unsigned integers. if a divide by zero occurs, the overflow and summary overflow spefscr bits are set. note that any overflow indication is always set as a side effect of this instruction. no form is defined that disables the setting of the overflow bits. in case of overflow, a saturated value is delivered into the destination register. figure 41. vector divide word unsigned (evdivwu) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10011000111 0313263 r a (dividends) r b (divisors) r a / r b r a / r b r d instruction set RM0004 487/1176 eveqv eveqv vector equivalent eveqv r d ,r a ,r b rd 0:31 ra 0:31 rb 0:31 // bitwise xnor rd 32:63 ra 32:63 rb 32:63 // bitwise xnor the corresponding elements of r a & r b are xnored bitwise, & the results are placed in r d. figure 42. vector equivalent (eveqv) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000011001 0313263 r a r b xnor xnor r d RM0004 instruction set 488/1176 evextsb evextsb vector extend sign byte evextsb r d ,r a rd 0:31 exts( ra 24:31 ) rd 32:63 exts( ra 56:63 ) the signs of the byte in each of the elements in r a are extended, and the results are placed in r d. figure 43. vector extend sign byte (evextsb) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001000001010 0313263 r a r d s 23 24 55 56 57 s s s ssss_ssss_ssss_ssss_ssss_ssss ssss_ssss_ssss_ssss_ssss_ssss instruction set RM0004 489/1176 evextsh evextsh vector extend sign half word evextsh r d ,r a rd 0:31 exts( ra 16:31 ) rd 32:63 exts( ra 48:63 ) the signs of the half words in each of the elements in r a are extended, and the results are placed in r d. figure 44. vector extend sign half word (evextsh) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001000001011 0313263 r a r d s s s s ssss_ssss_ssss_ssss ssss_ssss_ssss_ssss 15 16 17 47 48 49 RM0004 instruction set 490/1176 evfsabs evfsabs vector floating-point single-precision absolute value evfsabs r d ,r a rd 0:31 0b0 || ra 1:31 rd 32:63 0b0 || ra 33:63 the sign bit of each element in r a is set to 0 and the results are placed into r d. exceptions: exception detection for embedded floating-point absolute value operations is implementation dependent. an implementation may choose to not detect exceptions and carry out the computation. if the implementation does not detect exceptions, or if exception detection is disabled, the computation can be carried out in one of two ways, as a sign bit operation ignoring the rest of the contents of the source register, or by examining the input and appropriately saturating the input prior to performing the operation. if an implementation chooses to handle exceptions, the exception is handled as follows: if the contents of either element of r a are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriately, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if floating- point invalid input exceptions are enabled, an interrupt is taken and the destination register is not updated. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001010000100 instruction set RM0004 491/1176 evfsadd evfsadd vector floating-point single-precision add evfsadd r d ,r a ,r b rd 0:31 ra 0:31 + sp rb 0:31 rd 32:63 ra 32:63 + sp rb 32:63 each single-precision floating-point element of r a is added to the corresponding element of r b and the results are stored in r d. if an element of r a is nan or infinity, the corresponding result is either pmax ( a sign ==0 ), or nmax ( a sign ==1 ). otherwise, if an element of r b is nan or infinity, the corresponding result is either pmax ( b sign ==0 ), or nmax ( b sign ==1 ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in the corresponding element of r d. if an underflow occurs, +0 (for rounding modes rn, rz, rp) or ?0 (for rounding mode rm) is stored in the corresponding element of r d. exceptions: if the contents of either element of r a or r b are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[fi nve] is set, an interrupt is taken and the destination register is not update d. otherwise, if an overflow o ccurs, spefscr[fovf,fovfh] are set appropriately, or if an underflow occurs, spefscr[funf,funfh] are set appropriately. if either underflow or overflow exceptions are enabled and a corresponding status bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if either result element of this instruction is inexact, or overflows but overflow exceptions are disabled, and no other interrupt is taken, or underflows but underflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs,finxsh] is set. if the floating- point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx (fgh and fxh) are cleared if an overflow or underflow interrupt is taken, or if an invalid operation/input error is signaled for the low (high) element (regardless of finve). vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01010000000 RM0004 instruction set 492/1176 evfscfsf evfscfsf vector convert floating-point single-precision from signed fraction evfscfsf r d ,r b rd 0:31 cnvti32tofp32sat(rb 0:31 , sign, upper, f) rd 32:63 cnvti32tofp32sat(rb 32:63 , sign, lower, f) each signed fractional element of r b is converted to a single-precision floating-point value using the current rounding mode and the results are placed into the corresponding elements of r d. exceptions: this instruction can signal an inexact stat us and set spefscr[finxs] if the conversions are not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 0 1 1 instruction set RM0004 493/1176 evfscfsi evfscfsi vector convert floating-point single-precision from signed integer evfscfsi r d ,r b rd 0:31 cnvtsi32tofp32sat(rb 0:31 , sign, upper, i) rd 32:63 cnvtsi32tofp32sat(rb 32:63 , sign, lower, i) each signed integer element of r b is converted to the nearest single-precision floating-point value using the current rounding mode and the results are placed into the corresponding element of r d. exceptions: this instruction can signal an inexact stat us and set spefscr[finxs] if the conversions are not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 0 0 1 RM0004 instruction set 494/1176 evfscfuf evfscfuf vector convert floating-point single-precision from unsigned fraction evfscfuf r d ,r b rd 0:31 cnvti32tofp32sat(rb 0:31 , unsign, upper, f) rd 32:63 cnvti32tofp32sat(rb 32:63 , unsign, lower, f) each unsigned fractional element of r b is converted to a single-precision floating-point value using the current rounding mode and the results are placed into the corresponding elements of r d. exceptions: this instruction can signal an inexact stat us and set spefscr[finxs] if the conversions are not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 0 1 0 instruction set RM0004 495/1176 evfscfui evfscfui vector convert floating-point single-precision from unsigned integer evfscfui r d ,r b rd 0:31 cnvti32tofp32sat(rb 031 , unsign, upper, i) rd 32:63 cnvti32tofp32sat(rb 32:63 , unsign, lower, i) each unsigned integer element of r b is converted to the nearest single-precision floating- point value using the current rounding mode and the results are placed into the corresponding elements of r d. exceptions: this instruction can signal an inexact stat us and set spefscr[finxs] if the conversions are not exact. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 0 0 0 RM0004 instruction set 496/1176 evfscmpeq evfscmpeq vector floating-point single-precision compare equal evfscmpeq crf d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah = bh) then ch 1 else ch 0 if (al = bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) each element of r a is compared against the corresponding element of r b. if r a equals r b, the crf d bit is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). exceptions: if the contents of either element of r a or r b are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if floating-point invalid input exceptions are enabled, an interrupt is taken, and the condition register is not updated. otherwise, the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. vector spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1 0 1 0 0 0 1 1 1 0 instruction set RM0004 497/1176 evfscmpgt evfscmpgt vector floating-point single-precision compare greater than evfscmpgt crf d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah > bh) then ch 1 else ch 0 if (al > bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) each element of r a is compared against the corresponding element of r b. if r a is greater than r b, the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). exceptions: if the contents of either element of r a or r b are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if floating-point invalid input exceptions are enabled then an interrupt is taken, and the condition register is not updated. otherwise, the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. vector spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1 0 1 0 0 0 1 1 0 0 RM0004 instruction set 498/1176 evfscmplt evfscmplt vector floating-point single-precision compare less than evfscmplt crf d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah < bh) then ch 1 else ch 0 if (al < bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) each element of r a is compared against the corresponding element of r b. if r a is less than r b, the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ? 0). exceptions: if the contents of either element of r a or r b are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if floating-point invalid input exceptions are enabled then an interrupt is taken, and the condition register is not updated. otherwise, the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. vector spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1 0 1 0 0 0 1 1 0 1 instruction set RM0004 499/1176 evfsctsf evfsctsf vector convert floating-point single-precision to signed fraction evfsctsf r d ,r b rd 0:31 cnvtfp32toisat(rb 0:31 , sign, upper, round, f) rd 32:63 cnvtfp32toisat(rb 32:63 , sign, lower, round, f) each single-precision floating-point element in r b is converted to a signed fraction using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit signed fraction. nans are converted as though they were zero. exceptions: if either element of r b is infinity, denorm, or nan, or if an overflow occurs, spefscr[finv,finvh] are set app ropriately and spefscr[fg h,fxh,fg,fx] are cleared appropriately. if spefscr[finve] is set, an interrupt is taken, the destination register is not updated, and no other status bits are set. if either result element of this instruction is inexact and no other interrupt is taken, spefscr[finxs] is set. if the fl oating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result. the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 1 1 1 RM0004 instruction set 500/1176 evfsctsi evfsctsi vector convert floating-point single-precision to signed integer evfsctsi r d ,r b rd 0:31 cnvtfp32toisat(rb 0:31 , sign, upper, round, i) rd 32:63 cnvtfp32toisat(rb 32:63 , sign, lower, round, i) each single-precision floating-point element in r b is converted to a signed integer using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if the contents of either element of r b are infinity, denorm, or nan, or if an overflow occurs on conversion, spefscr[finv,finvh ] are set approp riately, and spefscr[fgh,fxh,fg,fx] are cl eared appropriately. if spe fscr[finve] is set, an interrupt is taken, the destination register is not updated, and no other status bits are set. if either result element of this instruction is inexact and no other interrupt is taken, spefscr[finxs] is set. if the fl oating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result. the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 1 0 1 instruction set RM0004 501/1176 evfsctsiz evfsctsiz vector convert floating-point single-precision to signed integer with round toward zero evfsctsiz r d ,r b rd 0:31 cnvtfp32toisat(rb 0:31 , sign, upper, trunc, i) rd 32:63 cnvtfp32toisat(rb 32:63 , sign, lower, trunc, i) each single-precision floating-point element in r b is converted to a signed integer using the rounding mode round toward zero and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if either element of r b is infinity, denorm, or nan, or if an overflow occurs, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[ finve] is set, an interrup t is taken, th e destination register is not updated, and no other status bits are set. if either result element of this instruction is inexact and no other interrupt is taken, spefscr[finxs] is set. if the fl oating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result. the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 1 0 1 0 RM0004 instruction set 502/1176 evfsctuf evfsctuf vector convert floating-point single-precision to unsigned fraction evfsctuf r d ,r b rd 0:31 cnvtfp32toisat(rb 0:31 , unsign, upper, round, f) rd 32:63 cnvtfp32toisat(rb 32:63 , unsign, lower, round, f) each single-precision floating-point element in r b is converted to an unsigned fraction using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit fraction. nans are converted as though they were zero. exceptions: if either element of r b is infinity, denorm, or nan, or if an overflow occurs, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[ finve] is set, an interrup t is taken, th e destination register is not updated, and no other status bits are set. if either result element of this instruction is inexact and no other interrupt is taken, spefscr[finxs] is set. if the fl oating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result. the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 1 1 0 instruction set RM0004 503/1176 evfsctui evfsctui vector convert floating-point single-precision to unsigned integer evfsctui r d ,r b rd 0:31 cnvtfp32toisat(rb 0:31 , unsign, upper, round, i) rd 32:63 cnvtfp32toisat(rb 32:63 , unsign, lower, round, i) each single-precision floating-point element in r b is converted to an unsigned integer using the current rounding mode and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if either element of r b is infinity, denorm, or nan, or if an overflow occurs, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[ finve] is set, an interrup t is taken, th e destination register is not updated, and no other status bits are set. if either result element of this instruction is inexact and no other interrupt is taken, spefscr[finxs] is set. if the fl oating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result. the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 0 1 0 0 RM0004 instruction set 504/1176 evfsctuiz evfsctuiz vector convert floating-point single-precision to unsigned integer with round toward zero evfsctuiz r d ,r b rd 0:31 cnvtfp32toisat(rb 0:31 , unsign, upper, trunc, i) rd 32:63 cnvtfp32toisat(rb 32:63 , unsign, lower, trunc, i) each single-precision floating-point element in r b is converted to an unsigned integer using the rounding mode round toward zero and the result is saturated if it cannot be represented in a 32-bit integer. nans are converted as though they were zero. exceptions: if either element of r b is infinity, denorm, or nan, or if an overflow occurs, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[ finve] is set, an interrup t is taken, th e destination register is not updated, and no other status bits are set. if either result element of this instruction is inexact and no other interrupt is taken, spefscr[finxs] is set. if the fl oating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result. the fgh, fxh, fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d 00000 r b 0 1 0 1 0 0 1 1 0 0 0 instruction set RM0004 505/1176 evfsdiv evfsdiv vector floating-point single-precision divide evfsdiv r d ,r a ,r b rd 0:31 ra 0:31 sp rb 0:31 rd 32:63 ra 32:63 sp rb 32:63 each single-precision floating-point element of r a is divided by the corresponding element of r b and the result is stored in r d. if an element of r b is a nan or infinity, the corresponding result is a properly signed zero. otherwise, if an element of r b is a zero (or a denormalized number optionally transformed to zero by the implementation), or if an element of r a is either nan or infinity, the corresponding result is either pmax ( a sign ==b sign ), or nmax ( a sign !=b sign ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in the corresponding element of r d. if an underflow occurs, +0 or ?0 (as appropriate) is stored in the corresponding element of r d. exceptions: if the contents of r a or r b are infinity, denorm, or nan, or if both r a and r b are 0, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[fi nve] is set, an interrupt is taken and the destination register is not updated. otherwise, if the content of r b is 0 and the content of r a is a finite normalized non-zero number, spefscr[fdbz,fdb zh] are set appropriately. if floating- point divide-by-zero exceptions are enabled, an interrupt is then taken. otherwise, if an overflow occurs, spefscr[fovf,fovfh] are set ap propriately, or if an underflow occurs, spefscr[funf,funfh] are set appropriately. if either underflow or overflow exceptions are enabled and a corresponding bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if either result element of this instruction is inexact, or overflows but overflow exceptions are disabled, and no other interrupt is taken, or underflows but underflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs] is set. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx (fgh and fxh) are cleared if an overflow or underflow interrupt is taken, or if an invalid operation/input error is signaled for the low (high) element (regardless of finve). vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01010001001 RM0004 instruction set 506/1176 evfsmul evfsmul vector floating-point single-precision multiply evfsmul r d ,r a ,r b rd 0:31 ra 0:31 sp rb 0:31 rd 32:63 ra 32:63 sp rb 32:63 each single-precision floating-point element of r a is multiplied with the corresponding element of r b and the result is stored in r d. if an element of r a or r b are either zero (or a denormalized number optionally transformed to zero by the implementation), the corresponding result is a properly signed zero. otherwise, if an element of r a or r b are either nan or infinity, the corresponding result is either pmax ( a sign ==b sign ), or nmax ( a sign !=b sign ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in the corresponding element of r d. if an underflow occurs, +0 or ?0 (as appropriate) is stored in the corresponding element of r d. exceptions: if the contents of either element of r a or r b are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[fi nve] is set, an interrupt is taken and the destination register is not update d. otherwise, if an overflow o ccurs, spefscr[fovf,fovfh] are set appropriately, or if an underflow occurs, spefscr[funf,funfh] are set appropriately. if either underflow or overflow exceptions are enabled and a corresponding status bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if either result element of this instruction is inexact, or overflows but overflow exceptions are disabled, and no other interrupt is taken, or underflows but underflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs] is set. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx (fgh and fxh) are cleared if an overflow or underflow exception is taken, or if an invalid operation/input error is signaled for the low (high) element (regardless of finve). vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01010001000 instruction set RM0004 507/1176 evfsnabs evfsnabs vector floating-point single-precision negative absolute value evfsnabs r d ,r a rd 0:31 0b1 || ra 1:31 rd 32:63 0b1 || ra 33:63 the sign bit of each element in r a is set to 1 and the results are placed into r d. exceptions: exception detection for embedded floating-point absolute value operations is implementation dependent. an implementation may choose to not detect exceptions and carry out the sign bit operation. if the implementation does not detect exceptions, or if exception detection is disabled, the computation can be carried out in one of two ways, as a sign bit operation ignoring the rest of the contents of the source register, or by examining the input and appropriately saturating the input prior to performing the operation. if an implementation chooses to handle exceptions, the exception is handled as follows: if the contents of either element of r a are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriately, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if floating- point invalid input exceptions are enabled then an interrupt is taken, and the destination register is not updated. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001010000101 RM0004 instruction set 508/1176 evfsneg evfsneg vector floating-point single-precision negate evfsneg r d ,r a rd 0:31 ?ra 0 || ra 1:31 rd 32:63 ?ra 32 || ra 33:63 the sign bit of each element in r a is complemented and the results are placed into r d. exceptions: exception detection for embedded floating-point absolute value operations is implementation dependent. an implementation may choose to not detect exceptions and carry out the sign bit operation. if the implementation does not detect exceptions, or if exception detection is disabled, the computation can be carried out in one of two ways, as a sign bit operation ignoring the rest of the contents of the source register, or by examining the input and appropriately saturating the input prior to performing the operation. if an implementation chooses to handle exceptions, the exception is handled as follows: if the contents of either element of r a are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriately, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if floating- point invalid input exceptions are enabled then an interrupt is taken, and the destination register is not updated. vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001010000110 instruction set RM0004 509/1176 evfssub evfssub vector floating-point single-precision subtract evfssub r d ,r a ,r b rd 0:31 ra 0:31 - sp rb 0:31 rd 32:63 ra 32:63 - sp rb 32:63 each single-precision floating-point element of r b is subtracted from the corresponding element of r a and the results are stored in r d. if an element of r a is nan or infinity, the corresponding result is either pmax ( a sign ==0 ), or nmax ( a sign ==1 ). otherwise, if an element of r b is nan or infinity, the corresponding result is either nmax ( b sign ==0 ), or pmax ( b sign ==1 ). otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in the corresponding element of r d. if an underflow occurs, +0 (for rounding modes rn, rz, rp) or ?0 (for rounding mode rm) is stored in the corresponding element of r d. exceptions: if the contents of either element of r a or r b are infinity, denorm, or nan, spefscr[finv,finvh] are set appropriat ely, and spefscr[fgh,fxh,fg,fx] are cleared appropriately. if spefscr[fi nve] is set, an interrupt is taken and the destination register is not update d. otherwise, if an overflow o ccurs, spefscr[fovf,fovfh] are set appropriately, or if an underflow occurs, spefscr[funf,funfh] are set appropriately. if either underflow or overflow exceptions are enabled and a corresponding status bit is set, an interrupt is taken. if any of these interrupts are taken, the destination register is not updated. if either result element of this instruction is inexact, or overflows but overflow exceptions are disabled, and no other interrupt is taken, or underflows but underflow exceptions are disabled, and no other interrupt is taken, spefscr[finxs] is set. if the floating-point inexact exception is enabled, an interrupt is taken using the floating-point round interrupt vector. in this case, the destination register is updated with the truncated result(s). the fg and fx bits are properly updated to allow rounding to be performed in the interrupt handler. fg and fx (fgh and fxh) are cleared if an overflow or underflow interrupt is taken, or if an invalid operation/input error is signaled for the low (high) element (regardless of finve). vector spfp apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01010000001 RM0004 instruction set 510/1176 evfststeq evfststeq vector floating-point single-precision test equal evfststeq crf d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah = bh) then ch 1 else ch 0 if (al = bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) each element of r a is compared against the corresponding element of r b. if r a equals r b, the bit in crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. no exceptions are taken during the execution of evfststeq . if strict ieee 754 compliance is required, the program should use evfscmpeq . implementation note: in an implementation, the execution of evfststeq is likely to be faster than the execution of evfscmpeq . vector spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1 0 1 0 0 1 1 1 1 0 instruction set RM0004 511/1176 evfststgt evfststgt vector floating-point single-precision test greater than evfststgt crf d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah > bh) then ch 1 else ch 0 if (al > bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) each element of r a is compared against the corresponding element of r b. if r a is greater than r b, the bit in crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. no exceptions are taken during the execution of evfststgt . if strict ieee 754 compliance is required, the program should use evfscmpgt . implementation note: in an implementation, the execution of evfststgt is likely to be faster than the execution of evfscmpgt . vector spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1 0 1 0 0 1 1 1 0 0 RM0004 instruction set 512/1176 evfststlt evfststlt vector floating-point single-precision test less than evfststlt crf d ,r a ,r b ah ra 0:31 al ra 32:63 bh rb 0:31 bl rb 32:63 if (ah < bh) then ch 1 else ch 0 if (al < bl) then cl 1 else cl 0 cr 4*crd:4*crd+3 ch || cl || (ch | cl) || (ch & cl) each element of r a is compared with the corresponding element of r b. if r a is less than r b, the bit in the crf d is set, otherwise it is cleared. comparison ignores the sign of 0 (+0 = ?0). the comparison proceeds after treating nans, infinities, and denorms as normalized numbers, using their values of ? e ? and ? f ? directly. no exceptions are taken during the execution of evfststlt . if strict ieee 754 compliance is required, the program should use evfscmplt . implementation note: in an implementation, the execution of evfststlt is likely to be faster than the execution of evfscmplt . vector spfp apu user 0 5 6 8 9 1011 1516 2021 31 000100 crf d00 r a r b 0 1 0 1 0 0 1 1 1 0 1 instruction set RM0004 513/1176 evldd evldd vector load double word into double word evldd r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*8) rd mem(ea, 8) the double word addressed by ea is loaded from memory and placed in r d. figure 45 shows how bytes are loaded into r d as determined by the endian mode. figure 45. evldd results in big- and little-endian modes implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe, vector spfp, scalar dpfp apus user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100000001 1. d = uimm * 8 cde f h 01234567 ab g cde f h ab g fedc a hg b memory gpr in big endian gpr in little endian byte address RM0004 instruction set 514/1176 evlddx evlddx vector load double word into double word indexed evlddx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd mem(ea, 8) the double word addressed by ea is loaded from memory and placed in r d. figure 46 shows how bytes are loaded into r d as determined by the endian mode. figure 46. evlddx results in big- and little-endian modes implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe, vector spfp, scalar dpfp apus user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100000000 cde f h 01234567 ab g cde f h ab g fedc a hg b memory gpr in big endian gpr in little endian byte address instruction set RM0004 515/1176 evldh evldh vector load double into four half words evldh r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*8) rd 0:15 mem(ea, 2) rd 16:31 mem(ea+2,2) rd 32:47 mem(ea+4,2) rd 48:63 mem(ea+6,2) the double word addressed by ea is loaded from memory and placed in r d. the figure below shows how bytes are loaded into r d as determined by the endian mode. evldh results in big- and little-endian modes implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100000101 1. d = uimm * 8 cde f h 01234567 ab g cde f h ab g dc f e g ba h memory gpr in big endian gpr in little endian byte address RM0004 instruction set 516/1176 evldhx evldhx vector load double into four half words indexed evldhx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:15 mem(ea, 2) rd 16:31 mem(ea+2,2) rd 32:47 mem(ea+4,2) rd 48:63 mem(ea+6,2) the double word addressed by ea is loaded from memory and placed in r d. figure 47 shows how bytes are loaded into r d as determined by the endian mode. figure 47. evldhx results in big- and little-endian modes implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100000100 cde f h 01234567 ab g cde f h ab g dc f e g ba h memory gpr in big endian gpr in little endian byte address instruction set RM0004 517/1176 evldw evldw vector load double into two words evldw r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*8) rd 0:31 mem(ea, 4) rd 32:63 mem(ea+4, 4) the double word addressed by ea is loaded from memory and placed in r d. figure 48 shows how bytes are loaded into r d as determined by the endian mode. figure 48. evldw results in big- and little-endian modes implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100000011 1. d = uimm * 8 cde f h 01234567 ab g cde f h ab g bahg e dc f memory gpr in big endian gpr in little endian byte address RM0004 instruction set 518/1176 evldwx evldwx vector load double into two words indexed evldwx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:31 mem(ea, 4) rd 32:63 mem(ea+4, 4) the double word addressed by ea is loaded from memory and placed in r d. figure 49 shows how bytes are loaded into r d as determined by the endian mode. figure 49. evldwx results in big- and little-endian modes implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100000010 cde f h 01234567 ab g cde f h ab g bahg e dc f memory gpr in big endian gpr in little endian byte address instruction set RM0004 519/1176 evlhhesplat evlhhesplat vector load half word into half words even and splat evlhhesplat r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*2) rd 0:15 mem(ea,2) rd 16:31 0x0000 rd 32:47 mem(ea,2) rd 48:63 0x0000 the half word addressed by ea is loaded from memory and placed in the even half words of each element of r d. figure 50 shows how bytes are loaded into r d as determined by the endian mode. figure 50. evlhhesplat results in big- and little-endian modes implementation note: if the ea is not half-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100001001 1. d = uimm * 2 0 ab zzab z ab z zzba z ba z memory gpr in big endian gpr in little endian byte address z = zero z = zero RM0004 instruction set 520/1176 evlhhesplatx evlhhesplatx vector load half word into half words even and splat indexed evlhhesplatx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:15 mem(ea,2) rd 16:31 0x0000 rd 32:47 mem(ea,2) rd 48:63 0x0000 the half word addressed by ea is loaded from memory and placed in the even half words of each element of r d. figure 51 shows how bytes are loaded into r d as determined by the endian mode. figure 51. evlhhesplatx results in big- and little-endian modes implementation note: if the ea is not half-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100001000 01 ab zzab z ab z zzba z ba z memory gpr in big endian gpr in little endian byte address z = zero z = zero instruction set RM0004 521/1176 evlhhossplat evlhhossplat vector load half word into half word odd signed and splat evlhhossplat r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*2) rd 0:31 exts(mem(ea,2)) rd 32:63 exts(mem(ea,2)) the half word addressed by ea is loaded from memory and placed in the odd half words sign extended in each element of r d. figure 52 shows how bytes are loaded into r d as determined by the endian mode. figure 52. evlhhossplat results in big- and little-endian modes in big-endian memory, the msb of a is sign exte nded. in little-endian memory, the msb of b is sign extended. implementation note: if the ea is not half-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100001111 1. d = uimm * 2 01 ab abss b ss a bass a ss b memory gpr in big endian gpr in little endian byte address s = sign s = sign RM0004 instruction set 522/1176 evlhhossplatx evlhhossplatx vector load half word into half word odd signed and splat indexed evlhhossplatx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:31 exts(mem(ea,2)) rd 32:63 exts(mem(ea,2)) the half word addressed by ea is loaded from memory and placed in the odd half words sign extended in each element of r d. figure 53 shows how bytes are loaded into r d as determined by the endian mode. figure 53. evlhhossplatx results in big- and little-endian modes in big-endian memory, the msb of a is sign exte nded. in little-endian memory, the msb of b is sign extended. implementation note: if the ea is not half-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100001110 01 ab abss b ss a bass a ss b memory gpr in big endian gpr in little endian byte address s = sign s = sign instruction set RM0004 523/1176 evlhhousplat evlhhousplat vector load half word into half word odd unsigned and splat evlhhousplat r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*2) rd 0:15 0x0000 rd 16:31 mem(ea,2) rd 32:47 0x0000 rd 48:63 mem(ea,2) the half word addressed by ea is loaded from memory and placed in the odd half words zero extended in each element of r d. figure 54 shows how bytes are loaded into r d as determined by the endian mode. figure 54. evlhhousplat results in big- and little-endian modes implementation note: if the ea is not half-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100001101 1. d = uimm * 2 01 ab abzz b zz a bazz a zz b memory gpr in big endian gpr in little endian byte address z = zero z = zero RM0004 instruction set 524/1176 evlhhousplatx evlhhousplatx vector load half word into half word odd unsigned and splat indexed evlhhousplatx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:15 0x0000 rd 16:31 mem(ea,2) rd 32:47 0x0000 rd 48:63 mem(ea,2) the half word addressed by ea is loaded from memory and placed in the odd half words zero extended in each element of r d. figure 55 shows how bytes are loaded into r d as determined by the endian mode. figure 55. evlhhousplatx results in big- and little-endian modes implementation note: if the ea is not half-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100001100 01 ab abzz b zz a bazz a zz b memory gpr in big endian gpr in little endian byte address z = zero z = zero instruction set RM0004 525/1176 evlwhe evlwhe vector load word into two half words even evlwhe r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) rd 0:15 mem(ea,2) rd 16:31 0x0000 rd 32:47 mem(ea+2,2) rd 48:63 0x0000 the word addressed by ea is loaded from memory and placed in the even half words in each element of r d. figure 56 shows how bytes are loaded into r d as determined by the endian mode. figure 56. evlwhe results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100010001 1. d = uimm * 4 cd 0123 ab zzcd z ab z zzdc z ba z memory gpr in big endian gpr in little endian byte address z = zero z = zero RM0004 instruction set 526/1176 evlwhex evlwhex vector load word into two half words even indexed evlwhex r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:15 mem(ea,2) rd 16:31 0x0000 rd 32:47 mem(ea+2,2) rd 48:63 0x0000 the word addressed by ea is loaded from memory and placed in the even half words in each element of r d. figure 57 shows how bytes are loaded into r d as determined by the endian mode. figure 57. evlwhex results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100010000 cd 0123 ab zzcd z ab z zzdc z ba z memory gpr in big endian gpr in little endian byte address z = zero z = zero instruction set RM0004 527/1176 evlwhos evlwhos vector load word into two half words odd signed (with sign extension) evlwhos r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) rd 0:31 exts(mem(ea,2)) rd 32:63 exts(mem(ea+2,2)) the word addressed by ea is loaded from memory and placed in the odd half words sign extended in each element of r d. figure 58 shows how bytes are loaded into r d as determined by the endian mode. figure 58. evlwhos results in big- and little-endian modes in big-endian memory, the most significant bits of a and c are sign extended. in little-endian memory, the most significant bits of b and d are sign extended. implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100010111 1. d = uimm * 4 cd 0123 ab abss d ss c bass c ss d memory gpr in big endian gpr in little endian byte address s = sign s = sign RM0004 instruction set 528/1176 evlwhosx evlwhosx vector load word into two half words odd signed indexed (with sign extension) evlwhosx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:31 exts(mem(ea,2)) rd 32:63 exts(mem(ea+2,2)) the word addressed by ea is loaded from memory and placed in the odd half words sign extended in each element of r d. figure 59 shows how bytes are loaded into r d as determined by the endian mode. figure 59. evlwhosx results in big- and little-endian modes in big-endian memory, the most significant bits of a and c are sign extended. in little-endian memory, the most significant bits of b and d are sign extended. implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100010110 cd 0123 ab abss d ss c bass c ss d memory gpr in big endian gpr in little endian byte address s = sign s = sign instruction set RM0004 529/1176 evlwhou evlwhou vector load word into two half words odd unsigned (zero-extended) evlwhou r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) rd 0:15 0x0000 rd 16:31 mem(ea,2) rd 32:47 0x0000 rd 48:63 mem(ea+2,2) the word addressed by ea is loaded from memory and placed in the odd half words zero extended in each element of r d. figure 60 shows how bytes are loaded into r d as determined by the endian mode. figure 60. evlwhou results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100010101 1. d = uimm * 4 cd 0123 ab abzz d zz c bazz c zz d memory gpr in big endian gpr in little endian byte address z = zero z = zero RM0004 instruction set 530/1176 evlwhoux evlwhoux vector load word into two half words odd unsigned indexed (zero-extended) evlwhoux r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:15 0x0000 rd 16:31 mem(ea,2) rd 32:47 0x0000 rd 48:63 mem(ea+2,2) the word addressed by ea is loaded from memory and placed in the odd half words zero extended in each element of r d. figure 61 shows how bytes are loaded into r d as determined by the endian mode. figure 61. evlwhoux results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100010100 cd 0123 ab abzz d zz c bazz c zz d memory gpr in big endian gpr in little endian byte address z = zero z = zero instruction set RM0004 531/1176 evlwhsplat evlwhsplat vector load word into two half words and splat evlwhsplat r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) rd 0:15 mem(ea,2) rd 16:31 mem(ea,2) rd 32:47 mem(ea+2,2) rd 48:63 mem(ea+2,2) the word addressed by ea is loaded from memory and placed in both the even and odd half words in each element of r d. figure 62 shows how bytes are loaded into r d as determined by the endian mode. figure 62. evlwhsplat results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100011101 1. d = uimm * 4 cd 0123 ab abcd d ab c badc c ba d memory gpr in big endian gpr in little endian byte address RM0004 instruction set 532/1176 evlwhsplatx evlwhsplatx vector load word into two half words and splat indexed evlwhsplatx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:15 mem(ea,2) rd 16:31 mem(ea,2) rd 32:47 mem(ea+2,2) rd 48:63 mem(ea+2,2) the word addressed by ea is loaded from memory and placed in both the even and odd half words in each element of r d. figure 63 shows how bytes are loaded into r d as determined by the endian mode. figure 63. evlwhsplatx results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100011100 cd 0123 ab abcd d ab c badc c ba d memory gpr in big endian gpr in little endian byte address instruction set RM0004 533/1176 evlwwsplat evlwwsplat vector load word into word and splat evlwwsplat r d ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) rd 0:31 mem(ea,4) rd 32:63 mem(ea,4) the word addressed by ea is loaded from memory and placed in both elements of r d. figure 64 shows how bytes are loaded into r d as determined by the endian mode. figure 64. evlwwsplat results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r auimm (1) 01100011001 1. d = uimm * 4 cd 0123 ab cdab d ab c badc a dc b memory gpr in big endian gpr in little endian byte address RM0004 instruction set 534/1176 evlwwsplatx evlwwsplatx vector load word into word and splat indexed evlwwsplatx r d ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) rd 0:31 mem(ea,4) rd 32:63 mem(ea,4) the word addressed by ea is loaded from memory and placed in both elements of r d. figure 65 shows how bytes are loaded into r d as determined by the endian mode. figure 65. evlwwsplatx results in big- and little-endian modes implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01100011000 cd 0123 ab cdab d ab c badc a dc b memory gpr in big endian gpr in little endian byte address instruction set RM0004 535/1176 evmergehi evmergehi vector merge high evmergehi r d ,r a ,r b rd 0:31 ra 0:31 rd 32:63 rb 0:31 the high-order elements of r a and r b are merged and placed into r d, as shown in figure 66 . figure 66. high order element merging (evmergehi) note: a vector splat high can be performed by specifying the same register in r a and r b. spe, ve;ctor spfp, scalar dpfp apus user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000101100 0313263 r a r b r d RM0004 instruction set 536/1176 evmergehilo evmergehilo vector merge high/low evmergehilo r d ,r a ,r b rd 0:31 ra 0:31 rd 32:63 rb 32:63 the high-order element of r a and the low-order element of r b are merged and placed into r d, as shown in figure 67 . figure 67. high order element merging (evmergehilo) application note: with appropriate specification of r a and r b, evmergehi , evmergelo , evmergehilo , and evmergelohi provide a full 32-bit permute of two source operands. spe, vector spfp, scalar dpfp apus user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000101110 0313263 r a r b r d instruction set RM0004 537/1176 evmergelo evmergelo vector merge low evmergelo r d ,r a ,r b rd 0:31 ra 32:63 rd 32:63 rb 32:63 the low-order elements of r a and r b are merged and placed in r d, as shown in figure 68 . figure 68. low order element merging (evmergelo) note: a vector splat low can be performed by specifying the same register in r a and r b. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000101101 0313263 r a r b r d RM0004 instruction set 538/1176 evmergelohi evmergelohi vector merge low/high evmergelohi r d ,r a ,r b rd 0:31 ra 32:63 rd 32:63 rb 0:31 the low-order element of r a and the high-order element of r b are merged and placed into r d, as shown in figure 69 . figure 69. low order element merging (evmergelohi) note: a vector swap can be performed by specifying the same register in r a and r b. spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000101111 0313263 r a r b r d instruction set RM0004 539/1176 evmhegsmfaa evmhegsmfaa vector multiply half words, even, guarded, signed, modulo, fractional and accumulate evmhegsmfaa r d ,r a ,r b temp 0:31 ra 32:47 sf rb 32:47 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low even-numbered, half-word signed fractional elements in r a and r b are multiplied. the product is added to the contents of the 64-bit accumulator and the result is placed into r d and the accumulator. note: this is a modulo sum. there is no overflow check and no saturation is performed. any overflow of the 64-bit sum is not recorded in to the spefscr. figure 70. evmhegsmfaa (even form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100101011 47 48 0313263 intermediate product accumulator r b x + r d and accumulator r a ssss_ssss_ssss_ssss...ssss RM0004 instruction set 540/1176 evmhegsmfan evmhegsmfan vector multiply half words, even, guarded, signed, modulo, fractional and accumulate negative evmhegsmfan r d ,r a ,r b temp 0:31 ra 32:47 sf rb 32:47 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low even-numbered, half-word signed fractional elements in r a and r b are multiplied. the product is subtracted from the contents of the 64-bit accumulator and the result is placed into r d and the accumulator. note: this is a modulo difference. there is no overflow check and no saturation is performed. any overflow of the 64-bit difference is not reco rded into the spefscr. figure 71. evmhegsmfan (even form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110101011 47 48 0313263 intermediate product accumulator r b x ? r d and accumulator r a ssss_ssss_ssss_ssss...sss instruction set RM0004 541/1176 evmhegsmiaa evmhegsmiaa vector multiply half words, even, guarded, signed, modulo, integer and accumulate evmhegsmiaa r d ,r a ,r b temp 0:31 ra 32:47 si rb 32:47 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low even-numbered half-word signed integer elements in r a and r b are multiplied. the intermediate product is sign-extended and added to the contents of the 64- bit accumulator, and the resu lting sum is placed into r d and into the accumulator. note: this is a modulo sum. there is no overflow check and no saturation is performed. any overflow of the 64-bit sum is not recorded in to the spefscr. figure 72. evmhegsmiaa (even form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100101001 47 48 0313263 intermediate product accumulator r b x + r d and accumulator r a ssss_ssss_ssss_ssss...ssss RM0004 instruction set 542/1176 evmhegsmian evmhegsmian vector multiply half words, even, guarded, signed, modulo, integer and accumulate negative evmhegsmian r d ,r a ,r b temp 0:31 ra 32:47 si rb 32:47 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low even-numbered half-word signed integer elements in r a and r b are multiplied. the intermediate product is sign-extended and subtracted from the contents of the 64-bit accumulator, and the result is placed into r d and into the accumulator. note: this is a modulo difference. there is no check for overflow and no saturation is performed. any overflow of the 64-bit difference is not recorded into the spefscr. figure 73. evmhegsmian (even form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110101001 47 48 0313263 intermediate product accumulator r b x ? r d and accumulator r a ssss_ssss_ssss_ssss...ssss instruction set RM0004 543/1176 evmhegumiaa evmhegumiaa vector multiply half words, even, guarded, unsigned, modulo, integer and accumulate evmhegumiaa r d ,r a ,r b temp 0:31 ra 32:47 ui rb 32:47 temp 0:63 extz(temp 0:31 ) rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low even-numbered half-word unsigned integer elements in r a and r b are multiplied. the intermediate product is zero-extended and added to the contents of the 64-bit accumulator. the resu lting sum is placed into r d and into the accumulator. note: this is a modulo sum. there is no overflow check and no saturation is performed. any overflow of the 64-bit sum is not recorded in to the spefscr. figure 74. evmhegumiaa (even form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100101000 47 48 0313263 intermediate product accumulator r b x + r d and accumulator r a 0000_0000_0000_0000...000 RM0004 instruction set 544/1176 evmhegumian evmhegumian vector multiply half words, even, guarded, unsigned, modulo, integer and accumulate negative evmhegumian r d ,r a ,r b temp 0:31 ra 32:47 ui rb 32:47 temp 0:63 extz(temp 0:31 ) rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low even-numbered unsigned integer elements in r a and r b are multiplied. the intermediate product is zero-extended and subtracted from the contents of the 64-bit accumulator. th e result is placed into r d and into the accumulator. note: this is a modulo difference. there is no check for overflow and no saturation is performed. any overflow of the 64-bit difference is not recorded into the spefscr. figure 75. evmhegumian (even form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110101000 47 48 0313263 intermediate product accumulator r b x ? r d and accumulator r a 0000_0000_0000_0000...000 instruction set RM0004 545/1176 evmhesmf evmhesmf vector multiply half words, even, si gned, modulo, fractional (to accumulator) evmhesmf r d ,r a ,r b (a = 0) evmhesmfa r d ,r a ,r b (a = 1) // high rd 0:31 ( ra 0:15 sf rb 0:15 ) // low rd 32:63 ( ra 32:47 sf rb 32:47 ) // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding even-numbered half-word signed fractional elements in r a and r b are multiplied then placed into the corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 76. even multiply of two signed modulo fractional elements (to accumulator) (evmhesmf) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a01011 15 16 47 48 0313263 r a r b r d x x ( and accumulator if evmhesmfa ) RM0004 instruction set 546/1176 evmhesmfaaw evmhesmfaaw vector multiply half words, even, signe d, modulo, fractional and accumulate into words evmhesmfaaw r d ,r a ,r b // high temp 0:31 (ra 0:15 sf rb 0:15 ) rd 0:31 acc 0:31 + temp 0:31 // low temp 0:31 (ra 32:47 sf rb 32:47 ) rd 32:63 acc 32:63 + temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding even-numbered half-word signed fractional elements in r a and r b are multiplied. the 32 bits of each intermediate product are added to the contents of the accumulator words to form intermediate sums, which are placed into the corresponding r d words and into the accumulator. other registers altered: acc figure 77. even form of vector half-word multiply (evmhesmfaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100001011 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a instruction set RM0004 547/1176 evmhesmfanw evmhesmfanw vector multiply half words, even, signed, modulo, fractional and accumulate negative into words evmhesmfanw r d ,r a ,r b // high temp 0:31 ra 0:15 sf rb 0:15 rd 0:31 acc 0:31 - temp 0:31 // low temp 0:31 ra 32:47 sf rb 32:47 rd 32:63 acc 32:63 - temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding even-numbered half-word signed fractional elements in r a and r b are multiplied. the 32-bit intermediate products are subtracted from the contents of the accumulator words to form intermediate differences, which are placed into the corresponding r d words and into the accumulator. other registers altered: acc figure 78. even form of vector half-word multiply (evmhesmfanw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110001011 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a RM0004 instruction set 548/1176 evmhesmi evmhesmi vector multiply half words, even, signed, modulo, integer (to accumulator) evmhesmi r d ,r a ,r b (a = 0) evmhesmia r d ,r a ,r b (a = 1) // high rd 0:31 ra 0:15 si rb 0:15 // low rd 32:63 ra 32:47 si rb 32:47 // update accumulator if a = 1, then acc 0:63 rd 0:63 the corresponding even-numbered half-word signed integer elements in r a and r b are multiplied. the two 32-bit products are placed into the corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 79. even form for vector multiply (to accumulator) (evmhesmi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a01001 15 16 47 48 0313263 r a r b r d (and accumulator x x for evmhesmia ) instruction set RM0004 549/1176 evmhesmiaaw evmhesmiaaw vector multiply half words, even, signed, modulo, integer and accumulate into words evmhesmiaaw r d ,r a ,r b // high temp 0:31 ra 0:15 si rb 0:15 rd 0:31 acc 0:31 + temp 0:31 // low temp 0:31 ra 32:47 si rb 32:47 rd 32:63 acc 32:63 + temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding even-numbered half-word signed integer elements in r a and r b are multiplied. each intermediate 32-bit product is added to the contents of the accumulator words to form intermediate sums, which are placed into the corresponding r d words and into the accumulator. other registers altered: acc figure 80. even form of vector half-word multiply (evmhesmiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100001001 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a RM0004 instruction set 550/1176 evmhesmianw evmhesmianw vector multiply half words, even, signed, modulo, integer and accumulate negative into words evmhesmianw r d ,r a ,r b // high temp0 0:31 ra 0:15 si rb 0:15 rd 0:31 acc 0:31 - temp0 0:31 // low temp1 0:31 ra 32:47 si rb 32:47 rd 32:63 acc 32:63 - temp1 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding even-numbered half-word signed integer elements in r a and r b are multiplied. each intermediate 32-bit product is subtracted from the contents of the accumulator words to form intermediate differences, which are placed into the corresponding r d words and into the accumulator. other registers altered: acc figure 81. even form of vector half-word multiply (evmhesmianw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110001001 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a instruction set RM0004 551/1176 evmhessf evmhessf vector multiply half words, even, signed, saturate, fractional (to accumulator) evmhessf r d ,r a ,r b (a = 0) evmhessfa r d ,r a ,r b (a = 1) // high temp 0:31 ra 0:15 sf rb 0:15 if (ra 0:15 = 0x8000) & (rb 0:15 = 0x8000) then rd 0:31 0x7fff_ffff //saturate movh 1 else rd 0:31 temp 0:31 movh 0 // low temp 0:31 ra 32:47 sf rb 32:47 if (ra 32:47 = 0x8000) & (rb 32:47 = 0x8000) then rd 32:63 0x7fff_ffff //saturate movl 1 else rd 32:63 temp 0:31 movl 0 // update accumulator if a = 1 then acc 0:63 rd 0:63 // update spefscr spefscr ovh movh spefscr ov movl spefscr sovh spefscr sovh | movh spefscr sov spefscr sov | movl the corresponding even-numbered half-word signed fractional elements in r a and r b are multiplied. the 32 bits of each product ar e placed into the corresponding words of r d. if both inputs are ?1.0, the result saturates to the largest positive signed fraction and the overflow and summary overflow bits are recorded in the spefscr. if a = 1, the result in r d is also placed into the accumulator. other registers altered: spefscr acc (if a = 1) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a00011 RM0004 instruction set 552/1176 figure 82. even multiply of two signed saturate fractional elements (to accumulator) (evmhessf) 15 16 47 48 0313263 r a r b r d (and accumulator x x if evmhessa ) instruction set RM0004 553/1176 evmhessfaaw evmhessfaaw vector multiply half words, even, signed, saturate, fractional and accumulate into words evmhessfaaw r d ,r a ,r b // high temp 0:31 ra 0:15 sf rb 0:15 if (ra 0:15 = 0x8000) & (rb 0:15 = 0x8000) then temp 0:31 0x7fff_ffff //saturate movh 1 else movh 0 temp 0:63 exts(acc 0:31 ) + exts(temp 0:31 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:31 ra 32:47 sf rb 32:47 if (ra 32:47 = 0x8000) & (rb 32:47 = 0x8000) then temp 0:31 0x7fff_ffff //saturate movl 1 else movl 0 temp 0:63 exts(acc 32:63 ) + exts(temp 0:31 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh movh spefscr ov movl spefscr sovh spefscr sovh | ovh | movh spefscr sov spefscr sov | ovl| movl the corresponding even-numbered half-word signed fractional elements in r a and r b are multiplied producing a 32-bit product. if both inputs are ?1.0, the result saturates to 0x7fff_ffff. each 32-bit product is then added to the corresponding word in the accumulator, saturating if overflow or underflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from either the multiply or the addition, the overflow and summary overflow bits ar e recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100000011 RM0004 instruction set 554/1176 figure 83. even form of vector half-word multiply (evmhessfaaw) 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a instruction set RM0004 555/1176 evmhessfanw evmhessfanw vector multiply half words, even, signed, saturate, fractional and accumulate negative into words evmhessfanw r d ,r a ,r b ++ the corresponding even-numbered half-word signed fractional elements in r a and r b are multiplied producing a 32-bit product. if both inputs are ?1.0, the result saturates to 0x7fff_ffff. each 32-bit product is then subtracted from the corresponding word in the accumulator, saturating if overflow or underflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from either the multiply or the addition, the overflow and summary overflow bits ar e recorded in the spefscr. other registers altered: spefscr acc figure 84. even form of vector half-word multiply (evmhessfanw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110000011 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a RM0004 instruction set 556/1176 evmhessiaaw evmhessiaaw vector multiply half words, even, signed, saturate, integer and accumulate into words evmhessiaaw r d ,r a ,r b // high temp 0:31 ra 0:15 si rb 0:15 temp 0:63 exts(acc 0:31 ) + exts(temp 0:31 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:31 ra 32:47 si rb 32:47 temp 0:63 exts(acc 32:63 ) + exts(temp 0:31 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the corresponding even-numbered half-word signed integer elements in r a and r b are multiplied producing a 32-bit product. each 32-bit product is then added to the corresponding word in the accumulator, saturating if overflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from either the multiply or the addition, the overflow and summary overflow bits ar e recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100000001 instruction set RM0004 557/1176 figure 85. even form of vector half-word multiply (evmhessiaaw) 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a RM0004 instruction set 558/1176 evmhessianw evmhessianw vector multiply half words, even, signed, saturate, integer and accumulate negative into words evmhessianw r d ,r a ,r b // high temp 0:31 ra 0:15 si rb 0:15 temp 0:63 exts(acc 0:31 ) - exts(temp 0:31 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:31 ra 32:47 si rb 32:47 temp 0:63 exts(acc 32:63 ) - exts(temp 0:31 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the corresponding even-numbered half-word signed integer elements in r a and r b are multiplied producing a 32-bit product. each 32-bit product is then subtracted from the corresponding word in the accumulator, saturating if overflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from either the multiply or the addition, the overflow and summary overflow bits ar e recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110000001 instruction set RM0004 559/1176 figure 86. even form of vector half-word multiply (evmhessianw) 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a RM0004 instruction set 560/1176 evmheumi evmheumi vector multiply half words, even, unsigned, modulo, integer (to accumulator) evmheumi r d ,r a ,r b (a = 0) evmheumia r d ,r a ,r b (a = 1) // high rd 0:31 ra 0:15 ui rb 0:15 // low rd 32:63 ra 32:47 ui rb 32:47 // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding even-numbered half-word unsigned integer elements in r a and r b are multiplied. the two 32-bit products are placed into the corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. figure 87. vector multiply half words, even, unsigned, modulo, integer (to accumulator) (evmheumi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a01000 15 16 47 48 0313263 r a r b r d (and accumulator x x if evmheumia ) instruction set RM0004 561/1176 evmheumiaaw evmheumiaaw vector multiply half words, even, unsigned, modulo, integer and accumulate into words evmheumiaaw r d ,r a ,r b // high temp 0:31 ra 0:15 ui rb 0:15 rd 0:31 acc 0:31 + temp 0:31 // low temp 0:31 ra 32:47 ui rb 32:47 rd 32:63 acc 32:63 + temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding even-numbered half-word unsigned integer elements in r a and r b are multiplied. each intermediate product is added to the contents of the corresponding accumulator words and the sums are placed into the corresponding r d and accumulator words. other registers altered: acc figure 88. even form of vector half-word multiply (evmheumiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100001000 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a RM0004 instruction set 562/1176 evmheumianw evmheumianw vector multiply half words, even, unsigned, modulo, integer and accumulate negative into words evmheumianw r d ,r a ,r b // high temp 0:31 ra 0:15 ui rb 0:15 rd 0:31 acc 0:31 - temp 0:31 // low temp 0:31 ra 32:47 ui rb 32:47 rd 32:63 acc 32:63 - temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding even-numbered half-word unsigned integer elements in r a and r b are multiplied. each in termediate product is subtracted from the contents of the corresponding accumulator words. the differences are placed into the corresponding r d and accumulator words. other registers altered: acc figure 89. even form of vector half-word multiply (evmheumianw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110001000 15 16 47 48 0313263 intermediate product accumulator r b x x - - r d and accumulator r a instruction set RM0004 563/1176 evmheusiaaw evmheusiaaw vector multiply half words, even, unsigned, saturate, integer and accumulate into words evmheusiaaw r d ,r a ,r b // high temp 0:31 ra 0:15 ui rb 0:15 temp 0:63 extz(acc 0:31 ) + extz(temp 0:31 ) ovh temp 31 rd 0:31 saturate(ovh, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) //low temp 0:31 ra 32:47 ui rb 32:47 temp 0:63 extz(acc 32:63 ) + extz(temp 0:31 ) ovl temp 31 rd 32:63 saturate(ovl, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl for each word element in the accumulator, corresponding even-numbered half-word unsigned integer elements in r a and r b are multiplied producing a 32-bit product. each 32- bit product is then added to the corresponding word in the accumulator, saturating if overflow occurs, and the result is placed in r d and the accumulator. if the addition causes overflow, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100000000 RM0004 instruction set 564/1176 figure 90. even form of vector half-word multiply (evmheusiaaw) 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a instruction set RM0004 565/1176 evmheusianw evmheusianw vector multiply half words, even, unsigned, saturate, integer and accumulate negative into words evmheusianw r d ,r a ,r b // high temp 0:31 ra 0:15 ui rb 0:15 temp 0:63 extz(acc 0:31 ) - extz(temp 0:31 ) ovh temp 31 rd 0:31 saturate(ovh, 0, 0x0000_0000, 0x0000_0000, temp 32:63 ) //low temp 0:31 ra 32:47 ui rb 32:47 temp 0:63 extz(acc 32:63 ) - extz(temp 0:31 ) ovl temp 31 rd 32:63 saturate(ovl, 0, 0x0000_0000, 0x0000_0000, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl for each word element in the accumulator, corresponding even-numbered half-word unsigned integer elements in r a and r b are multiplied producing a 32-bit product. each 32- bit product is then subtracted from the corresponding word in the accumulator, saturating if underflow occurs, and the result is placed in r d and the accumulator. if there is an underflow from the subtraction, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 rd ra rb 10110000000 RM0004 instruction set 566/1176 figure 91. even form of vector half-word multiply (evmheusianw) 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a instruction set RM0004 567/1176 evmhogsmfaa evmhogsmfaa vector multiply half words, odd, guarde d, signed, modulo, fr actional and accumulate evmhogsmfaa r d ,r a ,r b temp 0:31 ra 48:63 sf rb 48:63 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low odd-numbered half-word signed fractional elements in r a and r b are multiplied. the intermediate product is sign-extended to 64 bits then added to the contents of the 64-bit accumulator, and the result is placed into r d and into the accumulator. note: this is a modulo sum. there is no check for overflow and no saturation is performed. an overflow from the 64-bit sum, if one occurs, is not recorded into the spefscr. figure 92. evmhogsmfaa (odd form) spe apu user 0 5 6 1011 1516 2021 31 000100 rd ra rb 10100101111 47 48 0313263 intermediate product accumulator r b x + r d and accumulator r a ssss_ssss_ssss_ssss...ssss RM0004 instruction set 568/1176 evmhogsmfan evmhogsmfan vector multiply half words, odd, guarde d, signed, modulo, fr actional and accumulate negative evmhogsmfan r d ,r a ,r b temp 0:31 ra 48:63 sf rb 48:63 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low odd-numbered half-word signed fractional elements in r a and r b are multiplied. the intermediate product is sign-extended to 64 bits then subtracted from the contents of the 64-bit accumulator, and the result is placed into r d and into the accumulator. note: this is a modulo difference. there is no check for overflow and no saturation is performed. any overflow of the 64-bit differenc e is not recorded into the spefscr. figure 93. evmhogsmfan (odd form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 1 0110101111 47 48 0313263 intermediate product accumulator r b x ? r d and accumulator r a ssss_ssss_ssss_ssss...ssss instruction set RM0004 569/1176 evmhogsmiaa evmhogsmiaa vector multiply half words, odd, guarded, signed, modulo, integer, and accumulate evmhogsmiaa r d ,r a ,r b temp 0:31 ra 48:63 si rb 48:63 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low odd-numbered half-word signed integer elements in r a and r b are multiplied. the intermediate product is sign-extended to 64 bits then added to the contents of the 64-bit accumulator, and the result is placed into r d and into the accumulator. note: this is a modulo sum. there is no check for overflow and no saturation is performed. an overflow from the 64-bit su m, if one occurs, is not recorded into the spefscr. figure 94. evmhogsmiaa (odd form) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100101101 47 48 0313263 intermediate product accumulator r b x + r d and accumulator r a ssss_ssss_ssss_ssss...ssss RM0004 instruction set 570/1176 evmhogsmian evmhogsmian vector multiply half words, odd, guarded, signed, modulo, integer and accumulate negative evmhogsmian r d ,r a ,r b temp 0:31 ra 48:63 si rb 48:63 temp 0:63 exts(temp 0:31 ) rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low odd-numbered half-word signed integer elements in r a and r b are multiplied. the intermediate product is sign-extended to 64 bits then subtracted from the contents of the 64-bit accumulator, and the result is placed into r d and into the accumulator. note: this is a modulo difference. there is no check for overflow and no saturation is performed. any overflow of the 64-bit difference is not recorded into the spefscr. figure 95. evmhogsmian (odd form) spe apu user 0 5 6 1011 1516 2021 31 000100 rd ra rb 10110101101 47 48 0313263 intermediate product accumulator r b x ? r d and accumulator r a ssss_ssss_ssss_ssss...ssss instruction set RM0004 571/1176 evmhogumiaa evmhogumiaa vector multiply half words, odd, guarded, unsigned, modulo, integer and accumulate evmhogumiaa r d ,r a ,r b temp 0:31 ra 48:63 ui rb 48:63 temp 0:63 extz(temp 0:31 ) rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low odd-numbered half-word unsigned integer elements in r a and r b are multiplied. the intermediate product is zero-extended to 64 bits then added to the contents of the 64-bit accumulator, and the result is placed into r d and into the accumulator. note: this is a modulo sum. there is no check for overflow and no saturation is performed. an overflow from the 64-bit sum, if one occurs, is not recorded into the spefscr. figure 96. evmhogumiaa (odd form) spe apu user 0 5 6 1011 1516 2021 31 000100 rd ra rb 10100101100 47 48 0313263 intermediate product accumulator r b x + r d and accumulator r a 0000_0000_0000_0000...000 RM0004 instruction set 572/1176 evmhogumian evmhogumian vector multiply half words, odd, guarded, unsigned, modulo, integer and accumulate negative evmhogumian r d ,r a ,r b temp 0:31 ra 48:63 ui rb 48:63 temp 0:63 extz(temp 0:31 ) rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low odd-numbered half-word unsigned integer elements in r a and r b are multiplied. the intermediate product is zero-extended to 64 bits then subtracted from the contents of the 64-bit accumulator, and the result is placed into r d and into the accumulator. note: this is a modulo difference. there is no check for overflow and no saturation is performed. any overflow of the 64-bit difference is not recorded into the spefscr. figure 97. evmhogumian (odd form) spe apu user 0 5 6 1011 1516 2021 31 000100 rd ra rb 10110101100 47 48 0313263 intermediate product accumulator r b x ? r d and accumulator r a 0000_0000_0000_0000...000 instruction set RM0004 573/1176 evmhosmf evmhosmf vector multiply half words, odd, signed, modulo, fractional (to accumulator) evmhosmf r d ,r a ,r b (a = 0) evmhosmfa r d ,r a ,r b (a = 1) // high rd 0:31 ( ra 16:31 sf rb 16:31 ) // low rd 32:63 ( ra 48:63 sf rb 48:63 ) // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding odd-numbered, half-w ord signed fractional elements in r a and r b are multiplied. each product is placed into the corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 98. vector multiply half words, odd, signed, modulo, fractional (to accumulator) (evmhosmf) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a01111 15 16 47 48 0313263 r a r b r d (and accumulator x x if evmhosmf ) RM0004 instruction set 574/1176 evmhosmfaaw evmhosmfaaw ve ctor multiply half words, odd, signed, modulo, fractional and accumulate into words evmhosmfaaw r d ,r a ,r b // high temp 0:31 ra 16:31 sf rb 16:31 rd 0:31 acc 0:31 + temp 0:31 // low temp 0:31 ra 48:63 sf rb 48:63 rd 32:63 acc 32:63 + temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding odd-numbered half-word signed fractional elements in r a and r b are multiplied. the 32 bits of each intermediate product is added to the contents of the corresponding accumulator word and the results are placed into the corresponding r d words and into the accumulator other registers altered: acc figure 99. odd form of vector half-word multiply (evmhosmfaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100001111 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a instruction set RM0004 575/1176 evmhosmfanw evmhosmfanw vector multiply half words, odd, signed, modulo, fractional and accumulate negative into words evmhosmfanw r d ,r a ,r b // high temp 0:31 ra 16:31 sf rb 16:31 rd 0:31 acc 0:31 - temp 0:31 // low temp 0:31 ra 48:63 sf rb 48:63 rd 32:63 acc 32:63 - temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding odd-numbered half-word signed fractional elements in r a and r b are multiplied. the 32 bits of each intermediate product is subtracted from the contents of the corresponding accumulator word and the results are placed into the corresponding r d words and into the accumulator. other registers altered: acc figure 100. odd form of vector half-word multiply (evmhosmfanw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110001111 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a RM0004 instruction set 576/1176 evmhosmi evmhosmi vector multiply half words, odd, signed, modulo, integer (to accumulator) evmhosmi r d ,r a ,r b (a = 0) evmhosmia r d ,r a ,r b (a = 1) // high rd 0:31 ra 16:31 si rb 16:31 // low rd 32:63 ra 48:63 si rb 48:63 // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding odd-numbered half-word signed integer elements in r a and r b are multiplied. the two 32-bit products are placed into the corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 101. vector multiply half words, odd, signed, modulo, integer (to accumulator) (evmhosmi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a01101 15 16 47 48 0313263 r a r b r d (and accumulator x x if evmhosmia ) instruction set RM0004 577/1176 evmhosmiaaw evmhosmiaaw vector multiply half words, odd, signed, modulo, integer and accumulate into words evmhosmiaaw r d ,r a ,r b // high temp 0:31 ra 16:31 si rb 16:31 rd 0:31 acc 0:31 + temp 0:31 // low temp 0:31 ra 48:63 si rb 48:63 rd 32:63 acc 32:63 + temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding odd-numbered half-word signed integer elements in r a and r b are multiplied. each intermediate 32-bit product is added to the contents of the corresponding accumulator word and the results are placed into the corresponding r d words and into the accumulator. other registers altered: acc figure 102. odd form of vector half-word multiply (evmhosmiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100001101 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a RM0004 instruction set 578/1176 evmhosmianw evmhosmianw vector multiply half words, odd, signed, modulo, integer and accumulate negative into words evmhosmianw r d ,r a ,r b // high temp 0:31 ra 16:31 si rb 16:31 rd 0:31 acc 0:31 - temp 0:31 // low temp 0:31 ra 48:63 si rb 48:63 rd 32:63 acc 32:63 - temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding odd-numbered half-word signed integer elements in r a and r b are multiplied. each intermediate 32-bit product is subtracted from the contents of the corresponding accumulator word and the results are placed into the corresponding r d words and into the accumulator. other registers altered: acc figure 103. odd form of vector half-word multiply (evmhosmianw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110001101 15 16 47 48 0313263 intermediate product accumulator r b x x - - r d and accumulator r a instruction set RM0004 579/1176 evmhossf evmhossf vector multiply half words, odd, signed, saturate, fractional (to accumulator) evmhossf r d ,r a ,r b (a = 0) evmhossfa r d ,r a ,r b (a = 1) // high temp 0:31 ra 16:31 sf rb 16:31 if (ra 16:31 = 0x8000) & (rb 16:31 = 0x8000) then rd 0:31 0x7fff_ffff //saturate movh 1 else rd 0:31 temp 0:31 movh 0 // low temp 0:31 ra 48:63 sf rb 48:63 if (ra 48:63 = 0x8000) & (rb 48:63 = 0x8000) then rd 32:63 0x7fff_ffff //saturate movl 1 else rd 32:63 temp 0:31 movl 0 // update accumulator if a = 1 then acc 0:63 rd 0:63 // update spefscr spefscr ovh movh spefscr ov movl spefscr sovh spefscr sovh | movh spefscr sov spefscr sov | movl the corresponding odd-numbered half-word signed fractional elements in r a and r b are multiplied. the 32 bits of each product ar e placed into the corresponding words of r d. if both inputs are ?1.0, the result saturates to the largest positive signed fraction and the overflow and summary overflow bits are recorded in the spefscr. if a = 1, the result in r d is also placed into the accumulator. other registers altered: spefscr acc (if a = 1) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a00111 RM0004 instruction set 580/1176 figure 104. vector multiply half words, odd, signed, saturate, fractional (to accumulator) (evmhossf) 15 16 47 48 0313263 r a r b r d (and accumulator x x if evmhossfa) instruction set RM0004 581/1176 evmhossfaaw evmhossfaaw vector multiply half words, odd, signed, saturate, fractional and accumulate into words evmhossfaaw r d ,r a ,r b // high temp 0:31 ra 16:31 sf rb 16:31 if (ra 16:31 = 0x8000) & (rb 16:31 = 0x8000) then temp 0:31 0x7fff_ffff //saturate movh 1 else movh 0 temp 0:63 exts(acc 0:31 ) + exts(temp 0:31 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:31 ra 48:63 sf rb 48:63 if (ra 48:63 = 0x8000) & (rb 48:63 = 0x8000) then temp 0:31 0x7fff_ffff //saturate movl 1 else movl 0 temp 0:63 exts(acc 32:63 ) + exts(temp 0:31 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh movh spefscr ov movl spefscr sovh spefscr sovh | ovh | movh spefscr sov spefscr sov | ovl| movl the corresponding odd-numbered half-word signed fractional elements in r a and r b are multiplied producing a 32-bit product. if both inputs are ?1.0, the result saturates to 0x7fff_ffff. each 32-bit product is then added to the corresponding word in the accumulator, saturating if overflow or underflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from either the multiply or the addition, the overflow and summary overflow bits ar e recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100000111 RM0004 instruction set 582/1176 figure 105. odd form of vector half-word multiply (evmhossfaaw) 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a instruction set RM0004 583/1176 evmhossfanw evmhossfanw vector multiply half words, odd, signed, saturate, fractional and accumulate negative into words evmhossfanw r d ,r a ,r b // high temp 0:31 ra 16:31 sf rb 16:31 if (ra 16:31 = 0x8000) & (rb 16:31 = 0x8000) then temp 0:31 0x7fff_ffff //saturate movh 1 else movh 0 temp 0:63 exts(acc 0:31 ) - exts(temp 0:31 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:31 ra 48:63 sf rb 48:63 if (ra 48:63 = 0x8000) & (rb 48:63 = 0x8000) then temp 0:31 0x7fff_ffff //saturate movl 1 else movl 0 temp 0:63 exts(acc 32:63 ) - exts(temp 0:31 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh movh spefscr ov movl spefscr sovh spefscr sovh | ovh | movh spefscr sov spefscr sov | ovl| movl the corresponding odd-numbered half-word signed fractional elements in r a and r b are multiplied producing a 32-bit product. if both inputs are ?1.0, the result saturates to 0x7fff_ffff. each 32-bit product is then subtracted from the corresponding word in the accumulator, saturating if overflow or underflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from either the multiply or the subtraction, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110000111 RM0004 instruction set 584/1176 figure 106. odd form of vector half-word multiply (evmhossfanw) 15 16 47 48 0313263 intermediate product accumulator r b x x ? -- r d and accumulator r a instruction set RM0004 585/1176 evmhossiaaw evmhossiaaw vector multiply half words, odd, signed, saturate, integer and accumulate into words evmhossiaaw r d ,r a ,r b // high temp 0:31 ra 16:31 si rb 16:31 temp 0:63 exts(acc 0:31 ) + exts(temp 0:31 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:31 ra 48:63 si rb 48:63 temp 0:63 exts(acc 32:63 ) + exts(temp 0:31 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the corresponding odd-numbered half-word signed integer elements in r a and r b are multiplied producing a 32-bit product. each 32-bit product is then added to the corresponding word in the accumulator, saturating if overflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from the addition, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100000101 RM0004 instruction set 586/1176 figure 107. odd form of vector half-word multiply (evmhossiaaw) 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a instruction set RM0004 587/1176 evmhossianw evmhossianw vector multiply half words, odd, signed, saturate, integer and accumulate negative into words evmhossianw r d ,r a ,r b // high temp 0:31 ra 16:31 si rb 16:31 temp 0:63 exts(acc 0:31 ) - exts(temp 0:31 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:31 ra 48:63 si rb 48:63 temp 0:63 exts(acc 32:63 ) - exts(temp 0:31 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the corresponding odd-numbered half-word signed integer elements in r a and r b are multiplied producing a 32-bit product. each 32-bit product is then subtracted from the corresponding word in the accumulator, saturating if overflow occurs, and the result is placed in r d and the accumulator. if there is an overflow or underflow from the subtraction, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110000101 RM0004 instruction set 588/1176 figure 108. odd form of vector half-word multiply (evmhossianw) 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a instruction set RM0004 589/1176 evmhoumi evmhoumi vector multiply half words, odd, unsigned, modulo, integer (to accumulator) evmhoumi r d ,r a ,r b (a = 0) evmhoumia r d ,r a ,r b (a = 1) // high rd 0:31 ra 16:31 ui rb 16:31 // low rd 32:63 ra 48:63 ui rb 48:63 // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding odd-numbered half-word unsigned integer elements in r a and r b are multiplied. the two 32-bit products are placed into the corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 109. vector multiply half words, odd, unsigned, modulo, integer (to accumulator) (evmhoumi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10000a01100 15 16 47 48 0313263 r a r b r d (and accumulator x x if evmhoumia ) RM0004 instruction set 590/1176 evmhoumiaaw evmhoumiaaw vector multiply half words, odd, unsigned, modulo, integer and accumulate into words evmhoumiaaw r d ,r a ,r b // high temp 0:31 ra 16:31 ui rb 16:31 rd 0:31 acc 0:31 + temp 0:31 // low temp 0:31 ra 48:63 ui rb 48:63 rd 32:63 acc 32:63 + temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding odd-numbered half-word unsigned integer elements in r a and r b are multiplied. each intermediate product is added to the contents of the corresponding accumulator word. the sums are placed into the corresponding r d and accumulator words. other registers altered: acc figure 110. odd form of vector half-word multiply (evmhoumiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100001100 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a instruction set RM0004 591/1176 evmhoumianw evmhoumianw vector multiply half words, odd, unsigned, modulo, integer and accumulate negative into words evmhoumianw r d ,r a ,r b // high temp 0:31 ra 0:15 ui rb 0:15 rd 0:31 acc 0:31 - temp 0:31 / / low temp 0:31 ra 32:47 ui rb 32:47 rd 32:63 acc 32:63 - temp 0:31 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding odd-numbered half-word unsigned integer elements in r a and r b are multiplied. each in termediate product is subtracted from the contents of the corresponding accumulator word. the results are placed into the corresponding r d and accumulator words. other registers altered: acc figure 111. odd form of vector half-word multiply (evmhoumianw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110001100 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a RM0004 instruction set 592/1176 evmhousiaaw evmhousiaaw vector multiply half words, odd, unsigned, saturate, integer and accumulate into words evmhousiaaw r d ,r a ,r b // high temp 0:31 ra 16:31 ui rb 16:31 temp 0:63 extz(acc 0:31 ) + extz(temp 0:31 ) ovh temp 31 rd 0:31 saturate(ovh, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) //low temp 0:31 ra 48:63 ui rb 48:63 temp 0:63 extz(acc 32:63 ) + extz(temp 0:31 ) ovl temp 31 rd 32:63 saturate(ovl, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl for each word element in the accumulator, corresponding odd-numbered half-word unsigned integer elements in r a and r b are multiplied producing a 32-bit product. each 32- bit product is then added to the corresponding word in the accumulator, saturating if overflow occurs, and the result is placed in r d and the accumulator. if the addition causes overflow, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10100000100 instruction set RM0004 593/1176 figure 112. odd form of vector half-word multiply (evmhousiaaw) 15 16 47 48 0313263 intermediate product accumulator r b x x + + r d and accumulator r a RM0004 instruction set 594/1176 evmhousianw evmhousianw vector multiply half words, odd, unsigned, saturate, integer and accumulate negative into words evmhousianw r d ,r a ,r b // high temp 0:31 ra 16:31 ui rb 16:31 temp 0:63 extz(acc 0:31 ) - extz(temp 0:31 ) ovh temp 31 rd 0:31 saturate(ovh, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) //low temp 0:31 ra 48:63 ui rb 48:63 temp 0:63 extz(acc 32:63 ) - extz(temp 0:31 ) ovl temp 31 rd 32:63 saturate(ovl, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl for each word element in the accumulator, corresponding odd-numbered half-word unsigned integer elements in r a and r b are multiplied producing a 32-bit product. each 32- bit product is then subtracted from the corresponding word in the accumulator, saturating if overflow occurs, and the result is placed in r d and the accumulator. if subtraction causes overflow, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10110000100 instruction set RM0004 595/1176 figure 113. odd form of vector half-word multiply (evmhousianw) 15 16 47 48 0313263 intermediate product accumulator r b x x ? ? r d and accumulator r a RM0004 instruction set 596/1176 evmra evmra initialize accumulator evmra r d ,r a acc 0:63 ra 0:63 rd 0:63 ra 0:63 the contents of r a are written into the accumulator and copied into r d. this is the method for initializing the accumulator. other registers altered: acc figure 114. initialize accumulator (evmra) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011000100 0313263 r a r d and accumulator instruction set RM0004 597/1176 evmwhsmf evmwhsmf vector multiply word high signed, modulo, fractional (to accumulator) evmwhsmf r d ,r a ,r b (a = 0) evmwhsmfa r d ,r a ,r b (a = 1) // high temp 0:63 ra 0:31 sf rb 0:31 rd 0:31 temp 0:31 // low temp 0:63 ra 32:63 sf rb 32:63 rd 32:63 temp 0:31 // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding word signed fractional elements in r a and r b are multiplied and bits 0? 31 of the two products are placed into the two corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a =1) figure 115. vector multiply word high signed, modulo, fractional (to accumulator) (evmwhsmf) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a01111 0313263 intermediate product r b x r d (and accumulator r a x if evmshdmfa ) RM0004 instruction set 598/1176 evmwhsmi evmwhsmi vector multiply word high signed, modulo, integer (to accumulator) evmwhsmi r d ,r a ,r b (a = 0) evmwhsmia r d ,r a ,r b (a = 1) // high temp 0:63 ra 0:31 si rb 0:31 rd 0:31 temp 0:31 // low temp 0:63 ra 32:63 si rb 32:63 rd 32:63 temp 0:31 // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding word signed integer elements in r a and r b are multiplied. bits 0?31 of the two 64-bit products are placed into the two corresponding words of r d. if a = 1,the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 116. vector multiply word high signed, modulo, integer (to accumulator) (evmwhsm) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a01101 0313263 intermediate r b x r d r a x if evmwhsmia ) product r (and accumulator instruction set RM0004 599/1176 evmwhssf evmwhssf vector multiply word high signed, saturate, fractional (to accumulator) evmwhssf r d ,r a ,r b (a = 0) evmwhssfa r d ,r a ,r b (a = 1) // high temp 0:63 ra 0:31 sf rb 0:31 if (ra 0:31 = 0x8000_0000) & ( rb 0:31 = 0x8000_0000) then rd 0:31 0x7fff_ffff //saturate movh 1 else rd 0:31 temp 0:31 movh 0 // low temp 0:63 ra 32:63 sf rb 32:63 if (ra 32:63 = 0x8000_0000) & (rb 32:63 = 0x8000_0000) then rd 32:63 0x7fff_ffff //saturate movl 1 else rd 32:63 temp 0:31 movl 0 // update accumulator if a = 1 then acc 0:63 rd 0:63 // update spefscr spefscr ovh movh spefscr ov movl spefscr sovh spefscr sovh | movh spefscr sov spefscr sov | movl the corresponding word signed fractional elements in r a and r b are multiplied. bits 0?31 of each product are placed into the corresponding words of r d. if both inputs are ?1.0, the result saturates to the largest positive signed fraction and the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc (if a = 1) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a00111 RM0004 instruction set 600/1176 figure 117. vector multiply word high signed, saturate, fractional (to accumulator) (evmwhssf) 0313263 intermediate product r b x r d (and accumulator r a x if evmwhssfa ) instruction set RM0004 601/1176 evmwhumi evmwhumi vector multiply word high unsigned, modulo, integer (to accumulator) evmwhumi r d ,r a ,r b (a = 0) evmwhumia r d ,r a ,r b (a = 1) // high temp 0:63 ra 0:31 ui rb 0:31 rd 0:31 temp 0:31 // low temp 0:63 ra 32:63 ui rb 32:63 rd 32:63 temp 0:31 // update accumulator if a = 1, acc 0:63 rd 0:63 the corresponding word unsigned integer elements in r a and r b are multiplied. bits 0?31 of the two products are placed into the two corresponding words of r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 118. vector multiply word high unsigned, modulo, integer (to accumulator) (evmwhumi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a01100 0313263 intermediate product r b x r d (and accumulator r a x if evmwhumia ) RM0004 instruction set 602/1176 evmwlsmiaaw evmwlsmiaaw vector multiply word low signed, modulo, integer and accumulate in words evmwlsmiaaw r d ,r a ,r b // high temp 0:63 ra 0:31 si rb 0:31 rd 0:31 acc 0:31 + temp 32:63 // low temp 0:63 ra 32:63 si rb 32:63 rd 32:63 acc 32:63 + temp 32:63 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding word signed integer elements in r a and r b are multiplied. the least significant 32 bits of each intermediate product is added to the contents of the corresponding accumulator words, and the result is placed into r d and the accumulator. other registers altered: acc figure 119. vector multiply word low signed, modulo, integer & accumulate in words (evmwlsmiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101001001 0313263 intermediate product r b x accumulator r a x + + r d and accumulator instruction set RM0004 603/1176 evmwlsmianw evmwlsmianw vector multiply word low signed, modulo, integer and accumulate negative in words evmwlsmianw r d ,r a ,r b // high temp 0:63 ra 0:31 si rb 0:31 rd 0:31 acc 0:31 - temp 32:63 // low temp 0:63 ra 32:63 si rb 32:63 rd 32:63 acc 32:63 - temp 32:63 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding word elements in r a and r b are multiplied. the least significant 32 bits of each intermediate product is subtracted from the contents of the corresponding accumulator words and the result is placed in r d and the accumulator. other registers altered: acc figure 120. vector multiply word low signed, modulo, integer and accumulate negative in words (evmwlsmianw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10111001001 0313263 intermediate product r b x accumulator r a x - - r d and accumulator RM0004 instruction set 604/1176 evmwlssiaaw evmwlssiaaw vector multiply word low signed, saturate, integer and accumulate in words evmwlssiaaw r d ,r a ,r b // high temp 0:63 ra 0:31 si rb 0:31 temp 0:63 exts(acc 0:31 ) + exts(temp 32:63 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:63 ra 32:63 si rb 32:63 temp 0:63 exts(acc 32:63 ) + exts(temp 32:63 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the corresponding word signed integer elements in r a and r b are multiplied producing a 64- bit product. the 32 lsbs of each product is added to the corresponding word in the acc, saturating if overflow or underflow occurs; the result is placed in r d and the accumulator. if there is overflow or underflow from the addition, overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101000001 instruction set RM0004 605/1176 figure 121. vector multiply word low signed, saturate, integer & accumulate in words (evmwlssiaaw) 0313263 intermediate product r b x accumulator r a x + + r d and accumulator RM0004 instruction set 606/1176 evmwlssianw evmwlssianw vector multiply word low signed, saturate, integer and accumulate negative in words evmwlssianw r d ,r a ,r b // high temp 0:63 ra 0:31 si rb 0:31 temp 0:63 exts(acc 0:31 ) - exts(temp 32:63 ) ovh (temp 31 temp 32 ) rd 0:31 saturate(ovh, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // low temp 0:63 ra 32:63 si rb 32:63 temp 0:63 exts(acc 32:63 ) - exts(temp 32:63 ) ovl (temp 31 temp 32 ) rd 32:63 saturate(ovl, temp 31, 0x8000_0000, 0x7fff_ffff, temp32:63) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl the corresponding word signed integer elements in r a and r b are multiplied producing a 64- bit product. the 32 lsbs of each product are subtracted from the corresponding acc word, saturating if overflow or underflow occurs, and the result is placed in r d and the acc. if addition causes overflow or underflow, ov erflow and summary overflow spefscr bits are recorded. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10111000001 instruction set RM0004 607/1176 figure 122. vector multiply word low signed, saturate, integer & accumulate negative in words (evmwlssianw) 0313263 intermediate product r b x accumulator r a x _ _ r d and accumulator RM0004 instruction set 608/1176 evmwlumi evmwlumi vector multiply word low unsigned, modulo, integer evmwlumi r d ,r a ,r b(a = 0) evmwlumia r d ,r a ,r b(a = 1) // high temp 0:63 ra 0:31 ui rb 0:31 rd 0:31 temp 32:63 // low temp 0:63 ra 32:63 ui rb 32:63 rd 32:63 temp 32:63 // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding word unsigned integer elements in r a and r b are multiplied. the least significant 32 bits of each product are placed into the two corresponding words of r d. note: the least significant 32 bits of the product are independent of whether the word elements in r a and r b are treated as signed or unsigned 32-bit integers. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) note that evmwlumi and evmwlumia can be used for signed or unsigned integers. figure 123. vector multiply word low unsigned, modulo, integer (evmwlumi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a01000 0313263 intermediate product r b x r d (and accumulator r a x if evmwlumia ) instruction set RM0004 609/1176 evmwlumiaaw evmwlumiaaw vector multiply word low unsigned, modulo, integer and accumulate in words evmwlumiaaw r d ,r a ,r b // high temp 0:63 ra 0:31 ui rb 0:31 rd 0:31 acc 0:31 + temp 32:63 // low temp 0:63 ra 32:63 ui rb 32:63 rd 32:63 acc 32:63 + temp 32:63 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding word unsigned integer elements in r a and r b are multiplied. the least significant 32 bits of each product are added to the contents of the corresponding accumulator word and the result is placed into r d and the accumulator. other registers altered: acc figure 124. vector multiply word low unsigned, modulo, integer & accumulate in words (evmwlumiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101001000 0313263 intermediate product r b x accumulator r a x + + r d and accumulator RM0004 instruction set 610/1176 evmwlumianw evmwlumianw vector multiply word low unsigned, modulo, integer and accumulate negative in words evmwlumianw r d ,r a ,r b // high temp 0:63 ra 0:31 ui rb 0:31 rd 0:31 acc 0:31 - temp 32:63 // low temp 0:63 ra 32:63 ui rb 32:63 rd 32:63 acc 32:63 - temp 32:63 // update accumulator acc 0:63 rd 0:63 for each word element in the accumulator, the corresponding word unsigned integer elements in r a and r b are multiplied. the least significant 32 bits of each product are subtracted from the contents of the corresponding accumulator word and the result is placed into r d and the accumulator. other registers altered: acc figure 125. vector multiply word low unsigned, modulo, integer & accumulate negative in words (evmwlumianw) spe apu user 056101115162021 31 000100 r d r a r b 10111001000 0313263 intermediate product r b x accumulator r a x _ _ r d and accumulator instruction set RM0004 611/1176 evmwlusiaaw evmwlusiaaw vector multiply word low unsigned, saturate, integer and accumulate in words evmwlusiaaw r d ,r a ,r b // high temp 0:63 ra 0:31 ui rb 0:31 temp 0:63 extz(acc 0:31 ) + extz(temp 32:63 ) ovh temp 31 rd 0:31 saturate(ovh, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) //low temp 0:63 ra 32:63 ui rb 32:63 temp 0:63 extz(acc 32:63 ) + extz(temp 32:63 ) ovl temp 31 rd 32:63 saturate(ovl, 0, 0xffff_ffff, 0xffff_ffff, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl for each word element in the acc, corresponding word unsigned integer elements in r a and r b are multiplied, producing a 64-bit product. the 32 lsbs of each product are added to the corresponding acc word, saturating if overflow occurs; the result is placed in r d and the acc. if the addition causes overflow, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101000000 RM0004 instruction set 612/1176 figure 126. vector multiply word low unsigned, saturate, integer & accumulate in words (evmwlusiaaw) 0313263 intermediate r b x accumulator r a x + + r d and accumulator product instruction set RM0004 613/1176 evmwlusianw evmwlusianw vector multiply word low unsigned, saturate, integer and accumulate negative in words evmwlusianw r d ,r a ,r b // high temp 0:63 ra 0:31 ui rb 0:31 temp 0:63 extz(acc 0:31 ) - extz(temp 32:63 ) ovh temp 31 rd 0:31 saturate(ovh, 0, 0x0000_0000, 0x0000_0000, temp 32:63 ) //low temp 0:63 ra 32:63 ui rb 32:63 temp 0:63 extz(acc 32:63 ) - extz(temp 32:63 ) ovl temp 31 rd 32:63 saturate(ovl, 0, 0x0000_0000, 0x0000_0000, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl for each acc word element, corresponding word elements in r a and r b are multiplied producing a 64-bit product. the 32 lsbs of each product are subtracted from corresponding acc words, saturating if underflow occurs; the result is placed in r d and the acc. if there is an underflow from the subtraction, the overflow and summary overflow bits are recorded in the spefscr. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10111000000 RM0004 instruction set 614/1176 figure 127. vector multiply word low unsigned, saturate, integer & accumulate negative in words (evmwlusianw) 0313263 intermediate product r b x accumulator r a x _ _ r d and accumulator instruction set RM0004 615/1176 evmwsmf evmwsmf vector multiply word signed, modulo, fractional (to accumulator) evmwsmf r d ,r a ,r b (a = 0) evmwsmfa r d ,r a ,r b (a = 1) rd 0:63 ra 32:63 sf rb 32:63 // update accumulator if a = 1 then acc 0:63 rd 0:63 the corresponding low word signed fractional elements in r a and r b are multiplied. the product is placed into r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 128. vector multiply word signed, modulo, fractional (to accumulator) (evmwsmf) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a11011 0313263 r d (and accumulator if r b x r a evmwsmfa ) RM0004 instruction set 616/1176 evmwsmfaa evmwsmfaa vector multiply word signed, modulo, fractional and accumulate evmwsmfaa r d ,r a ,r b temp 0:63 ra 32:63 sf rb 32:63 rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low word signed fractional elements in r a and r b are multiplied. the intermediate product is added to the contents of the 64-bit accumulator and the result is placed in r d and the accumulator. other registers altered: acc figure 129. vector multiply word signed, modulo, fractional & accumulate (evmwsmfaa) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101011011 0313263 intermediate product accumulator r b x + r d and accumulator r a instruction set RM0004 617/1176 evmwsmfan evmwsmfan vector multiply word signed, modulo, fractional and accumulate negative evmwsmfan r d ,r a ,r b temp 0:63 ra 32:63 sf rb 32:63 rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the corresponding low word signed fractional elements in r a and r b are multiplied. the intermediate product is subtracted from the contents of the accumulator and the result is placed in r d and the accumulator. other registers altered: acc figure 130. vector multiply word signed, modulo, fractional & accumulate negative (evmwsmfan) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10111011011 0313263 intermediate product accumulator r b x ? r d and accumulator r a RM0004 instruction set 618/1176 evmwsmi evmwsmi vector multiply word signed, modulo, integer (to accumulator) evmwsmi r d ,r a ,r b (a = 0) evmwsmia r d ,r a ,r b (a = 1) rd 0:63 ra 32:63 si rb 32:63 // update accumulator if a = 1 then acc 0:63 rd 0:63 the low word signed integer elements in r a and r b are multiplied. the product is placed into r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 131. vector multiply word signed, modulo, integer (to accumulator) (evmwsmi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a11001 0313263 r d (and accumulator r b x r a if evmwsmia ) instruction set RM0004 619/1176 evmwsmiaa evmwsmiaa vector multiply word signed, modulo, integer and accumulate evmwsmiaa r d ,r a ,r b temp 0:63 ra 32:63 si rb 32:63 rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the low word signed integer elements in r a and r b are multiplied. the intermediate product is added to the contents of the 64-bit accumulator and the result is placed into r d and the accumulator. other registers altered: acc figure 132. vector multiply word signed, modulo, integer & accumulate (evmwsmiaa) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101011001 0313263 intermediate product accumulator r b x + r d and accumulator r a RM0004 instruction set 620/1176 evmwsmian evmwsmian vector multiply word signed, modulo, integer and accumulate negative evmwsmian r d ,r a ,r b temp 0:63 ra 32:63 si rb 32:63 rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the low word signed integer elements in r a and r b are multiplied. the intermediate product is subtracted from the contents of the 64-bit accumulator and the result is placed into r d and the accumulator. other registers altered: acc figure 133. vector multiply word signed, modulo, integer & accumulate negative (evmwsmian) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10111011001 0313263 intermediate product accumulator r b x ? r d and accumulator r a instruction set RM0004 621/1176 evmwssf evmwssf vector multiply word signed, saturate, fractional (to accumulator) evmwssf r d ,r a ,r b (a = 0) evmwssfa r d ,r a ,r b (a = 1) temp 0:63 ra 32:63 sf rb 32:63 if (ra 32:63 = 0x8000_0000) & (rb 32:63 = 0x8000_0000) then rd 0:63 0x7fff_ffff_ffff_ffff //saturate mov 1 else rd 0:63 temp 0:63 mov 0 // update accumulator if a = 1 then acc 0:63 rd 0:63 // update spefscr spefscr ovh 0 spefscr ov mov spefscr sov spefscr sov | mov the low word signed fractional elements in r a and r b are multiplied. the 64 bit product is placed into r d. if both inputs are ?1.0, the result saturates to the largest positive signed fraction and the overflow and summary ov erflow bits are reco rded in the spefscr. the architecture specifies that if the final result cannot be represented in 64 bits, spefscr[ov] should be set (a long with the sov bit, if it is not already set). if a = 1, the result in r d is also placed into the accumulator. other registers altered: spefscr acc (if a = 1) figure 134. vector multiply word signed, saturate, fractional (to accumulator) (evmwssf) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a10011 0313263 r d (and accumulator r b x r a if evmwssfa ) RM0004 instruction set 622/1176 evmwssfaa evmwssfaa vector multiply word signed, saturate, fractional and accumulate evmwssfaa r d ,r a ,r b temp 0:63 ra 32:63 sf rb 32:63 if (ra 32:63 = 0x8000_0000) & (rb 32:63 = 0x8000_0000) then temp 0:63 0x7fff_ffff_ffff_ffff //saturate mov 1 else mov 0 temp 0:64 exts(acc 0:63 ) + exts(temp 0:63 ) ov (temp 0 temp 1 ) rd 0:63 temp 1:64 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh 0 spefscr ov mov spefscr sov spefscr sov | ov | mov the low word signed fractional elements in r a and r b are multiplied producing a 64-bit product. if both inputs are ?1.0, the product satu rates to the largest positive signed fraction. the 64-bit product is added to the acc and the result is placed in r d and the acc. if there is an overflow from either the mult iply or the addition, the spefscr overflow and summary overflow bits are recorded. note: there is no saturation on the addition with the accumulator. other registers altered: spefscr acc figure 135. vector multiply word signed, saturate, fractional, & accumulate (evmwssfaa) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101010011 0313263 intermediate product accumulator r b x + r d and accumulator r a instruction set RM0004 623/1176 evmwssfan evmwssfan vector multiply word signed, saturate, fractional and accumulate negative evmwssfan r d ,r a ,r b temp 0:63 ra 32:63 sf rb 32:63 if (ra 32:63 = 0x8000_0000) & (rb 32:63 = 0x8000_0000) then temp 0:63 0x7fff_ffff_ffff_ffff //saturate mov 1 else mov 0 temp 0:64 exts(acc 0:63 ) - exts(temp 0:63 ) ov (temp 0 temp 1 ) rd 0:63 temp 1:64 ) // update accumulator acc 0:63 rd 0:63 // update spefscr spefscr ovh 0 spefscr ov mov spefscr sov spefscr sov | ov | mov the low word signed fractional elements in r a and r b are multiplied producing a 64-bit product. if both inputs are ?1.0, the product satu rates to the largest positive signed fraction. the 64-bit product is subtracted from the acc and the result is placed in r d and the acc. if there is an overflow from either the mult iply or the addition, the spefscr overflow and summary overflow bits are recorded. note: there is no saturation on the subtraction with the accumulator. other registers altered: spefscr acc spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10111010011 RM0004 instruction set 624/1176 figure 136. vector multiply word signed, saturate, fractional & accumulate negative (evmwssfan) 0313263 intermediate product accumulator r b x ? r d and accumulator r a instruction set RM0004 625/1176 evmwumi evmwumi vector multiply word unsigned, modulo, integer (to accumulator) evmwumi r d ,r a ,r b (a = 0) evmwumia r d ,r a ,r b (a = 1) rd 0:63 ra 32:63 ui rb 32:63 // update accumulator if a = 1 then acc 0:63 rd 0:63 the low word unsigned integer elements in r a and r b are multiplied to form a 64-bit product that is placed into r d. if a = 1, the result in r d is also placed into the accumulator. other registers altered: acc (if a = 1) figure 137. vector multiply word unsigned, modulo, integer (to accumulator) (evmwumi) spe apu user 0 5 6 1011 1516 2021 252627 31 000100 r d r a r b 10001a11000 0313263 r d (an accumulator r b x r a if evmwunia ) RM0004 instruction set 626/1176 evmwumiaa evmwumiaa vector multiply word unsigned, modulo, integer and accumulate evmwumiaa r d ,r a ,r b temp 0:63 ra 32:63 ui rb 32:63 rd 0:63 acc 0:63 + temp 0:63 // update accumulator acc 0:63 rd 0:63 the low word unsigned integer elements in r a and r b are multiplied. the intermediate product is added to the contents of the 64-bit accumulator, and the resulting value is placed into the accumulator and into r d. other registers altered: acc figure 138. vector multiply word unsigned, modulo, integer & accumulate (evmwumiaa) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10101011000 0313263 intermediate product accumulator r b x + r d and accumulator r a instruction set RM0004 627/1176 evmwumian evmwumian vector multiply word unsigned, modulo, integer and accumulate negative evmwumian r d ,r a ,r b temp 0:63 ra 32:63 ui rb 32:63 rd 0:63 acc 0:63 - temp 0:63 // update accumulator acc 0:63 rd 0:63 the low word unsigned integer elements in r a and r b are multiplied. the intermediate product is subtracted from the contents of the 64-bit accumulator, and the resulting value is placed into the accumulator and into r d. other registers altered: acc figure 139. vector multiply word unsigned, modulo, integer & accumulate negative (evmwumian) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 10111011000 0313263 intermediate product accumulator r b x ? r d and accumulator r a RM0004 instruction set 628/1176 evnand evnand vector nand evnand r d ,r a ,r b rd 0:31 ?(ra 0:31 & rb 0:31 ) // bitwise nand rd 32:63 ?(ra 32:63 & rb 32:63 ) // bitwise nand corresponding word elements of r a and r b are bitwise nanded. the result is placed in the corresponding element of r d. figure 140. vector nand (evnand) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000011110 0313263 r a r b nand nand r d instruction set RM0004 629/1176 evneg evneg vector negate evneg r d ,r a rd 0:31 neg(ra 0:31 ) rd 32:63 neg(ra 32:63 ) the negative of each element of r a is placed in r d. the negative of 0x8000_0000 (most negative number) returns 0x8000_0000. no overflow is detected. figure 141. vector negate (evneg) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001000001001 0313263 r a neg neg r d RM0004 instruction set 630/1176 evnor evnor vector nor evnor r d ,r a ,r b rd 0:31 ?(ra 0:31 | rb 0:31 ) // bitwise nor rd 32:63 ?(ra 32:63 | rb 32:63 ) // bitwise nor each element of r a and r b is bitwise nored. the result is placed in the corresponding element of r d. note: use evnand or evnor for evnot . figure 142. vector nor (evnor) simplified mnemonic: evnot r d ,r a performs a complement register evnot r d ,r a equivalent to evnor r d ,r a ,r a spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000011000 0313263 r a r b nor nor r d instruction set RM0004 631/1176 evor evor vector or evor r d ,r a ,r b rd 0:31 ra 0:31 | rb 0:31 //bitwise or rd 32:63 ra 32:63 | rb 32:63 // bitwise or each element of r a and r b is bitwise ored. the result is placed in the corresponding element of r d. figure 143. vector or (evor) simplified mnemonic: evmr r d ,r a handles moving of the full 64-bit spe register. evmr r d ,r a equivalent to evor r d ,r a ,r a spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000010111 0313263 r a r b or or r d RM0004 instruction set 632/1176 evorc evorc vector or with complement evorc r d ,r a ,r b rd 0:31 ra 0:31 | (?rb 0:31 ) // bitwise orc rd 32:63 ra 32:63 | (?rb 32:63 ) // bitwise orc each element of r a is bitwise ored with the complement of r b. the result is placed in the corresponding element of r d. figure 144. vector or with complement (evorc) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000011011 0313263 r a r b or or r d ? ? instruction set RM0004 633/1176 evrlw evrlw vector rotate left word evrlw r d ,r a ,r b nh rb 27:31 nl rb 59:63 rd 0:31 rotl(ra 0:31 , nh) rd 32:63 rotl(ra 32:63 , nl) each of the high and low elements of r a is rotated left by an amount specified in r b. the result is placed into r d. rotate values for each element of r a are found in bit positions r b[27?31] and r b[59?63]. figure 145. vector rotate left word (evrlw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000101000 0313263 r a r b r d RM0004 instruction set 634/1176 evrlwi evrlwi vector rotate left word immediate evrlwi r d ,r a , uimm n uimm rd 0:31 rotl(ra 0:31 , n) rd 32:63 rotl(ra 32:63 , n) both the high and low elements of r a are rotated left by an amount specified by a 5-bit immediate value. figure 146. vector rotate left word immediate (evrlwi) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a uimm 01000101010 0313263 r a uimm r d instruction set RM0004 635/1176 evrndw evrndw vector round word evrndw r d ,r a rd 0:31 (ra 0:31 +0x00008000) & 0xffff0000 // modulo sum rd 32:63 (ra 32:63 +0x00008000) & 0xffff0000 // modulo sum the 32-bit elements of r a are rounded into 16 bits. the result is placed into r d. the resulting 16 bits are placed in the most significant 16 bits of each element of r d, zeroing out the low order 16 bits of each element. figure 147. vector round word (evrndw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000001000001100 0313263 r a r d 0313263 15 16 47 48 RM0004 instruction set 636/1176 evsel evsel vector select evsel r d ,r a ,r b ,cr s ch cr crs*4 cl cr crs*4+1 if (ch = 1) then rd 0:31 ra 0:31 else rd 0:31 rb 0:31 if (cl = 1) then rd 32:63 ra 32:63 else rd 32:63 rb 32:63 if the most significant bit in the cr s field of cr is set, the high-order element of r a is placed in the high-order element of r d; otherwise, the high-order element of r b is placed into the high-order element of r d. if the next most significant bit in the cr s field of cr is set, the low- order element of r a is placed in the low-order element of r d, otherwise, the low-order element of r b is placed into the low-order element of r d. this is shown in figure 148 . figure 148. vector select (evsel) spe apu user 0 5 6 1011 1516 2021 2829 31 000100 r d r a r b 0 1001111 cr s 0313263 r a r b r d cl ch 1 0 0 1 instruction set RM0004 637/1176 evslw evslw vector shift left word evslw r d ,r a ,r b nh rb 26:31 nl rb 58:63 rd 0:31 sl(ra 0:31 , nh) rd 32:63 sl(ra 32:63 , nl) each of the high and low elements of r a are shifted left by an amount specified in r b. the result is placed into r d. the separate shift amounts for each element are specified by 6 bits in r b that lie in bit positions 26?31 and 58?63. shift amounts from 32 to 63 give a zero result. figure 149. vector shift left word (evslw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 0 1000100100 0313263 r a r b r d nh nl 0313263 26 58 high word shifted by value specified in nh low word shifted by value specified in nl 25 57 RM0004 instruction set 638/1176 evslwi evslwi vector shift left word immediate evslwi r d ,r a , uimm n uimm rd 0:31 sl(ra 0:31 , n) rd 32:63 sl(ra 32:63 , n) both high and low elements of r a are shifted left by the 5-bit uimm value and the results are placed in r d. figure 150. vector shift left word immediate (evslwi) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a uimm 01000100110 0313263 r a r d high and low words shifted by uimm value instruction set RM0004 639/1176 evsplatfi evsplatfi vector splat fractional immediate evsplatfi r d , simm rd 0:31 simm || 27 0 rd 32:63 simm || 27 0 the 5-bit immediate value is padded with trailing zeros and placed in both elements of r d, as shown in figure 151 . the simm ends up in bit positions r d[0?4] and r d[32?36]. figure 151. vector splat fractional immediate (evsplatfi) spe apu user 0 5 6 1011 1516 2021 31 000100 r d simm 0000001000101011 simm r d 0313263 sabcd sabcd000...........000000 sabcd000...........000000 RM0004 instruction set 640/1176 evsplati evsplati vector splat immediate evsplati r d , simm rd 0:31 exts(simm) rd 32:63 exts(simm) the 5-bit immediate value is sign extended and placed in both elements of r d, as shown in figure 152 . figure 152. evsplati sign extend spe apu user 0 5 6 1011 1516 2021 31 000100 r d simm 0000001000101001 simm r d 0313263 sabcd sss......................sabcd sss......................sabcd instruction set RM0004 641/1176 evsrwis evsrwis vector shift right word immediate signed evsrwis r d ,r a , uimm n uimm rd 0:31 exts(ra 0:31-n ) rd 32:63 exts(ra 32:63-n ) both high and low elements of r a are shifted right by the 5-bit uimm value. bits in the most significant positions vacated by the shift are filled with a copy of the sign bit. figure 153. vector shift right word immediate signed (evsrwis) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a uimm 01000100011 0313263 r a r d high and low words shifted by uimm value RM0004 instruction set 642/1176 evsrwiu evsrwiu vector shift right word immediate unsigned evsrwiu r d ,r a , uimm n uimm rd 0:31 extz(ra 0:31-n ) rd 32:63 extz(ra 32:63-n ) both high and low elements of r a are shifted right by the 5-bit uimm value; 0 bits are shifted in to the most significant position. bits in the most significant positions vacated by the shift are filled with a zero bit. figure 154. vector shift right word immediate unsigned (evsrwiu) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a uimm 01000100010 0313263 r a r d high and low words shifted by uimm value instruction set RM0004 643/1176 evsrws evsrws vector shift right word signed evsrws r d ,r a ,r b nh rb 26:31 nl rb 58:63 rd 0:31 exts(ra 0:31-nh ) rd 32:63 exts(ra 32:63-nl ) both the high and low elements of r a are shifted right by an amount specified in r b. the result is placed into r d. the separate shift amounts for each element are specified by 6 bits in r b that lie in bit positions 26?31 and 58?63. the sign bits are shifted in to the most significant position. shift amounts from 32 to 63 give a result of 32 sign bits. figure 155. vector shift right word signed (evsrws) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000100001 0313263 r a r b r d nh nl 0313263 26 58 low word shifted by value specified in nl high word shifted by value specified in nh 25 57 RM0004 instruction set 644/1176 evsrwu evsrwu vector shift right word unsigned evsrwu r d ,r a ,r b nh rb 26:31 nl rb 58:63 rd 0:31 extz(ra 0:31-nh ) rd 32:63 extz(ra 32:63-nl ) both the high and low elements of r a are shifted right by an amount specified in r b. the result is placed into r d. the separate shift amounts for each element are specified by 6 bits in r b that lie in bit positions 26?31 and 58?63. zero bits are shifted in to the most significant position. shift amounts from 32 to 63 give a zero result. figure 156. vector shift right word unsigned (evsrwu) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000100000 0313263 r a r b r d nh nl 0313263 26 58 low word shifted by value specified in nl high word shifted by value specified in nh 57 25 instruction set RM0004 645/1176 evstdd evstdd vector store double of double evstdd r s ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*8) mem(ea,8) rs 0:63 the contents of r s are stored as a double word in storage addressed by ea. figure 157 shows how bytes are stored in memory as determined by the endian mode. figure 157. evstdd results in big- and little-endian modes implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe, vector spfp, scalar dpfp apus user 0 5 6 1011 1516 2021 31 000100 r s r auimm (1) 01100100001 1. d = uimm * 8 cde f h ab g 01234567 cde f h ab g fedc a hg b gpr memory in big endian memory in little endian byte address RM0004 instruction set 646/1176 evstddx evstddx vector store double of double indexed evstddx r s ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) mem(ea,8) rs 0:63 the contents of r s are stored as a double word in storage addressed by ea. figure 158 shows how bytes are stored in memory as determined by the endian mode. figure 158. evstddx results in big- and little-endian modes note: implementation: if the ea is not double-word aligned, an alignment exception occurs. spe, vector spfp, scalar dpfp apus user 0 5 6 1011 1516 2021 31 000100 r s r a r b 01100100000 cde f h ab g cde f h ab g fedc a hg b gpr memory in big endian memory in little endian 01234567 byte address instruction set RM0004 647/1176 evstdh evstdh vector store double of four half words evstdh r s ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*8) mem(ea,2) rs 0:15 mem(ea+2,2) rs 16:31 mem(ea+4,2) rs 32:47 mem(ea+6,2) rs 48:63 the contents of r s are stored as four half words in storage addressed by ea. figure 159 shows how bytes are stored in memory as determined by the endian mode. figure 159. evstdh results in big- and little-endian modes note: implementation note: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r auimm (1) 01100100101 1. d = uimm * 8 cde f h ab g cde f h ab g dc f e g ba h gpr memory in big endian memory in little endian 01234567 byte address RM0004 instruction set 648/1176 evstdhx evstdhx vector store double of four half words indexed evstdhx r s ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) mem(ea,2) rs 0:15 mem(ea+2,2) rs 16:31 mem(ea+4,2) rs 32:47 mem(ea+6,2) rs 48:63 the contents of r s are stored as four half words in storage addressed by ea. figure 160 shows how bytes are stored in memory as determined by the endian mode. figure 160. evstdhx results in big- and little-endian modes note: implementation: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r a r b 01100100100 cde f h ab g cde f h ab g dc f e g ba h gpr memory in big endian memory in little endian 01234567 byte address instruction set RM0004 649/1176 evstdw evstdw vector store double of two words evstdw r s ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*8) mem(ea,4) rs 0:31 mem(ea+4,4) rs 32:63 the contents of r s are stored as two words in storage addressed by ea. figure 161 shows how bytes are stored in memory as determined by the endian mode. figure 161. evstdw results in big- and little-endian modes note: implementation: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r auimm (1) 01100100011 1. d = uimm * 8 cde f h ab g 01234567 cde f h ab g bahg e dc f gpr memory in big endian memory in little endian byte address RM0004 instruction set 650/1176 evstdwx evstdwx vector store double of two words indexed evstdwx r s ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) mem(ea,4) rs 0:31 mem(ea+4,4) rs 32:63 the contents of r s are stored as two words in storage addressed by ea. figure 162 shows how bytes are stored in memory as determined by the endian mode. figure 162. evstdwx results in big- and little-endian modes note: implementation: if the ea is not double-word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r a r b 01100100010 cde f h ab g 01234567 cde f h ab g bahg e dc f gpr memory in big endian memory in little endian byte address instruction set RM0004 651/1176 evstwhe evstwhe vector store word of two half words from even evstwhe r s ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) mem(ea,2) rs 0:15 mem(ea+2,2) rs 32:47 the even half words from each element of r s are stored as two half words in storage addressed by ea. figure 163 shows how bytes are stored in memory as determined by the endian mode. figure 163. evstwhe results in big- and little-endian modes note: implementation: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r auimm (1) 01100110001 1. d = uimm * 4 cde f h ab g ef ab fe ba gpr memory in big endian memory in little endian 0123 byte address RM0004 instruction set 652/1176 evstwhex evstwhex vector store word of two half words from even indexed evstwhex r s ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) mem(ea,2) rs 0:15 mem(ea+2,2) rs 32:47 the even half words from each element of r s are stored as two half words in storage addressed by ea. figure 164 shows how bytes are stored in memory as determined by the endian mode. figure 164. evstwhex results in big- and little-endian modes note: implementation: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r a r b 01100110000 cde f h ab g ef ab fe ba gpr memory in big endian memory in little endian 0123 byte address instruction set RM0004 653/1176 evstwho evstwho vector store word of two half words from odd evstwho r s ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) mem(ea,2) rs 16:31 mem(ea+2,2) rs 48:63 the odd half words from each element of r s are stored as two half words in storage addressed by ea. figure 165. evstwho results in big- and little-endian modes spe apu user 0 5 6 1011 1516 2021 31 000100 r s r auimm (1) 01100110101 1. d = uimm * 4 cde f h ab g 0123 gh cd hg dc gpr memory in big endian memory in little endian byte address RM0004 instruction set 654/1176 evstwhox evstwhox vector store word of two half words from odd indexed evstwhox r s ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) mem(ea,2) rs 16:31 mem(ea+2,2) rs 48:63 the odd half words from each element of r s are stored as two half words in storage addressed by ea. figure 166 shows how bytes are stored in memory as determined by the endian mode. figure 166. evstwhox results in big- and little-endian modes note: implementation: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r a r b 01100110100 cde f h ab g gh cd hg dc gpr memory in big endian memory in little endian 0123 byte address instruction set RM0004 655/1176 evstwwe evstwwe vector store word of word from even evstwwe r s ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) mem(ea,4) rs 0:31 the even word of r s is stored in storage addressed by ea. figure 167 shows how bytes are stored in memory as determined by the endian mode. figure 167. evstwwe results in big- and little-endian modes note: implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r auimm (1) 01100111001 1. d = uimm * 4 cde f h ab g cd ab ba dc gpr memory in big endian memory in little endian 0123 byte address RM0004 instruction set 656/1176 evstwwex evstwwex vector store word of word from even indexed evstwwex r s ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) mem(ea,4) rs 0:31 the even word of r s is stored in storage addressed by ea. figure 168 shows how bytes are stored in memory as determined by the endian mode. figure 168. evstwwex results in big- and little-endian modes note: implementation: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r a r b 01100111000 cde f h ab g cd ab ba dc gpr memory in big endian memory in little endian 0123 byte address instruction set RM0004 657/1176 evstwwo evstwwo vector store word of word from odd evstwwo r s ,d(r a ) if (ra = 0) then b 0 else b (ra) ea b + extz(uimm*4) mem(ea,4) rs 32:63 the odd word of r s is stored in storage addressed by ea. figure 169 shows how bytes are stored in memory as determined by the endian mode. figure 169. evstwwo results in big- and little-endian modes note: implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r auimm (1) 01100111101 1. d = uimm * 4 cde f h ab g gh ef fe hg gpr memory in big endian memory in little endian 0123 byte address RM0004 instruction set 658/1176 evstwwox evstwwox vector store word of word from odd indexed evstwwox r s ,r a ,r b if (ra = 0) then b 0 else b (ra) ea b + (rb) mem(ea,4) rs 32:63 the odd word of r s is stored in storage addressed by ea. figure 170 shows how bytes are stored in memory as determined by the endian mode. figure 170. evstwwox results in big- and little-endian modes note: implementation note: if the ea is not word aligned, an alignment exception occurs. spe apu user 0 5 6 1011 1516 2021 31 000100 r s r a r b 01100111100 cde f h ab g gh ef fe hg gpr memory in big endian memory in little endian 0123 byte address instruction set RM0004 659/1176 evsubfsmiaaw evsubfsmiaaw vector subtract signed, modulo, integer to accumulator word evsubfsmiaaw r d ,r a // high rd 0:31 acc 0:31 - ra 0:31 // low rd 32:63 acc 32:63 - ra 32:63 // update accumulator acc 0:63 rd 0:63 each word element in r a is subtracted from the corresponding element in the accumulator and the difference is placed into the corresponding r d word and into the accumulator. other registers altered: acc figure 171. vector subtract signed, modulo, integer to accumulator word (evsubfsmiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011001011 0313263 accumulator r a ? ? r d and accumulator RM0004 instruction set 660/1176 evsubfssiaaw evsubfssiaaw vector subtract signed, saturate, integer to accumulator word evsubfssiaaw r d ,r a // high temp 0:63 exts(acc 0:31 ) - exts(ra 0:31 ) ovh temp 31 temp 32 rd 0:31 saturate(ovh, temp 31 , 0x80000000, 0x7fffffff, temp 32:63 ) // low temp 0:63 exts(acc 32:63 ) - exts(ra 32:63 ) ovl temp 31 temp 32 rd 32:63 saturate(ovl, temp 31 , 0x80000000, 0x7fffffff, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl each signed integer word element in r a is sign-extended and subtracted from the corresponding sign-extended element in the accumulator, saturating if overflow occurs, and the results are placed in r d and the accumulator. any overfl ow is recorded in the spefscr overflow and summary overflow bits. other registers altered: spefscr acc figure 172. vector subtract signed, saturate, integer to accumulator word (evsubfssiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011000011 0313263 accumulator r a ? ? r d and accumulator instruction set RM0004 661/1176 evsubfumiaaw evsubfumiaaw vector subtract unsigned, modulo, integer to accumulator word evsubfumiaaw r d ,r a // high rd 0:31 acc 0:31 - ra 0:31 // low rd 32:63 acc 32:63 - ra 32:63 // update accumulator acc 0:63 rd 0:63 each unsigned integer word element in r a is subtracted from the corresponding element in the accumulator and the results are placed in r d and into the accumulator. other registers altered: acc figure 173. vector subtract unsigned, modulo, integer to accumulator word (evsubfumiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011001010 0313263 accumulator r a ? ? r d and accumulator RM0004 instruction set 662/1176 evsubfusiaaw evsubfusiaaw vector subtract unsigned, saturate, integer to accumulator word evsubfusiaaw r d ,r a // high temp 0:63 extz(acc 0:31 ) - extz(ra 0:31 ) ovh temp 31 rd 0:31 saturate(ovh, temp 31 , 0x00000000, 0x00000000, temp 32:63 ) // low temp 0:63 exts(acc 32:63 ) - exts(ra 32:63 ) ovl temp 31 rd 32:63 saturate(ovl, temp 31 , 0x00000000, 0x00000000, temp 32:63 ) // update accumulator acc 0:63 rd 0:63 spefscr ovh ovh spefscr ov ovl spefscr sovh spefscr sovh | ovh spefscr sov spefscr sov | ovl each unsigned integer word element in r a is zero-extended and subtracted from the corresponding zero-extended element in the accumulator, saturating if underflow occurs, and the results are placed in r d and the accumulator. any underflow is recorded in the spefscr overflow and summary overflow bits. other registers altered: spefscr acc figure 174. vector subtract unsigned, saturate, integer to accumulator word (evsubfusiaaw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a 0000010011000010 0313263 accumulator r a ? ? r d and accumulator instruction set RM0004 663/1176 evsubfw evsubfw vector subtract from word evsubfw r d ,r a ,r b rd 0:31 rb 0:31 - ra 0:31 // modulo difference rd 32:63 rb 32:63 - ra 32:63 // modulo difference each signed integer element of r a is subtracted from the corresponding element of r b and the results are placed into r d. figure 175. vector subtract from word (evsubfw) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000000100 0313263 r b r a ? ? r d RM0004 instruction set 664/1176 evsubifw evsubifw vector subtract immediate from word evsubifw r d , uimm ,r b rd 0:31 rb 0:31 - extz(uimm) // modulo difference rd 32:63 rb 32:63 - extz(uimm) // modulo difference uimm is zero-extended and subtracted from both the high and low elements of r b. note that the same value is subtracted from both elements of the register. uimm is 5 bits. figure 176. vector subtract immediate from word (evsubifw) spe apu user 0 5 6 1011 1516 2021 31 000100 r duimm r b 01000000110 0313263 r b uimm ? ? r d and accumulator uimm instruction set RM0004 665/1176 evxor evxor vector xor evxor r d ,r a ,r b rd 0:31 ra 0:31 rb 0:31 // bitwise xor rd 32:63 ra 32:63 rb 32:63 // bitwise xor each element of r a and r b is exclusive-ored. the results are placed in r d. figure 177. vector xor (evxor) spe apu user 0 5 6 1011 1516 2021 31 000100 r d r a r b 01000010110 0313263 r a r b xor xor r d RM0004 instruction set 666/1176 extsb extsb extend sign (byte | half word) extsb r a ,r s (sz=0b01, rc=0) extsb. r a ,r s (sz=0b01, rc=1) extsh r a ,r s (sz=0b00, rc=0) extsh. r a ,r s (sz=0b00, rc=1) if ?extsb[.]? then n 56 if ?extsh[.]? then n 48 if ?extsw? then n 32 if rc=1 then do lt rs n:63 < 0 gt rs n:63 > 0 eq rs n:63 = 0 cr0 lt || gt || eq || so s rs n ra n s || rs n:63 for extsb [ . ], the contents of r s[56?63] are placed into r a[56?63]. bit r s[56] is copied into bits 0?55 of r a. if rc=1, cr field 0 is set to reflect the result. for extsh [ . ], the contents of r s[48?63] are placed into r a[48?63]. r s[48] is copied into r a[0? 47]. if rc=1, cr field 0 is set to reflect the result. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 23242526 3031 011111 r s r a /// 111sz11010rc instruction set RM0004 667/1176 _ extsb x _extsb x extend sign (byte | halfword) se_extsb r x se_extsh r x if se_extsb then n 56 if se_extsh then n 48 if ?extsw? then n 32 if rc=1 then do lt gpr(rs) n:63 < 0 gt gpr(rs) n:63 > 0 eq gpr(rs) n:63 = 0 cr0 lt || gt || eq || so s gpr(rs or rx) n gpr(ra or rx) n-32 s || gpr(rs or rx) n:63 for se_extsb , the contents of bits 56?63 of gpr( r x) are placed into bits 56?63 of gpr( r x). bit 56 of the contents of gpr( r x) is copied into bits 32?55 of gpr( r x). for se_extsh , the contents of bits 48?63 of gpr( r x) are placed into bits 48?63 of gpr( r x). bit 48 of the contents of gpr( r x) is copied into bits 32?47 of gpr( r x). special registers altered: cr0 (if rc=1) 056111215 000000001101 rx 056111215 000000001111 rx vle user RM0004 instruction set 668/1176 _ extz x _extz x extend zero (byte | halfword) se_extzb r x se_extzh r x if ?se_extzb? then n 56 if ?se_extzh? then n 48 gpr(rx) n-32 0 || gpr(rx) n:63 for se_extzb , the contents of bits 56?63 of gpr( r x) are placed into bits 56?63 of gpr( r x). bits 32?55 of gpr( r x) are cleared. for se_extzh , the contents of bits 48?63 of gpr( r x) are placed into bits 48?63 of gpr( r x). bits 32?47 of gpr( r x) are cleared. special registers altered: none 056111215 000000001100 rx 056111215 000000001110 rx vle user instruction set RM0004 669/1176 fabs fabs floating absolute value fabs fr d ,fr b(rc=0) fabs. fr d ,fr b(rc=1) frd) 0b0||frb 1:63 the contents of fr b with bit 0 cleared are placed into fr d. if msr[fp]=0, an attempt to execute fabs [ . ] causes a floating-point unavailable interrupt. other registers altered: cr1 fx || fex || vx || ox (if rc=1) book e user 0 5 6 1011 1516 2021 3031 111111 fr d /// fr b 0100001000rc RM0004 instruction set 670/1176 fadd fadd floating add [single] fadd fr d ,fr a ,fr b(p=1, rc=0) fadd. fr d ,fr a ,fr b(p=1, rc=1) fadds fr d ,fr a ,fr b(p=0, rc=0) fadds. fr d ,fr a ,fr b(p=0, rc=1) if p=1 then frd fra + dp frb else frd fra + sp frb the floating-point operand in fr a is added to the floating-point operand in fr b. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], and placed into fr d. floating-point addition is based on expo nent comparison and addition of the two significands. the exponents of the two operands are compared, and the significand accompanying the smaller exponent is shifted right, with its exponent increased by one for each bit shifted, until the two exponents are equal. the two significands are then added or subtracted as appropriate, depending on the signs of the operands, to form an intermediate sum. all 53 bits of the significand as well as all three guard bits (g, r, and x) enter into the computation. if a carry occurs, the sum?s significand is shifted right one bit position and the exponent is increased by one. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. if msr[fp]=0, an attempt to execute fadd [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan vxisi cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a fr b /// 10101rc instruction set RM0004 671/1176 fcfid fcfid floating convert from integer doubleword fcfid fr d ,fr b sign frb 0 exp 63 frac 0:63 frb if frac 0:63 = 0 then go to zero operand if sign = 1 then frac 0:63 ? frac 0:63 + 1 do while frac 0 = 0 /* do loop 0 times if frb = max negative integer */ frac 0:63 frac 1:63 || 0b0 exp exp : 1 end round float( sign, exp, frac 0:63 , fpscr[rn] ) if sign = 0 then fpscr[fprf] ?+normal number? if sign = 1 then fpscr[fprf] ?:normal number? frd 0 sign frd[1-11] exp + 1023 /* exp + bias */ frd[12-63] frac 1:52 done zero operand: fpscr[fr,fi] 0b00 fpscr[fprf] ?+zero? frd 0x0000_0000_0000_0000 done round float( sign, exp, frac 0:63 , round_mode ): inc 0 lsb frac 52 gbit frac 53 rbit frac 54 xbit frac 55:63 > 0 if round_mode = 0b00 then do /* comparison ignores u bits */ if sign || lsb || gbit || rbit || xbit = 0bu11uu then inc 1 if sign || lsb || gbit || rbit || xbit = 0bu011u then inc 1 if sign || lsb || gbit || rbit || xbit = 0bu01u1 then inc 1 end if round_mode = 0b10 then do /* comparison ignores u bits */ if sign || lsb || gbit || rbit || xbit = 0b0u1uu then inc 1 if sign || lsb || gbit || rbit || xbit = 0b0uu1u then inc 1 if sign || lsb || gbit || rbit || xbit = 0b0uuu1 then book e user 0 5 6 1011 1516 2021 3031 111111 fr d /// fr b 1101001110 / RM0004 instruction set 672/1176 inc 1 end if round_mode = 0b11 then do /* comparison ignores u bits */ if sign || lsb || gbit || rbit || xbit = 0b1u1uu then inc 1 if sign || lsb || gbit || rbit || xbit = 0b1uu1u then inc 1 if sign || lsb || gbit || rbit || xbit = 0b1uuu1 then inc 1 end frac 0:52 frac 0:52 + inc if carry_out = 1 then exp exp + 1 fpscr[fr] inc fpscr[fi] gbit | rbit | xbit fpscr[xx] fpscr[xx] | fpscr[fi] return the 64-bit signed operand in fr b is converted to an infinitely precise floating-point integer. the result of the conversion is rounded to double-precision, as specified by fpscr[rn], and placed into fr d. fpscr[fprf] is set to the class and sign of th e result. fpscr[fr] is set if the result is incremented when rounded. fpscr[fi] is set if the result is inexact. if msr[fp]=0, an attempt to execute fcfid causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx xx instruction set RM0004 673/1176 fcmpu fcmpu floating compare fcmpu cr d ,fr a ,fr b(u=0) fcmpo cr d ,fr a ,fr b(u=1) if fra is a nan or frb is a nan then c 0b0001 else if fra < frb then c 0b1000 else if fra > frb then c 0b0100 else c 0b0010 fpcc c cr 4 cr d:4 cr d+3 c if ?fcmpu? & (fra is a snan or frb is a snan) then vxsnan 1 if ?fcmpo? then do if fra is a snan or frb is a snan then do if ve=0 then vxvc 1 else if fra is a qnan or frb is a qnan then vxvc 1 the floating-point operand in fr a is compared to the floating-point operand in fr b. the result of the compare is placed into cr field cr d and the fpcc. if either of the operands is a nan, either quiet or signaling, the cr field cr d and the fpcc are set to reflect unordered. if fcmpu , then if either of the operands is a signaling nan, vxsnan is set. if fcmpo , then do the following: if either of the operands is a signaling nan and invalid operation is disabled (ve=0), vxvc is set. if neither operand is a signaling nan but at least one operand is a quiet na n, then vxvc is set. if msr[fp]=0, an attempt to execute fcmpo or fcmpu causes a floating-point unavailable interrupt. other registers altered: cr field cr d fpcc fx vxsnan vxvc(if fcmpo ) book e user 0 5 6 1011 1516 2021 242526 3031 111111 cr d// fr a fr b 0000u00000 / RM0004 instruction set 674/1176 fctid fctid floating convert to integer doubleword fctid fr d ,fr b(z=0) fctidz fr d ,fr b(z=1) if ?fctid[ . ]? then round_mode fpscr[rn] if ?fctidz[ . ]? then round_mode 0b01 sign frb 0 if frb[1:11] = 2047 and frb[12:63] = 0 then goto infinity operand if frb[1:11] = 2047 and frb 12 = 0 then goto snan operand if frb[1:11] = 2047 and frb 12 = 1 then goto qnan operand if frb[1:11] > 1086 then goto large operand if frb[1:11] > 0 then exp frb[1:11] : 1023 /* exp : bias */ if frb[1:11] = 0 then exp :1022 /* normal; need leading 0 for later complement */ if frb[1:11] > 0 then frac 0:64 0b01 || frb[12:63] || 11 0 /* denormal */ if frb[1:11] = 0 then frac 0:64 0b00 || frb[12:63] || 11 0 gbit || rbit || xbit 0b000 do i=1,63:exp /* do the loop 0 times if exp = 63 */ frac 0:64 || gbit || rbit || xbit 0b0 || frac 0:64 || gbit || (rbit | xbit) end round integer( sign, frac 0:64 , gbit, rbit, xbit, round_mode ) /* needed leading 0 for :2 64 < frb < :2 63 */ if sign=1 then frac 0:64 ? frac 0:64 + 1 if frac 0:64 > 2 63 :1 then goto large operand if frac 0:64 < :2 63 then goto large operand fpscr[xx] fpscr[xx] | fpscr[fi] fpscr[fprf] undefined frd frac 1:64 done round integer( sign,frac0:64, gbit, rbit, xbit, round_mode ): inc 0 if round_mode = 0b00 then /* comparison ignores u bits */ do if sign || frac 64 || gbit || rbit || xbit = 0bu11uu then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0bu011u then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0bu01u1 then inc 1 end if round_mode = 0b10 then /* comparison ignores u bits */ do if sign || frac 64 || gbit || rbit || xbit = 0b0u1uu then inc 1 book e user 0 5 6 1011 1516 2021 293031 111111 fr d /// fr b 110010111z / instruction set RM0004 675/1176 if sign || frac 64 || gbit || rbit || xbit = 0b0uu1u then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0b0uuu1 then inc 1 end if round_mode = 0b11 then /* comparison ignores u bits */ do if sign || frac 64 || gbit || rbit || xbit = 0b1u1uu then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0b1uu1u then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0b1uuu1 then inc 1 end frac 0:64 frac 0:64 + inc fpscr[fr] inc fpscr[fi] gbit | rbit | xbit return infinity operand: fpscr[fr,fi,vxcvi] 0b001 if fpscr[ve] = 0 then do if sign = 0 then frd 0x7fff_ffff_ffff_ffff if sign = 1 then frd 0x8000_0000_0000_0000 fpscr[fprf] undefined end done snan operand: fpscr[fr,fi,vxsnan,vxcvi] 0b0011 if fpscr[ve] = 0 then do frd 0x8000_0000_0000_0000 fpscr[fprf] undefined end done qnan operand: fpscr[fr,fi,vxcvi] 0b001 if fpscr[ve] = 0 then do frd 0x8000_0000_0000_0000 fpscr[fprf] undefined end done large operand: fpscr[fr,fi,vxcvi] 0b001 if fpscr[ve] = 0 then do if sign = 0 then frd 0x7fff_ffff_ffff_ffff if sign = 1 then frd 0x8000_0000_0000_0000 fpscr[fprf] undefined end done for fctid or fctid. , the rounding mode is specified by fpscr[rn]. for fctidz or fctidz. , the rounding mode used is round toward zero. RM0004 instruction set 676/1176 the floating-point operand in fr b is converted to a 64-bit signed integer, using the rounding mode specified by the instruction, and placed into fr d. if the floating-point operand in fr b is greater than 2 63 ?1, then 0x7fff_ffff_ffff_ffff is placed into fr d. if the floating-point operand in fr b is less than ?2 63 , 0x8000_0000_0000_0000 is placed into fr d. except for enabled invalid operation exceptio ns, fpscr[fprf] is undefined. fpscr[fr] is set if the result is incremented when rounded. fpscr[fi] is set if the result is inexact. if msr[fp]=0, an attempt to execute fctid [ z ] causes a floating-point unavailable interrupt. other registers altered: fprf (undefined) fr fi fx xx vxsnan vxcvi instruction set RM0004 677/1176 fctiw fctiw floating convert to integer word fctiw fr d ,fr b(z=0, rc=0) fctiw. fr d ,fr b(z=0, rc=1) fctiwz fr d ,fr b(z=1, rc=0) fctiwz. fr d ,fr b(z=1, rc=1) if ?fctiw[ . ]? then round_mode fpscr[rn] if ?fctiwz[ . ]? then round_mode 0b01 sign frb 0 if frb[1:11] = 2047 and frb[12:63] = 0 then goto infinity operand if frb[1:11] = 2047 and frb 12 = 0 then goto snan operand if frb[1:11] = 2047 and frb 12 = 1 then goto qnan operand if frb[1:11] > 1086 then goto large operand if frb[1:11] > 0 then exp frb[1:11] : 1023 /* exp : bias */ if frb[1:11] = 0 then exp :1022 /* normal; need leading 0 for later complement */ if frb[1:11] > 0 then frac 0:64 0b01 || frb[12:63] || 11 0 /* denormal */ if frb[1:11] = 0 then frac 0:64 0b00 || frb[12:63] || 11 0 gbit || rbit || xbit 0b000 do i=1,63:exp /* do the loop 0 times if exp = 63 */ frac 0:64 || gbit || rbit || xbit 0b0 || frac 0:64 || gbit || (rbit | xbit) end round integer( sign, frac 0:64 , gbit, rbit, xbit, round_mode ) /* needed leading 0 for :2 64 < frb < :2 63 */ if sign=1 then frac 0:64 ? frac 0:64 + 1 if frac 0:64 > 2 31 :1 then goto large operand if frac 0:64 < :2 31 then goto large operand fpscr[xx] fpscr[xx] | fpscr[fi] frd 0xuuuu_uuuu || frac 33:64 /* u is undefined hex digit */ fpscr[fprf] undefined done round integer( sign, frac0:64, gbit, rbit, xbit, round_mode ): inc 0 if round_mode = 0b00 then /* comparison ignores u bits */ do if sign || frac 64 || gbit || rbit || xbit = 0bu11uu then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0bu011u then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0bu01u1 then inc 1 end if round_mode = 0b10 then /* comparison ignores u bits */ do book e user 0 5 6 1011 1516 2021 293031 111111 fr d /// fr b 000000111zrc RM0004 instruction set 678/1176 if sign || frac 64 || gbit || rbit || xbit = 0b0u1uu then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0b0uu1u then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0b0uuu1 then inc 1 end if round_mode = 0b11 then /* comparison ignores u bits */ do if sign || frac 64 || gbit || rbit || xbit = 0b1u1uu then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0b1uu1u then inc 1 if sign || frac 64 || gbit || rbit || xbit = 0b1uuu1 then inc 1 end frac 0:64 frac 0:64 + inc fpscr[fr] inc fpscr[fi] gbit | rbit | xbit return infinity operand: fpscr[fr,fi,vxcvi] 0b001 if fpscr[ve] = 0 then do /* u is undefined hex digit */ if sign = 0 then frd 0xuuuu_uuuu_7fff_ffff if sign = 1 then frd 0xuuuu_uuuu_8000_0000 fpscr[fprf] undefined end done snan operand: fpscr[fr,fi,vxsnan,vxcvi] 0b0011 if fpscr[ve] = 0 then do /* u is undefined hex digit */ frd 0xuuuu_uuuu_8000_0000 fpscr[fprf] undefined end done qnan operand: fpscr[fr,fi,vxcvi] 0b001 if fpscr[ve] = 0 then do /* u is undefined hex digit */ frd 0xuuuu_uuuu_8000_0000 fpscr[fprf] undefined end done large operand: fpscr[fr,fi,vxcvi] 0b001 if fpscr[ve] = 0 then do /* u is undefined hex digit */ if sign = 0 then frd 0xuuuu_uuuu_7fff_ffff if sign = 1 then frd 0xuuuu_uuuu_8000_0000 fpscr[fprf] undefined end done for fctiw or fctiw. , the rounding mode is specified by fpscr[rn]. instruction set RM0004 679/1176 for fctiwz or fctiwz. , the rounding mode used is round toward zero. the floating-point operand in fr b is converted to a 32-bit signed integer, using the rounding mode specified by the instruction, and placed into fr d[32?63]; fr d[0?31] are undefined. if the operand in fr b is greater than 2 31 ?1, then fr d[32?63] are set to 0x7fff_ffff. if the operand in fr b is less than ?2 31 , then fr d[32?63] are set to 0x8000_0000. except for enabled invalid operation exceptio ns, fpscr[fprf] is undefined. fpscr[fr] is set if the result is incremented when rounded. fpscr[fi] is set if the result is inexact. if msr[fp]=0, an attempt to execute fctiw [ z ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf (undefined) fr fi fx xx vxsnan vxcvi cr1 fx || fex || vx || ox (if rc=1) RM0004 instruction set 680/1176 fdiv fdiv floating divi de [single] fdiv fr d ,fr a ,fr b(p=1, rc=0) fdiv. fr d ,fr a ,fr b(p=1, rc=1) fdivs fr d ,fr a ,fr b(p=0, rc=0) fdivs. fr d ,fr a ,fr b(p=0, rc=1) if p=1 then frd fra dp frb else frd fra sp frb the floating-point operand in fr a is divided by the floating-point operand in fr b. the remainder is not supplied as a result. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], and placed into fr d. floating-point division is based on exponent subtraction and division of the significands. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1 and zero divide exceptions when fpscr[ze]=1. if msr[fp]=0, an attempt to execute fdiv [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux zx xx vxsnan vxidi vxzdz cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a fr b /// 10010rc instruction set RM0004 681/1176 fmadd fmadd floating multiply-add [single] fmadd fr d ,fr a ,fr c ,fr b(p=1, rc=0) fmadd. fr d ,fr a ,fr c ,fr b(p=1, rc=1) fmadds fr d ,fr a ,fr c ,fr b(p=0, rc=0) fmadds. fr d ,fr a ,fr c ,fr b(p=0, rc=1) if p=1 then frd [fra fp frc] + dp frb else frd [fra fp frc] + sp frb the floating-point operand in fr a is multiplied by the floating-point operand in fr c. the floating-point operand in fr b is added to this intermediate result. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], and placed into fr d. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. if msr[fp]=0, an attempt to execute fmadd [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan vxisi vximz cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a fr b fr c 11101rc RM0004 instruction set 682/1176 fmr fmr floating move register fmr fr d ,fr b(rc=0) fmr. fr d ,fr b(rc=1) frd frb the contents of fr b are placed into fr d. if msr[fp]=0, an attempt to execute fmr [ . ] causes a floating-point unavailable interrupt. other registers altered: cr1 fx || fex || vx || ox (if rc=1) book e user 0 5 6 1011 1516 2021 3031 111111 fr d /// fr b 0001001000rc instruction set RM0004 683/1176 fmsub fmsub floating multiply-subtract [single] fmsub fr d ,fr a ,fr c ,fr b(p=1, rc=0) fmsub. fr d ,fr a ,fr c ,fr b(p=1, rc=1) fmsubs fr d ,fr a ,fr c ,fr b(p=0, rc=0 ) fmsubs. fr d ,fr a ,fr c ,fr b(p=0, rc=1) if p=1 then frd [fra fp frc] - dp frb else frd [fra fp frc] - sp frb the floating-point operand in fr a is multiplied by the floating-point operand in fr c. the floating-point operand in fr b is subtracted from this intermediate result. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], and placed into fr d. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. if msr[fp]=0, an attempt to execute fmsub [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan vxisi vximz cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a fr b fr c 11100rc RM0004 instruction set 684/1176 fmul fmul floating multiply [single] fmul fr d ,fr a ,fr c(p=1, rc=0) fmul. fr d ,fr a ,fr c(p=1, rc=1) fmuls fr d ,fr a ,fr c(p=0, rc=0) fmuls. fr d ,fr a ,fr c(p=0, rc=1) if p=1 then frd fra dp frc else frd fra sp frc the floating-point operand in fr a is multiplied by the floating-point operand in fr c. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], and placed into fr d. floating-point multiplication is based on exponent addition and multiplication of the significands. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. if msr[fp]=0, an attempt to execute fmul [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan vximz cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a/// fr c 11001rc instruction set RM0004 685/1176 fnabs fnabs floating negative absolute value fnabs fr d ,fr b(rc=0) fnabs. fr d ,fr b(rc=1) frd 0b1||frb 1:63 the contents of fr b with bit 0 set are placed into fr d. if msr[fp]=0, an attempt to execute fnabs [ . ] causes a floating-point unavailable interrupt. other registers altered: cr1 fx || fex || vx || ox (if rc=1) book e user 0 5 6 1011 1516 2021 3031 111111 fr d /// fr b 0010001000rc RM0004 instruction set 686/1176 fneg fneg floating negate fneg fr d ,fr b (rc=0) fneg. fr d ,fr b(rc=1) frd ? frb0||frb 1:63 the contents of fr b with bit 0 inverted are placed into fr d. if msr[fp]=0, an attempt to execute fneg [ . ] causes a floating-point unavailable interrupt. other registers altered: cr1 fx || fex || vx || ox (if rc=1) book e user 0 5 6 1011 1516 2021 3031 111111 fr d /// fr b 0000101000rc instruction set RM0004 687/1176 fnmadd fnmadd floating negative multiply-add [single] fnmadd fr d ,fr a ,fr c ,fr b(p=1, rc=0) fnmadd. fr d ,fr a ,fr c ,fr b(p=1, rc=1) fnmadds fr d ,fr a ,fr c ,fr b(p=0, rc=0) fnmadds. fr d ,fr a ,fr c ,fr b(p=0, rc=1) if p=1 then frd -([fra fp frc] + dp frb) else frd -([fra fp frc] + sp frb) the floating-point operand in fr a is multiplied by the floating-point operand in fr c. the floating-point operand in fr b is added to this intermediate result. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], then negated and placed into fr d. this instruction produces the same result as would be obtained by using the floating multiply-add instruction and then negating the result, with the following exceptions. qnans propagate with no effect on their sign bit. qnans that are generated as the result of a disabled invalid operation exception have a sign bit of 0. snans that are converted to qnans as the result of a disabled invalid operation exception retain the sign bit of the snan. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. an attempt to execute fnmadd [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan vxisi vximz cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a fr b fr c 11111rc RM0004 instruction set 688/1176 fnmsub fnmsub floating negative multiply-subtract [single] fnmsub fr d ,fr a ,fr c ,fr b(p=1, rc=0) fnmsub. fr d ,fr a ,fr c ,fr b(p=1, rc=1) fnmsubs fr d ,fr a ,fr c ,fr b(p=0, rc=0) fnmsubs. fr d ,fr a ,fr c ,fr b(p=0, rc=1) if p=1 then frd -([fra fp frc] : dp frb) else frd -([fra fp frc] : sp frb) the floating-point operand in fr a is multiplied by the floating-point operand in fr c. the floating-point operand in fr b is subtracted from this intermediate result. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], then negated and placed into fr d. this instruction produces the same result as would be obtained by using the floating multiply-subtract instruction and then negatin g the result, with the following exceptions. qnans propagate with no effect on their sign bit. qnans that are generated as the result of a disabled invalid operation exception have a sign bit of 0. snans that are converted to qnans as the result of a disabled invalid operation exception retain the sign bit of the snan. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. an attempt to execute fnmsub [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan vxisi vximz cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a fr b fr c 11110rc instruction set RM0004 689/1176 fres fres floating reciprocal estimate single fres fr d ,fr b(rc=0) fres. fr d ,fr b(rc=1) frd fpreciprocalestimate( frb ) a single-precision estimate of the reciprocal of the floating-point operand in fr b is placed into fr d. the estimate placed into fr d is correct to a precision of one part in 256 of the reciprocal of ( fr b), that is, in this example, x is the initial value in fr b. note that the value placed into fr d may vary between implementations, and between different executions on the same implementation. operation with various special values of the operand is summarized in ta b l e 2 0 4 . fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1 and zero divide exceptions when fpscr[ze]=1. if msr[fp]=0, an attempt to execute fres [ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr (undefined) fi (undefined) fx ox ux zx vxsnan cr1 fx || fex || vx || ox (if rc=1) book e user 0 5 6 1011 1516 2021 2526 3031 111011 fr d /// fr b /// 11000rc table 204. operations with special values operand result exception ? ?0 none ?0 ? (no result if fpscr[ze] = 1) zx +0 + (no result if fpscr[ze] = 1) zx + +0 none snan qnan (no result if fpscr[ve] = 1.) vxsnan qnan qnan none estimate - 1 x -- - 1 x -- - ------------------------------- 1 256 --------- - RM0004 instruction set 690/1176 frsp frsp floating round to single-precision frsp fr d ,fr b(rc=0) frsp. fr d ,fr b(rc=1) if frb[1:11] < 897 and frb 1:63 > 0 then do if fpscr[ue] = 0 then goto disabled exponent underflow if fpscr[ue] = 1 then goto enabled exponent underflow if frb[1:11] > 1150 and frb[1:11] < 2047 then do if fpscr[oe] = 0 then goto disabled exponent overflow if fpscr[oe] = 1 then goto enabled exponent overflow if frb[1:11] > 896 and frb[1:11] < 1151 then goto normal operand if frb 1:63 = 0 then goto zero operand if frb[1:11] = 2047 then do if frb[12:63] = 0 then goto infinity operand if frb 12 = 1 then goto qnan operand if frb 12 = 0 and frb[13:63] > 0 then goto snan operand disabled exponent underflow: sign frb 0 if frb[1:11] = 0 then do exp :1022 frac 0:52 0b0 || frb[12:63] if frb[1:11] > 0 then do exp frb[1:11] : 1023 fr 0b1 || frb[12:63] denormalize operand: g || r || x 0b000 do while exp < :126 exp exp + 1 frac 0:52 || g || r || x 0b0 || frac 0:52 || g || (r | x) fpscr[ux] (frac 24:52 || g || r || x) > 0 round single(sign,exp , frac 0:52 ,g,r,x) fpscr[xx] fpscr[xx] | fpscr[fi] if frac 0:52 = 0 then do frd 0 sign frd 1:63 0 if sign = 0 then fpscr[fprf] ?+zero? if sign = 1 then fpscr[fprf] ?:zero? if frac 0:52 > 0 then do if frac 0 = 1 then do if sign = 0 then fpscr[fprf] ?+normal number? if sign = 1 then fpscr[fprf] ?:normal number? if frac 0 = 0 then do if sign = 0 then fpscr[fprf] book e user 0 5 6 1011 1516 2021 3031 111111 fr d /// fr b 0000001100rc instruction set RM0004 691/1176 ?+denormalized number? if sign = 1 then fpscr[fprf] ?:denormalized number? normalize operand: do while frac 0 = 0 exp exp:1 frac 0:52 frac 1:52 || 0b0 frd 0 sign frd[1-11] exp + 1023 frd[12-63] frac 1:52 done enabled exponent underflow: fpscr[ux] 1 sign frb 0 if frb[1:11] = 0 then do exp :1022 frac 0:52 0b0 || frb[12:63] if frb[1:11] > 0 then do exp frb[1:11] : 1023 frac 0:52 0b1 || frb[12:63] normalize operand: do while frac 0 = 0 exp exp : 1 frac 0:52 frac 1:52 || 0b0 round single(sign,exp,frac 0:52 ,0,0,0) fpscr[xx] fpscr[xx] | fpscr[fi] exp exp + 192 frd 0 sign frd[1-11] exp + 1023 frd[12-63] frac 1:52 if sign = 0 then fpscr[fprf] ?+normal number? if sign = 1 then fpscr[fprf] ?:normal number? done disabled exponent overflow fpscr[ox] 1 if fpscr[rn] = 0b00 then do /* round to nearest */ if frb 0 = 0 then frd 0x7ff0_0000_0000_0000 if frb 0 = 1 then frd 0xfff0_0000_0000_0000 if frb 0 = 0 then fpscr[fprf] ?+infinity? if frb 0 = 1 then fpscr[fprf] ?:infinity? if fpscr[rn] = 0b01 then do /* round toward zero */ if frb 0 = 0 then frd 0x47ef_ffff_e000_0000 if frb 0 = 1 then frd 0xc7ef_ffff_e000_0000 if frb 0 = 0 then fpscr[fprf] ?+normal number? if frb 0 = 1 then fpscr[fprf] ?:normal RM0004 instruction set 692/1176 number? if fpscr[rn] = 0b10 then do /* round toward +infinity */ if frb 0 = 0 then frd 0x7ff0_0000_0000_0000 if frb 0 = 1 then frd 0xc7ef_ffff_e000_0000 if frb 0 = 0 then fpscr[fprf] ?+infinity? if frb 0 = 1 then fpscr[fprf] ?:normal number? if fpscr[rn] = 0b11 then do /* round toward :infinity */ if frb 0 = 0 then frd 0x47ef_ffff_e000_0000 if frb 0 = 1 then frd 0xfff0_0000_0000_0000 if frb 0 = 0 then fpscr[fprf] ?+normal number? if frb 0 = 1 then fpscr[fprf] ?:infinity? fpscr[fr] undefined fpscr[fi] 1 fpscr[xx] 1 done enabled exponent overflow: sign frb 0 exp frb[1:11] : 1023 frac 0:52 0b1 || frb[12:63] round single(sign,exp,frac 0:52 ,0,0,0) fpscr[xx] fpscr[xx] | fpscr[fi] enabled overflow: fpscr[ox] 1 exp exp : 192 frd 0 sign frd[1-11] exp + 1023 frd[12-63] frac 1:52 if sign = 0 then fpscr[fprf] ?+normal number? if sign = 1 then fpscr[fprf] ?:normal number? done zero operand: frd frb if frb 0 = 0 then fpscr[fprf] ?+zero? if frb 0 = 1 then fpscr[fprf] ?:zero? fpscr[fr,fi] 0b00 done infinity operand: frd frb if frb 0 = 0 then fpscr[fprf] ?+infinity? if frb 0 = 1 then fpscr[fprf] ?:infinity? fpscr[fr,fi] 0b00 done qnan operand: frd frb 0:34 || 29 0 instruction set RM0004 693/1176 fpscr[fprf] ?qnan? fpscr[fr,fi] 0b00 done snan operand: fpscr[vxsnan] 1 if fpscr[ve] = 0 then do frd[0:11] frb[0:11] frd 12 1 frd[13:63] frb[13:34] || 29 0 fpscr[fprf] ?qnan? fpscr[fr,fi] 0b00 done normal operand: sign frb 0 exp frb[1:11] : 1023 frac 0:52 0b1 || frb[12:63] round single(sign,exp,frac 0:52 ,0,0,0) fpscr[xx] fpscr[xx] | fpscr[fi] if exp > 127 and fpscr[oe] = 0 then go to disabled exponent overflow if exp > 127 and fpscr[oe] = 1 then go to enabled overflow frd 0 sign frd[1-11] exp + 1023 frd[12-63] frac 1:52 if sign = 0 then fpscr[fprf] ?+normal number? if sign = 1 then fpscr[fprf] ?:normal number? done round single(sign,exp,frac 0:52 ,g,r,x): inc 0 lsb frac 23 gbit frac 24 rbit frac 25 xbit (frac 26:52 ||g||r||x) 0 if fpscr[rn] = 0b00 then do /* comparison ignores u bits */ if sign || lsb || gbit || rbit || xbit = 0bu11uu then inc 1 if sign || lsb || gbit || rbit || xbit = 0bu011u then inc 1 if sign || lsb || gbit || rbit || xbit = 0bu01u1 then inc 1 if fpscr[rn] = 0b10 then do /* comparison ignores u bits */ if sign || lsb || gbit || rbit || xbit = 0b0u1uu then inc 1 if sign || lsb || gbit || rbit || xbit = 0b0uu1u then inc 1 if sign || lsb || gbit || rbit || xbit = 0b0uuu1 then inc 1 if fpscr[rn] = 0b11 then do /* comparison ignores u bits */ RM0004 instruction set 694/1176 if sign || lsb || gbit || rbit || xbit = 0b1u1uu then inc 1 if sign || lsb || gbit || rbit || xbit = 0b1uu1u then inc 1 if sign || lsb || gbit || rbit || xbit = 0b1uuu1 then inc 1 frac 0:23 frac 0:23 + inc if carry_out = 1 then do frac 0:23 0b1 || frac 0:22 exp exp + 1 frac 24:52 29 0 fpscr[fr] inc fpscr[fi] gbit | rbit | xbit return the floating-point operand in fr b is rounded to single-precision, using the rounding mode specified by fpscr[rn], and placed into fr d. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. if msr[fp]=0, an attempt to execute frsp [ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan cr1 fx || fex || vx || ox (if rc=1) instruction set RM0004 695/1176 frsqrte frsqrte floating reciprocal square root estimate frsqrte fr d ,fr b(rc=0) frsqrte. fr d ,fr b(rc=1) frd fpreciprocalsquarerootestimate( frb ) a double-precision estimate of the reciprocal of the square root of the floating-point operand in fr b is placed into fr d. the estimate is correct to a precision of one part in 32 of the reciprocal of the square root of ( fr b), that is, here, x is the initial value in fr b. note that the value placed into fr d may vary between implementations, and between different executions on the same implementation. operation with various special values of the operand is summarized in ta b l e 2 0 5 . fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1 and zero divide exceptions when fpscr[ze]=1. if msr[fp]=0, attempting to execute frsqrte [ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr (undefined) fi (undefined) fx zx vxsnan vxsqrt cr1 fx || fex || vx || ox (if rc=1) book e user 0 5 6 1011 1516 2021 2526 3031 111111 fr d /// fr b /// 11010rc table 205. operations with special values operand result exception ? qnan (no result if fpscr[ve] = 1.) vxsqrt < 0 qnan (no result if fpscr[ve] = 1.) vxsqrt ?0 ? (no result if fpscr[ze] = 1.) zx +0 + (no result if fpscr[ze] = 1.) zx + +0 none snan qnan (no result if fpscr[ve] = 1.) vxsnan qnan qnan none estimate - 1 x ------ - ?? ?? 1 x ------ - ----------------------------------------- 1 32 ------ RM0004 instruction set 696/1176 fsel fsel floating select fsel fr d ,fr a ,fr c ,fr b(rc=0) fsel. fr d ,fr a ,fr c ,fr b(rc=1) if fra 0.0 then frd frc else frd frb the floating-point operand in fr a is compared to the value zero. if the operand is greater than or equal to zero, fr d is set to the contents of fr c. if the operand is less than zero or is a nan, fr d is set to the contents of fr b. the comparison ignores the sign of zero (that is, +0 and ?0 are regarded as equal). if msr[fp]=0, an attempt to execute fsel [ . ] causes a floating-point unavailable interrupt. other registers altered: cr1 fx || fex || vx || ox (if rc=1) note: programming: examples of uses of this instruction can be found in the appendix warning: care must be taken in us ing fsel if ieee compatibility is required, or if the values being tested can be nans or infinities book e user 0 5 6 1011 1516 2021 2526 3031 111111 fr d fr a fr b fr c 10111rc instruction set RM0004 697/1176 fsqrt fsqrt floating square root [single] fsqrt fr d ,fr b(p=1, rc=0) fsqrt. fr d ,fr b(p=1, rc=1) fsqrts fr d ,fr b(p=0, rc=0) fsqrts. fr d ,fr b(p=0, rc=1) if p=1 then frd fpsquarerootdouble( frb ) else frd fpsquarerootsingle( frb ) the square root of the floating-point operand in fr b is placed into fr d. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn], and placed into fr d. operation with various special values of the operand is summarized in ta b l e 2 0 6 . fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. if msr[fp]=0, an attempt to execute fsqrt [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx xx vxsnan vxsqrt cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d /// fr b /// 10110rc table 206. operations with special values operand result exception ? qnan (no result if fpscr[ve] = 1) vxsqrt < 0 qnan (no result if fpscr[ve] = 1) vxsqrt ?0 ?0 none + + none snan qnan(no result if fpscr[ve] = 1)\ vxsnan qnan qnan none RM0004 instruction set 698/1176 fsub fsub floating subtract [single] fsub fr d ,fr a ,fr b(p=1, rc=0) fsub. fr d ,fr a ,fr b(p=1, rc=1) fsubs fr d ,fr a ,fr b(p=0, rc=0) fsubs. fr d ,fr a ,fr b(p=0, rc=1) if p=1 then frd fra - dp frb else frd fra - sp frb the floating-point operand in fr b is subtracted from the floating-point operand in fr a. if the msb of the resultant significand is not 1, the result is normalized. the result is rounded to the target precision under control of the fl oating-point rounding control field, fpscr[rn]. and placed into fr d. the execution of the floating subtract instruction is identical to that of floating add, except that the contents of fr b participate in the operation with the sign bit (bit 0) inverted. fpscr[fprf] is set to the class and sign of the result, except for invalid operation exceptions when fpscr[ve]=1. if msr[fp]=0, an attempt to execute fsub [ s ][ . ] causes a floating-point unavailable interrupt. other registers altered: fprf fr fi fx ox ux xx vxsnan vxisi cr1 fx || fex || vx || ox (if rc=1) book e user 0 23456 1011 1516 2021 2526 3031 111p11 fr d fr a fr b /// 10100rc instruction set RM0004 699/1176 icbi icbi instruction cache block invalidate icbi r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 invalidateinstructioncacheblock( ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 if the block containing the byte addressed by ea is in memory that is memory-coherence required and a block containing the byte addressed by ea is in the instruction cache of any processors, the block is invalidated in those instruction caches, so that subsequent references cause the block to be fetched from main memory. if the block containing the byte addressed by ea is in memory that is not memory-coherence required and a block containing the byte addressed by ea is in the instruction cache of this processor, the block is invalidated in that instruction cache, so that subsequent references cause the block to be fetched from main memory. the function of this instruction is independent of whether the block containing the byte addressed by ea is in memory that is write-through required or caching-inhibited. this instruction is treated as a load. icbi may cause a cache-locking exception on some implementations. see the implementation documentation. on some implementations, hi d1[abe] must be set to allo w management of external l2 caches (for implementations with l2 caches) as well as other l1 caches in the system. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 /// r a r b 1111010110 / RM0004 instruction set 700/1176 icblc icblc instruction cache block lock clear icblc ct, r a, r b form: x if r a = 0 then a 64 0 else a gpr( r a) if mode32 then ea 32 0 || (a + gpr( r b)) 32:63 if mode64 then ea a + gpr( r b) instructioncacheblockclearlock(ct, ea) ea calculation: ea for r a=0ea for r a 0 32 0 || gpr(rb) 32:63 32 0 || (gpr(ra)+gpr(rb)) 32:63 the instruction cache specified by ct has the cache line corresponding to ea unlocked allowing the line to participate in the normal replacement policy. cache lock clear instructions remove locks pr eviously set by cache lock set instructions. user-level cache instructions on page 180 , lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. the icbtlc instruction requires read (r) or execute (x) permissions with respect to translation and memory protection and can cause dsi and dtlb error interrupts accordingly. an unable-to-unlock condition is said to oc cur any of the following conditions exist: the target address is marked cache-inhibited, or the storage attributes of the address uses a coherency protocol th at does not support locking. the target cache is disabled or not present. the ct field of the instructions contains a value not supported by the implementation. the target address is not in the cache or is present in the cache but is not locked. if an unable-to-unlock condition occurs, no cache operation is performed. eis specifics setting l1csr1[iclfi] a llows system software to clear all l1 instruction cache locking bits without knowing the addresses of the lines locked. cache locking apu user 0 56 101115162021 3031 011111 ct r a r b 0 01110011 0 / instruction set RM0004 701/1176 icbt icbt instruction cache block touch icbt ct ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 prefetchinstructioncacheblock( ct, ea ) ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 this instruction is a hint that performance would likely be improved if the block containing the byte addressed by ea is fetched into t he instruction cache, bec ause the program will probably soon execute code from the addressed location. user-level cache instructions on page 180 ,? lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. implementations should perform no operation when ct specifies a value not supported by the implementation. the hint is ignored if the block is caching-inhibited. this instruction treated as a load (see the discussion of cache and mmu operation in the user?s manual), except that an interrupt is not taken for a translation or protection violation. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 ct r a r b 0000010110 / RM0004 instruction set 702/1176 icbtls icbtls instruction cache block touch and lock set icbtls ct, r a, r b form: x if r a = 0 then a 64 0 else a gpr( r a) if mode32 then ea 32 0 || (a + gpr( r b)) 32:63 if mode64 then ea a + gpr( r b) prefetchinstructioncacheblocklockset(ct, ea) ea calculation: ea for r a=0ea for r a 0 32 0 || gpr(rb) 32:63 32 0 || (gpr(ra)+gpr(rb)) 32:63 the instruction cache specified by ct has the line corresponding to ea loaded and locked. if the line exists in the cache, it is locked without refetching from memory. cache touch and lock set instructions allow software to lock lines into the cache to shorten latency for critical cache accesses and more deterministic behavior. lines locked in the cache do not participate in the normal replacement policy when a line must be victimized for replacement. user-level cache instructions on page 180 ,? lists supported ct values. an implementation may use other ct values to enable software to target specific, implementation-dependent portions of its cache hierarchy or structure. the icbtls requires read (r) or execute (x) pe rmissions for translation and memory protection and can cause dsi and dtlb error interrupts accordingly. for unable-to-lock conditions, described in unable-to-lock conditions on page 849 ,? no cache operation is performed and licsr0[icul] is set. an overlocking condition is said to exist is all the available ways for a given cache index are already locked. if an overlocking condition occurs for a icbtls instruction and if the lock was targeted for the primary cache or secondary cache (ct = 0 or ct = 2), the requested line is not locked into the cache. when an over lock condition occu rs, l1csr1[iclo] (l2csr[l2clo] for ct = 2) is set. if l1csr1[icloa] is set (or l2csr[l2cloa] for ct = 2), the requested line is locked into the cache and implementation dependent line currently locked in the cache is evicted. results of overlocking and unable-to-lock conditions for caches other than the primary and secondary cache are defined as part of the architecture for the cache hierarchy designated by ct. if a unified primary cache is implemented and l1csr1 is not implemented, l1csr0[dcul] and l1csr0[dclo] are updated instead of the corresponding l1csr1 bits. other registers altered: l1csr1[icul] if unable to lock occurs l1csri[iclo] (l2csr[l2clo]) if lock overflow occurs cache locking apu user 0 56 101115162021 3031 011111 ct r a r b 0 11110011 0 / instruction set RM0004 703/1176 _ illegal _illegal illegal se_illegal srr1 msr srr0 cia nia ivpr 32:47 || ivor6 48:59 || 0b0000 msr we,ee,pr,is,ds,fp,fe0,fe1 0b0000_0000 se_illegal is used to request an illegal instruct ion exception. a program interrupt is generated. the contents of the msr are copied into srr1 and the address of the se_illegal instruction is placed into srr0. msr[we,ee,pr,is,ds,fp,fe0,fe1] are cleared. the interrupt causes the next instruction to be fetched from address ivpr[32? 47]||ivor6[48?59]||0b0000 this instruction is context synchronizing. special registers altered: srr0 sr r1 msr[we,ee,pr,is,ds,fp,fe0,fe1] 015 0000000000000000 vle user RM0004 instruction set 704/1176 isel isel integer select isel r d, r a, r b, cr b if ( r a = 0) then a 64 0 else a gpr( r a) c cr cr b + 32 if c then r d a else r d gpr( r b) if cr[ cr b + 32] is set, the contents of r a|0 are copied into r d. if cr[ cr b + 32] is clear, the contents of r b are copied into r d. integer select apu user 0 56 10111516202125263031 011111 r d r a r b cr b 011110 instruction set RM0004 705/1176 isync isync instruction synchronize isync isync provides an ordering function for the effects of all instructions executed by the processor executing the isync instruction. executing an isync ensures that all instructions preceding the isync have completed before isync completes, and that no subsequent instructions are initiated until after isync completes. it also causes any prefetched instructions to be discarded, with the effect that subsequent instructions are fetched and executed in the context established by the instructions preceding isync . isync may complete before memory accesses associated with instructions preceding isync have been performed. isync is context synchronizing. see context synchronization on page 144 .? other registers altered: none book e user 0 5 6 2021 3031 010011 /// 0010010110 / RM0004 instruction set 706/1176 _ isync _isync instruction synchronize se_isync the se_isync instruction provides an ordering function for the effects of all instructions executed by the processor executing the se_isync instruction. executing an se_isync instruction ensures that all instructions preceding the se_isync instruction have completed before the se_isync instruction completes, and that no subsequent instructions are initiated until after the se_isync instruction completes. it also causes any prefetched instructions to be discarded, with the effect that subsequent instructions are fetched and executed in the context established by the instructions preceding the se_isync instruction. the se_isync instruction may complete before memory accesses associated with instructions preceding the se_isync instruction have been performed. this instruction is context synchronizing (see book e). it has identical semantics to book e isync , just a different encoding. special registers altered: none 015 0000000000000001 vle user instruction set RM0004 707/1176 lbz lbz load byte and zero [with update] [indexed] lbz r d , d (r a ) (d-mode, u=0) lbzu r d , d (r a ) (d-mode, u=1) lbzx r d ,r a ,r b (x-mode, u=0) lbzux r d ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 rd 56 0 || mem(ea,1) if u=1 then ra ea the ea is calculated as follows: for lbz and lbzu, ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for lbzx and lbzux , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the byte in memory addressed by ea is loaded into r d[56?63]; r d[0?55] are cleared. if u=1 (with update), ea is placed into r a. if u=1 (with update), and r a=0 or r a= r d, the instruction form is invalid. other registers altered: none book e user 05610111516 31 10001u r d r ad 0 5 6 1011 1516 2021 242526 3031 011111 r d r a r b 0001u10111 / RM0004 instruction set 708/1176 _ lbz x _lbz x load byte and zero [with update] [indexed] e_lbz r d , d (r a ) (d-mode) se_lbz r z , sd4 (r x ) (sd4-mode) e_lbzu r d , d8 (r a ) (d8-mode) if (ra=0 & !se_lbz) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 28 0 || sd4)) 32:63 gpr(rd or rz) 24 0 || mem(ea,1) if e_lbzu then gpr(ra) ea let the ea be calculated as follows: for e_lbz and e_lbzu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_lbz , let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field. the byte in memory addressed by ea is loaded into bits 56?63 of gpr( r d or r z). bits 32?55 of gpr( r d or r z) are cleared. if e_lbzu , ea is placed into gpr( r a). if e_lbzu and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 31 001100 rd ra d 03478111215 1 0 0 0 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rd ra 00000000 d8 instruction set RM0004 709/1176 lfd lfd load floating-point double lfd fr d , d (r a ) (d-mode, u=0) lfdu fr d , d (r a ) (d-mode, u=1) lfdx fr d ,r a ,r b (x-mode, u=0) lfdux fr d ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 frd mem(ea,8) if u=1 then ra ea the ea is calculated as follows: for lfd and lfdu , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for lfdx and lfdux , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the double word addressed by ea is placed into fr d. if u=1 (with update), ea is placed into register r a. if u=1 (with update) and r a=0, the instruction form is invalid. if msr[fp]=0, an attempt to execute lfd [ u ][ x ] causes a floating-point unavailable interrupt. other registers altered: none book e user 05610111516 31 11001u fr d r ad 0 5 6 1011 1516 2021 242526 3031 011111 fr d r a r b 1001u10111 / RM0004 instruction set 710/1176 lfs lfs load floating-point single lfs fr d , d (r a ) (d-mode, u=0) lfsu fr d , d (r a ) (d-mode, u=1) lfsx fr d ,r a ,r b (x-mode, u=0) lfsux fr d ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 frd double(mem(ea,4)) if u=1 then ra ea the ea is calculated as follows: for lfs and lfsu , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for lfsx and lfsux , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the word addressed by ea is interpreted as a single-precision operand, converted to floating-point double format, and placed into fr d. if u=1 (with update), ea is placed into register r a. if u=1 (with update) and r a=0, the instruction form is invalid. if msr[fp]=0, an attempt to execute lfs [ u ][ x ] causes a floating-point unavailable interrupt. other registers altered: none book e user 0 4 5 6 10 11 15 16 31 11000u fr d r ad 0 5 6 1011 1516 2021 242526 3031 011111 fr d r a r b 1000u10111 / instruction set RM0004 711/1176 lha lha load half word algebraic [with update] [indexed] lha r d , d (r a ) (d-mode, u=0) lhau r d , d (r a ) (d-mode, u=1) lhax r d ,r a ,r b (x-mode, u=0) lhaux r d ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 rd 32 0 || exts(mem(ea,2)) 32:63 if u=1 then ra ea the ea is calculated as follows: for lha and lhau , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for lhax and lhaux , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the half word addressed by ea is loaded into r d[48?63]. r d[32?47] are filled with a copy of bit 0 of the loaded half word. bits r d[0?31] are cleared. if u=1 (with update), ea is placed into r a. if u=1 (with update), and r a=0 or r a= r d, the instruction form is invalid. other registers altered: none book e user 0 4 5 6 10 11 15 16 31 10101u r d r ad 0 5 6 1011 1516 2021 242526 3031 011111 r d r a r b 0101u10111 / RM0004 instruction set 712/1176 _ lha x _lha x load halfword algebraic [with update] [indexed] e_lha r d , d (r a ) (d-mode) e_lhau r d , d8 (r a ) (d8-mode) if ra=0 then a 32 0 else a gpr(ra) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 gpr(rd) exts(mem(ea,2)) 32:63 if e_lhau then gpr(ra) ea let the ea be calculated as follows: for e_lha and e_lhau , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. the half word in memory addressed by ea is loaded into bits 48?63 of gpr( r d). bits 32?47 of gpr( r d) are filled with a copy of bi t 0 of the loaded half word. if e_lhau , ea is placed into gpr( r a). if e_lhau and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 31 001110 rd ra d 0 5 6 1011 1516 2324 31 000110 rd ra 00000011 d8 instruction set RM0004 713/1176 lhbrx lhbrx load half word byte-reverse indexed lhbrx r d ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 data 0:15 mem(ea,2) rd 48 0 || data 8:15 || data 0:7 the ea is calculated as follows: for lhbrx , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. bits 0?7 of the half word addressed by ea are loaded into r d[56?63]. bits 8?15 of the half word addressed by ea are loaded into r d[48?55]; r d[0?47] are cleared. other registers altered: none programming notes: when ea references big-endian memory, these instructions have the effect of loading data in little-endian byte order. likewise, when ea references little-endian memory, these instructions have the effect of loading data in big-endian byte order. in some implementations, the load half word byte-reverse indexed instructions may have greater latency than other load instructions. book e user 0 5 6 1011 1516 2021 3031 011111 r d r a r b 1100010110 / RM0004 instruction set 714/1176 lhz lhz load half word and zero [with update] [indexed] lhz r d , d (r a ) (d-mode, u=0) lhzu r d , d (r a ) (d-mode, u=1) lhzx r d ,r a ,r b (x-mode, u=0) lhzux r d ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 rd 48 0 || mem(ea,2) if u=1 then r a ea the ea is calculated as follows: for lhz and lhzu , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for lhzx and lhzux , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the half word addressed by ea is loaded into r d[48?63]; r d[0?47] are cleared. if u=1 (with update), ea is placed into r a. if u=1 (with update), and r a=0 or r a= r d, the instruction form is invalid. other registers altered: none book e user 0 4 5 6 10 11 15 16 31 10100u r d r ad 0 5 6 1011 1516 2021 242526 3031 011111 r d r a r b 0100u10111 / instruction set RM0004 715/1176 _ lhz x _lhz x load halfword and zero [with update] [indexed] e_lhz r d , d (r a ) (d-mode) se_lhz r z , sd4 (r x ) (sd4-mode) e_lhzu r d , d8 (r a ) (d8-mode) if (ra=0 & !se_lhz) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 27 0 || sd4 || 0)) 32:63 gpr(rd or rz) 16 0 || mem(ea,2) if e_lhzu then gpr(ra) ea let the ea be calculated as follows: for e_lhz and e_lhzu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_lhz let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 1 bit. the half word in memory addressed by ea is loaded into bits 48?63 of gpr( r d). bits 32?47 of gpr( r d) are cleared. if e_lhzu , ea is placed into gpr( r a). if e_lhzu and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 31 010110 rd ra d 03478111215 1 0 1 0 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rd ra 00000001 d8 RM0004 instruction set 716/1176 _ li x _li x load immediate [shifted] e_li r d , li20 (li20-mode) li20 li20 0:3 || li20 4:8 || li20 9:19 gpr(rd) exts(li20) for e_li , the sign-extended li20 field is placed into gpr( r d). special registers altered: none e_lis r d , ui ui ui 0:4 || ui 5:15 gpr(rd) ui || 16 0 for e_lis , the ui field is concatenated on the right with 16 0?s and placed into gpr( r d). special registers altered: none se_li r x , ui7 gpr(rx) 25 0 || ui7 for se_li , the zero-extended ui7 field is placed into gpr( r x). special registers altered: none vle user 0 5 6 1011 151617 2021 31 011100 rd li20 4:8 0 li20 0:3 li20 9:19 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11100 ui 5:15 045 111215 01001 ui7 rx instruction set RM0004 717/1176 lmw lmw load multiple word lmw r d , d (r a ) if ra=0 then ea 32 0 || exts(d) 32:63 else ea 32 0 || (ra+exts(d)) 32:63 r rd do while r 31 gpr(r) 32 0 || mem(ea,4) r r + 1 ea 32 0 || (ea+4) 32:63 the ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign- extended value of the d instruction field. here n=(32? r d). n consecutive words starting at ea are loaded into bits 32?63 of registers r d through gpr31. bits 0?31 of these gprs are cleared. ea must be a multiple of 4. if it is not, either an alignment interrupt is invoked or the results are boundedly undefined. if r a is in the range of registers to be loaded, including the case in which r a=0, the instruction form is invalid. other registers altered: none book e user 05610111516 31 101110 r d r ad RM0004 instruction set 718/1176 _ lmw _lmw load multiple word e_lmw r d , d8 (r a ) if ra=0 then ea exts(d8) 32:63 else ea (gpr(ra)+exts(d8)) 32:63 r rd do while r 31 gpr(r) mem(ea,4) r r + 1 ea (ea+4) 32:63 let the ea be the sum of the contents of gpr( r a), or 32 0s if r a = 0, and the sign-extended value of the d8 instruction field. let n = (32-rd). n consecutive words starting at ea are loaded into bits 32?63 of registers gpr( r d) through gpr(31). ea must be a multiple of 4. if it is not, either an alignment interrupt is invoked or the results are boundedly undefined. if r a is in the range of registers to be loaded, including the case in which r a = 0, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 2324 31 000110 rd ra 0 0 0 0 1 0 0 0 d8 instruction set RM0004 719/1176 lswi lswi load string word (immediate | indexed) lswi r d ,r a , nb lswx r d ,r a ,r b if ra=0 then a 64 0 else a ra if ?lswi? then ea 32 0 || a 32:63 if ?lswx? then ea 32 0 || (a + rb) 32:63 if ?lswi? & nb=0 then n 32 if ?lswi? & nb 0 then n nb if ?lswx? then n xer 57:63 r rd : 1 i 32 rd undefined do while n > 0 if i = 32 then r r + 1 (mod 32) gpr(r) 0 gpr(r) i:i+7 mem(ea,1) i i + 8 if i = 64 then i 32 ea 32 0 || (ea+1) 32:63 n n : 1 the ea is calculated as follows: for lswi , ea is 32 zeros concatenated with r a[32?63], or 32 zeros if r a=0. for lwsx , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. if lswi , n = nb if nb 0, n = 32 if nb=0. if lswx , n=xer[57?63]. n is the number of bytes to load. here nr=ceil(n 4): nr is the number of registers to receive data. if n>0, n consecutive bytes starting at ea are loaded into registers r d through ( r d+nr?1). data is loaded into the low-order 4 bytes of each gpr; the high-order 4 bytes are cleared. bytes are loaded left to right in each gpr. the sequence wraps to gpr0 if required. if the 4 lsbs of gpr( r d+nr?1) are partially fill ed, the unfilled lsbs of that gpr are cleared. if lswx and n=0, the contents of r d are undefined. if r a, or r b for lswx , is in the range of registers to be loaded, including where r a=0, an illegal instruction type program interrupt is invoked or results are boundedly undefined. if r d= r a, or r d= r b for lswx , the instruction form is invalid. other registers altered: none note: programming: string instructions move data without concern for alignment. they can perform short moves between arbitrary locations or long moves between misaligned memory fields. book e user 0 5 6 1011 1516 2021 3031 011111 r d r a nb 1001010101 / 0 5 6 1011 1516 2021 3031 011111 r d r a r b 1000010101 / RM0004 instruction set 720/1176 lwarx lwarx load word and reserve indexed lwarx r d ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 reserve 1 reserve_addr real_addr(ea) rd 32 0 || mem(ea,4) ea is bits 32?63 of the sum of the contents of r a (32 zeros if r a=0), and the contents of r b. the word addressed by ea is loaded into r d[32?63]; r d[0?31] are cleared. lwarx creates a reservation for use by a stwcx. instruction. an address computed from the ea is associated with the reservation and replaces any previously associated address. see atomic update primitives using lwarx and stwcx. on page 176 .? if ea is not a multiple of 4, an alignment interrupt occurs or results are boundedly undefined. other registers altered: none programming notes: lwarx , and stwcx. permit programmers to write an instruction sequence that appears to perform an atomic update operation on a memory location. this operation depends on a single reservation resource in each processor. at most one reservation exists on any given processor. because lwarx instructions have implementation dependencies (such as the granularity at which reservations are managed), they must be used with care. system library programs should use these instructions to implement high-level synchronization functions (such as test and set, compare and swap) needed by application programs. application programs should use these library programs, rather than use lwarx directly the granularity with which reservations are managed is implementation-dependent. therefore the location to be accessed by lwarx should be allocated by a system library program. see atomic update primitives using lwarx and stwcx. on page 176 .? book e user 0 5 6 1011 1516 2021 3031 011111 r d r a r b 0000010100 / instruction set RM0004 721/1176 lwbrx lwbrx load word byte-reverse indexed lwbrx r d ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 data 0:31 mem(ea,4) rd 32 0 || data 24:31 || data 16:23 || data 8:15 || data 0:7 the ea is calculated as follows: for lwbrx , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. bits 0?7 of the word addressed by ea are loaded into r d[56?63]. bits 8?15 of the word addressed by ea are loaded into r d[48?55]. bits 16?23 of the word addressed by ea are loaded into r d[40?47]. bits 24?31 of the word addressed by ea are loaded into r d[32?39]. bits r d[0?31] are cleared. other registers altered: none programming notes: when ea references big-endian memory, these instructions have the effect of loading data in little-endian byte order. likewise, when ea references little-endian memory, these instructions have the effect of loading data in big-endian byte order. in some implementations, the load word byte-reverse instructions may have greater latency than other load instructions. book e user 0 5 6 1011 1516 2021 3031 011111 r d r a r b 1000010110 / RM0004 instruction set 722/1176 lwz lwz load word and zero [with update] [indexed] lwz r d , d (r a ) (d-mode, u=0) lwzu r d , d (r a ) (d-mode, u=1) lwzx r d ,r a ,r b (x-mode, u=0) lwzux r d ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 rd 32 0 || mem(ea,4) if u=1 then ra ea the ea is calculated as follows: for lwz and lwzu , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for lwzx and lwzux , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the word addressed by the ea is loaded into r d[32?63]; r d[0?31] are cleared. if u=1 (with update), ea is placed into r a. if u=1 (with update), and r a=0 or r a= r d, the instruction form is invalid. other registers altered: none book e user 05610111516 31 10000u r d r ad 0 5 6 1011 1516 2021 242526 3031 011111 r d r a r b 0000u10111 / instruction set RM0004 723/1176 _ lwz _lwz load word and zero [with update] [indexed] e_lwz r d , d (r a ) (d-mode) se_lwz r z , sd4 (r x ) (sd4-mode) e_lwzu r d , d8 (r a ) (d8-mode) if (ra=0 & !se_lwz) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 26 0 || sd4 || 2 0)) 32:63 gpr(rd or rz) mem(ea,4) if e_lwzu then gpr(ra) ea let the ea be calculated as follows: for e_lwz and e_lwzu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_lwz let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 2 bits. the word in memory addressed by the ea is loaded into bits 32?63 of gpr( r d). if e_lwzu , ea is placed into gpr( r a). if e_lwzu and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 31 010100 rd ra d 03478111215 1 1 0 0 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rd ra 00000010 d8 RM0004 instruction set 724/1176 mbar mbar memory barrier mbar mo when mo=0, mbar provides a memory ordering function for all memory access instructions executed by the processor executing the mbar instruction. executing an mbar instruction ensures that all data me mory accesses caused by instructions preceding the mbar have completed before any data me mory accesses caused by an y instructions after the mbar . this order is seen by all mechanisms. when mbar (mo = 1), as defined by the eis, mbar functions like eieio as it is defined by the classic powerpc architecture. it provides ordering for the effects of load and store instructions. these instructions consist of two sets, which are ordered separately. memory accesses caused by a dcbz or a dcba are ordered like a store. the two sets follow: caching-inhibited, guarded loads and stores to memory and write-through-required stores to memory. mbar (mo=1) controls the order in which accesses are performed in main memory. it ensures that all applicable memory accesses caused by instructions preceding the mbar have completed with respect to main memory before any applicable memory accesses ca used by instructions following mbar access main memory. it acts like a barrier that flows through the memory queues and to main memory, preventing the reordering of memory accesses across the barrier. no ordering is performed for dcbz if the instruction causes the system alignment error handler to be invoked. all accesses in this set are ordered as one set; there is not one order for guarded, caching-inhibited loads and stores and another for write-through-required stores. stores to memory that are caching-allowed, write-through not required, and memory- coherency required. mbar (mo=1) controls the order in which accesses are performed with respect to coherent memory. it ensures that, with respect to coherent memory, applicable stores caused by instructions before the mbar complete before any applicable stores caused by instructions after it. except for dcbz and dcba , mbar (mo=1) does not affect the order of cache operations (whether caused explicitly by a cache managem ent instruction or imp licitly by the cache coherency mech anism). also. mbar does not affect the order of accesses in one set with respect to accesses in the other. mbar (mo=1) may complete before memory accesses caused by instructions preceding it have been performed with respect to main memory or coherent memory as appropriate. mbar (mo=1) is intended for use in managing shared data structures, in accessing memory-mapped i/o, and in preventing load/store combining operations in main memory. for the first use, the shared data structure and the lock that protects it must be altered only by stores that are in the same set (for both cases described above). for the second use, mbar (mo=1) can be thought of as placing a barrier into the stream of memory accesses issued by a core, such that any given memory access appears to be on the same side of the barrier to both the core and the i/o device. because the core performs store operations in order to memory that is designated as both caching-inhibited and guarded, mbar (mo=1) is needed for such memory only when loads must be ordered with respect to stores or with respect to other loads. book e user 056101120213031 011111 mo / / / 1101010110 / instruction set RM0004 725/1176 note that mbar (mo=1) does not connect hardware considerations to it such as multiprocessor implementations that send an mbar (mo=1) address-only broadcast (useful in some designs). for example, if a design has an external buffer that re-orders loads and stores for better bus efficiency, mbar (mo=1) broadcasts signals to that buffer that previous loads/stores (marked caching-inhibited, guarded, or write-through required) must complete before any following loads/stores (marked caching-inhibited, guarded, or write-through required). if mo is not 0 or 1, an implementation may support the mbar instruction ordering a particular subset of memory accesses. an implementation may also support multiple, non- zero values of mo that each specify a different subset of memory accesses that are ordered by the mbar instruction. which subsets of memory accesses are ordered and which values of mo specify these subsets is implementation-dependent. see the user?s manual for the implementation. on some implementations, hi d1[abe] must be set to allo w management of external l2 caches (for implementations with l2 caches) as well as other l1 caches in the system. other registers altered: none programming note: mbar is provided to implement a pipelined memory barrier. the following sequence shows one use of mbar in supporting shared data, ensuring the action is completed before releasing the lock. p1 p2 lock . . . read & write . . . mbar . . . free lock . . . ... lock . . . read & write ... mbar ... free lock RM0004 instruction set 726/1176 mcrf mcrf move condition register field mcrf cr d ,cr s cr 4xbf+32:4xbf+35 cr 4x cr s+32:4x cr s+35 the contents of field cr s (bits 4 cr s+32?4 cr s+35) of cr are copied to field cr d (bits 4 cr d+32?4 cr d+35) of cr. other registers altered: cr book e user 0 5 6 8 9 1011 1314 2021 3031 010011 cr d// cr s /// 0000000000 / instruction set RM0004 727/1176 _ mcrf _mcrf move cr field e_mcrf cr d , cr s cr 4xcrd+32:4xcrd+35 cr 4xcrs+32:4xcrs+35 the contents of field cr s (bits 4 crs+32 through 4 crs+35) of the cr are copied to field cr d (bits 4 crd+32 through 4 crd+35) of the cr. special registers altered: cr vle user 0 5 6 8 9 1011 1314 2021 3031 011111 crd // crs /// 0000010000 / RM0004 instruction set 728/1176 mcrfs mcrfs move to condition register from fpscr mcrfs cr d ,cr s cr bf 4: cr d 4+3 fpscr cr s 4: cr s 4+3 fpscr cr s 4: cr s 4+3 0b0000 the contents of fpscr[ cr s] are copied to cr field cr d. all exception bits copied are cleared in the fpscr. if the fx bit is copied, it is cleared in the fpscr. if msr[fp]=0, an attempt to execute mcrfs causes a floating-point unavailable interrupt. other registers altered: cr field cr d fx ox(if cr s=0) ux zx xx vxsnan(if cr s=1) vxisi vxidi vxzdz vximz(if cr s=2) vxvc(if cr s=3) vxsoft vxsqrt vxcvi(if cr s=5) book e user 0 5 6 8 9 1011 1314 2021 3031 111111 cr d// cr s /// 0001000000 / instruction set RM0004 729/1176 mcrxr mcrxr move to condition register from integer exception register mcrxr cr d cr 4 cr d+32:4 cr d+35 xer 32:35 xer 32:35 0b0000 the contents of xer[32?35] are copied to cr field cr d. xer[32?35] are cleared. other registers altered: cr xer[32?35] book e user 0 5 6 8 9 2021 3031 011111 cr d /// 1000000000 / RM0004 instruction set 730/1176 mfapidi mfapidi move from apid indirect mfapidi r d ,r a rd implementation-dependent value based on ra the contents of r a are provided to any auxiliary proce ssing extensions that may be present. a value, that is implementation-dependent and extension-dependent, is placed in r d. other registers altered: none programming note: this instruction is provided as a mechanism for software to query the presence and configuration of one or more auxiliary proces sing extensions. see user?s manual for the implementation for details on the behavior of this instruction. book e user 0 5 6 1011 1516 2021 3031 011111 r d r a /// 0100010011 / instruction set RM0004 731/1176 _ mfar _mfar move from alternate register se_mfar r x ,ar y gpr(rx) gpr(ary) for se_mfar , the contents of gpr( ar y) are placed into gpr( r x). ar y specifies a gpr in the range r8?r23. the encoding 0000 specifies r8, 0001 specifies r9,?, 1111 specifies r23. special registers altered: none 05678111215 00000011 ary rx vle user RM0004 instruction set 732/1176 mfcr mfcr move from condition register mfcr r d rd 32 0 || cr the contents of the cr are placed into r d[32?63]. bits r d[0?31] are cleared. other registers altered: none book e user 056101120213031 011111 r d /// 0000010011 / instruction set RM0004 733/1176 _ mfctr _mfctr move from count register se_mfctr r x gpr(rx) ctr the ctr contents are placed into bits 32?63 of gpr( r x). special registers altered: none 056111215 000000 0 0 1 0 1 0 rx vle user RM0004 instruction set 734/1176 mfdcr mfdcr move from device control register mfdcr r d , dcrn rd dcreg(dcrn) dcrn identifies the dcr (see the user?s ma nual for a list of dcrs supported by the implementation). the contents of the designated dcr are placed into r d. for 32-bit dcrs, the contents of the dcr are placed into r d[32?63]. bits r d[0?31] are cleared. execution of this instruction is restricted to supervisor mode. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 r d dcrn 5?9 dcrn 0?4 0101000011 / instruction set RM0004 735/1176 mffs mffs move from fpscr mffs fr d(rc=0) mffs. fr d(rc=1) frd fpscr the contents of the fpscr are placed into fr d[32?63]; fr d[0?31] are undefined. if msr[fp]=0, an attempt to execute mffs [ . ] causes a floating-point unavailable interrupt. other registers altered: cr1 fx || fex || vx || ox (if rc=1) book e user 056101120213031 111111 fr d /// 1001000111rc RM0004 instruction set 736/1176 _ mflr _mflr move from link register se_mflr r x gpr(rx) lr the lr contents are placed into bits 32?63 of gpr( r x). special registers altered: none 056111215 000000 0 0 1 0 0 0 rx vle user instruction set RM0004 737/1176 mfmsr mfmsr move from machine state register mfmsr r d rd 32 0 || msr the contents of the msr are placed into r d[32?63]. bits r d[0?31] are cleared. execution of this instruction is restricted to supervisor mode. other registers altered: none book e user 056101120213031 011111 r d /// 0001010011 / RM0004 instruction set 738/1176 mfpmr mfpmr move from performance monitor register mfpmr r d,pmrn gpr( r d) pmreg(pmrn) pmrn denotes a performance monitor register. section 2.16: performance monitor registers (pmrs) ,? lists supported performance monitor registers. the contents of the designated performanc e monitor register are placed into gpr[ r d]. when msr[pr] = 1, specifying a performance moni tor register that is not implemented and is not privileged (pmrn[5] = 0) results in an illegal instruction ex ception-type program interrupt. when msr[pr] = 1, specifying a performance monitor register that is privileged (pmrn[5] = 1) results in a privileged instruction exception-type program interrupt. when msr[pr] = 0, specifying an unimplemented performance monitor register is boundedly undefined. other registers altered: none book e user 056101115162021 31 011111 r d pmrn 5?9 pmrn 0?4 01010011100 instruction set RM0004 739/1176 mfspr mfspr move from special purpose register mfspr r d , sprn rd spreg(sprn) sprn denotes an spr (see chapter 2.18: book e spr model on page 130 ? ). the contents of the designated spr are placed into r d. for 32-bit sprs, the contents of the spr are placed into r d[32?63]. bits r d[0?31] are cleared. execution of this instruction specifying a defined and privileged spr (sprn[5]=1) when msr[pr]=1 results in a privileged instruction exception-type program interrupt. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 r d sprn[5?9] sprn[0?4] 0101010011 / table 207. effect of sprn[5] and msr[pr] sprn[5] msr[pr] sprn class result 01defined if not implemented, illegal instruction exception if implemented, as defined in book e 0 1 allocated if not implemented, illegal instruction exception if implemented, as defined in user?s manual 0 1 preserved if not implemented, illegal instruction exception if implemented, as defined in powerpc architecture 0 1 reserved illegal instruction exception 1 1 ? privileged exception ?0defined if not implemented, boundedly undefined if implemented, as defined in book e ? 0 allocated if not implemented, boundedly undefined if implemented, as defined in user?s manual ? 0 preserved if not implemented, boundedly undefined if implemented, as defined in powerpc architecture ? 0 reserved boundedly undefined RM0004 instruction set 740/1176 _ mr _mr move register se_mr r x ,r y gpr(rx) gpr(ry) for se_mr , the contents of gpr( r y) are placed into gpr( r x). special registers altered: none 05678111215 00000001 ry rx vle user instruction set RM0004 741/1176 msync msync memory synchronize msync the msync instruction provides an ordering function for the effects of all instructions executed by the processor executing the msync . executing msync ensures that all instructions preceding the msync have completed before msync completes and that no subsequent instructions ar e initiated until after the msync completes. it also creates a memory barrier (see atomic update primitives using lwarx and stwcx. on page 176 ? ), which orders the memory accesses associated with these instructions. the msync may not complete before memory accesses associated with instructions preceding msync have been performed. on some implementations, hi d1[abe] must be set to allo w management of external l2 caches (for implementations with l2 caches) as well as other l1 caches in the system. msync is execution synchronizing. (see execution synchronization on page 145 .? ) other registers altered: none programming notes: msync can be used to ensure that all stores into a data structure, caused by store instructions executed in a critical section of a program, are performed with respect to another processor before the store that releases the lock is performed with respect to that processor. the functions performed by the msync may take a significant amount of time to complete, so indiscriminate use of this instruction may adversely affect performance. the memory barrier ( mbar ) instruction may be more appropriate than msync for many cases. msync replaces the sync instruction; it uses the same opcode as sync such that powerpc applications calling for sync invoke the msync when executed on an book e implementation. the functionality of msync is identical to sync except that msync also does not complete until all prev ious memory accesses complete. mbar is provided in the book e for those occasions when only ordering of memory accesses is required without execution synchronization. book e user 0 5 6 2021 3031 011111 /// 1001010110 / RM0004 instruction set 742/1176 _ mtar _mtar move to alternate register se_mtar ar x ,r y gpr(arx) gpr(ry) for se_mtar , the contents of gpr( r y) are placed into gpr( ar x). ar x specifies a gpr in the range r8?r23. the encoding 0000 specifies r8, 0001 specifies r9,?, 1111 specifies r23. special registers altered: none 05678111215 00000010 ry arx vle user instruction set RM0004 743/1176 mtcrf mtcrf move to condition register fields mtcrf crm ,r s i 0 do while i < 8 if crm i =1 then cr 4 i+32:4 i+35 rs 4 i+32:4 i+35 i i+1 the contents of r s[32?63] are placed into the cr under control of the field mask specified by crm. the field mask identifies the 4-bit fields affected. let i be an integer in the range 0? 7. if crm i = 1, cr field i (cr bits 4 i+32 through 4 i+35) is set to the contents of the corresponding field of r s[32?63]. other registers altered: cr fields selected by mask book e user 0 5 6 101112 192021 3031 011111 r s / crm / 0010010000 / RM0004 instruction set 744/1176 _ mtctr _mtctr move to count register se_mtctr r x ctr gpr(rx) the contents of bits 32?63 of gpr( r x) are placed into the ctr. special registers altered: ctr 056111215 000000 0 0 1 0 1 1 rx vle user instruction set RM0004 745/1176 mtdcr mtdcr move to device control register mtdcr dcrn ,r s dcreg(dcrn) rs dcrn identifies the dcr (see user?s manual for a list of dcrs supported by the implementation). the contents of r s are placed into the desig nated dcr. for 32-bit dcrs, r s[32?63] are placed into the dcr. execution of this instruction is restricted to supervisor mode. other registers altered: see the user?s manual for the implementation book e user 0 5 6 1011 1516 2021 3031 011111 r s dcrn 5?9 dcrn 0?4 0111000011 / RM0004 instruction set 746/1176 mtfsb0 mtfsb0 move to fpscr bit 0 mtfsb0 crb d(rc=0) mtfsb0. crb d(rc=1) fpscr[bt] 0b0 fpscr[bt] is cleared. if msr[fp]=0, an attempt to execute mtfsb0 [ . ] causes a floating-point unavailable interrupt. other registers altered: fpscr[bt] cr1 fx || fex || vx || ox (if rc=1) programming note: bits 1 and 2 (fex and vx) cannot be explicitly reset. book e user 056101120213031 111111 crb d /// 0001000110rc instruction set RM0004 747/1176 mtfsb1 mtfsb1 move to fpscr bit 1 mtfsb1 crb d(rc=0) mtfsb1. crb d(rc=1) fpscr[bt] 0b1 fpscr[bt] is set. if msr[fp]=0, an attempt to execute mtfsb1 [ . ] causes a floating-point unavailable interrupt. other registers altered: fpsclr[bt,fx] cr1 fx || fex || vx || ox (if rc=1) programming note: bits 1 and 2 (fex and vx) cannot be explicitly set. book e user 056101120213031 111111 crb d /// 0000100110rc RM0004 instruction set 748/1176 mtfsf mtfsf move to fpscr fields mtfsf fm ,fr b(rc=0) mtfsf. fm ,fr b(rc=1) i 0 do while i<8 if fm i =1 then fpscr 4 i:4 i+3 frb 4 i:4 i+3 i i+1 the contents of fr b[32?63] are placed into the fpscr under control of the field mask specified by fm. the field mask identifies the 4-bit fields affected. let i be an integer in the range 0?7. if fm i =1, fpscr field i (fpscr bits 4 i through 4 i+3) is set to the contents of the corresponding field of the low-order 32 bits of fr b. fpscr[fx] is altered only if fm 0 = 1. if msr[fp]=0, an attempt to execute mtfsf [ . ] causes a floating-point unavailable interrupt. other registers altered: fpscr fields selected by mask cr1 fx || fex || vx || ox (if rc=1) programming notes: updating fewer than all eight fields of the fpscr may have substantially poorer performance on some implementations than updating all the fields. when fpscr[0?3] is specified, bits 0 (fx) and 3 (ox) are set to the values of ( fr b) 32 and ( fr b) 35 (that is, even if this instruction causes ox to change from 0 to 1, fx is set from ( fr b) 32 and not by the usual rule that fx is set when an exception bit changes from 0 to 1). bits 1 and 2 (fex and vx) are set according to the usual rule (see table 10: fpscr field descriptions on page 59 ) and not from ( fr b) 33?34 . book e user 0 5 6 7 14 15 16 20 21 30 31 111111 / fm / fr b 1011000111rc instruction set RM0004 749/1176 mtfsfi mtfsfi move to fpscr field immediate mtfsfi cr d , uimm (rc=0) mtfsfi. cr d , uimm (rc=1) fpscr bf 4: cr d 4+3 uimm the value of the uimm field is placed into fpscr[ cr d]. fpscr[fx] is altered only if cr d = 0. if msr[fp]=0, an attempt to execute mtfsfi [ . ] causes a floating-point unavailable interrupt. other registers altered: fpscr[ cr d] cr1 fx || fex || vx || ox (if rc=1) programming note: when fpscr[0?3] is specified, bits 0 (fx) and 3 (ox) are set to the values of u0 and u3 (that is, even if this instruction causes ox to change from 0 to 1, fx is set from u0 and not by the usual rule that fx is set when an exception bit changes from 0 to 1). bits 1 and 2 (fex and vx) are set according to the usual rule (see table 10: fpscr field descriptions on page 59 ), and not from u1?2. book e user 0 5 6 8 9 1516 192021 3031 111111 cr d /// uimm / 0010000110rc RM0004 instruction set 750/1176 _ mtlr _mtlr move to link register se_mtlr r x lr gpr(rx) the contents of bits 32?63 of gpr( r x) are placed into the lr. special registers altered: lr 056111215 000000 0 0 1 0 0 1 rx vle user instruction set RM0004 751/1176 mtmsr mtmsr move to machine state register mtmsr r s msr rs 32:63 the contents of r s[32?63] are placed into the msr. execution of this instruction is restricted to supervisor mode. execution of this instruction is execution synchronizing. see execution synchronization on page 145 .? in addition, changes to the ee or ce bits are effective as soon as the instruction completes. thus if msr[ee]=0 and an external interrupt is pending, executing an mtmsr that sets msr[ee] causes the external interrupt to be taken before the next instruction is executed, if no higher priority exception exists. likewise, if msr[ce]=0 and a critical input interrupt is pending, executing an mtmsr that sets msr[ce] causes the critical input interrupt to be taken before the next instruction is executed if no higher priority exception exists. other registers altered: msr programming note: for a discussion of software synchronization requirements when altering certain msr bits, refer to chapter 2.18.2: synchronization requirements for sprs on page 130 .? book e supervisor 056101120213031 011111 r s /// 0010010010 / RM0004 instruction set 752/1176 mtpmr mtpmr move to performance monitor register mtpmr pmrn, r s pmreg(pmrn) gpr(rs) pmrn denotes a performance monitor register. section 2.16: performance monitor registers (pmrs) ,? lists supported performance monitor registers). the contents of gpr[ r s] are placed into the designated performance monitor register. when msr[pr] = 1, specifying a performance moni tor register that is not implemented and is not privileged (pmrn[5] = 0) results in an illegal instruction ex ception-type program interrupt. when msr[pr] = 1, specifying a performance monitor register that is privileged (pmrn[5] = 1) results in a privileged instruction exception-type program interrupt. when msr[pr] = 0, specifying a unimplemented performance monitor register is boundedly undefined. other registers altered: none performance monitor apu user/supervisor 056101115162021 31 011111 r s pmrn 5?9 pmrn 0?4 01110011100 instruction set RM0004 753/1176 mtspr mtspr move to special purpose register mtspr sprn ,r s spreg(sprn) rs sprn denotes an spr (see chapter 2.18: book e spr model on page 130 ,? and the user?s manual of the implementation for a list of all sprs that are implemented). the contents of r s are placed into the designated spr. for 32-bit sprs, the contents of r s[32?63] are placed into the spr. when msr[pr]=1, specifying an spr that is not implemented and is not privileged (sprn[5]=0) results in an ille gal instruction exception-ty pe program interrupt. when msr[pr]=1, specifying an spr that is priv ileged (sprn[5]=1) resu lts in a privileged instruction exception-type program interrupt. when msr[pr]=0, specifying an spr that is not implemented is boundedly undefined. other registers altered: see chapter 2.18: book e spr model on page 130 ,? or the user?s manual for the implementation. programming note: for a discussion of software synchronization requirements when altering certain sprs, please refer to chapter 2.18.2: synchronization requirements for sprs on page 130 .? book e user/supervisor 0 5 6 1011 1516 2021 3031 011111 r s sprn[5?9] sprn[0?4] 0111010011 / RM0004 instruction set 754/1176 mulhw mulhw multiply high word mulhw r d ,r a ,r b(rc=0) mulhw. r d ,r a ,r b(rc=1) prod 0:63 ra 32:63 rb 32:63 if rc=1 then do lt prod 0:31 < 0 gt prod 0:31 > 0 eq prod 0:31 = 0 cr0 lt || gt || eq || so rd 32:63 prod 0:31 rd 0:31 undefined bits 0?31 of the 64-bit product of the contents of r a[32?63] and the contents of r b[32?63] are placed into r d[32?63]. bits r d[0?31] are undefined. both operands and the product are interpreted as signed integers. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b / 001001011rc instruction set RM0004 755/1176 mulhwu mulhwu multiply high word unsigned mulhwu r d ,r a ,r b(rc=0) mulhwu. r d ,r a ,r b(rc=1) prod 0:63 ra 32:63 rb 32:63 if rc=1 then do lt prod 0:31 < 0 gt prod 0:31 > 0 eq prod 0:31 = 0 cr0 lt || gt || eq || so rd 32:63 prod 0:31 rd 0:31 undefined bits 0?31 of the 64-bit product the contents of r a[32?63] and the contents of r b[32?63] are placed into r d[32?63]. bits r d[0?31] are undefined. both operands and the product are interpreted as unsigned integers, except that if rc=1 the first three bits of cr field 0 are set by signed comparison of the result to zero. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b / 000001011rc RM0004 instruction set 756/1176 mulli mulli multiply low immediate mulli r d ,r a , simm prod 0:127 ra exts(simm) rd prod 64:127 bits 64?127 of the 128-bit product of the contents of r a and the sign-extended value of the simm field are placed into r d. both operands and the product are interpreted as signed integers. other registers altered: none programming notes: for mulli , the low-order 64 bits of the product are independent of whether the operands are regarded as signed or unsigned 64-bit integers. for mulli and mullw , bits 32?63 of the product are independent of whether the operands are regarded as signed or unsigned 32-bit integers. book e user 05610111516 31 000111 r d r asimm instruction set RM0004 757/1176 _ mulli x _mulli x multiply low [2 operand] immediate e_mulli r d ,r a , sci8 imm sci8(f,scl,ui8) prod 0:63 gpr(ra) imm gpr(rd) prod 32:63 bits 32?63 of the 64-bit product of the contents of gpr( r a) and the value of sci8 are placed into gpr( r d). both operands and the product are interpreted as signed integers. special registers altered: none e_mull2i r a , si prod 0:63 gpr(ra) exts(si 0:4 || si 5:15 ) gpr(ra) prod 32:63 bits 32?63 of the 64-bit product of the contents of gpr( r a) and the sign-extended value of the si field are placed into gpr( r a). both operands and the product are interpreted as signed integers. special registers altered: none vle user 0 5 6 1011 1516 2021222324 31 000110 rd ra 10100f scl ui8 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0100 si 5:15 RM0004 instruction set 758/1176 mullw mullw multiply low word mullw r d ,r a ,r b(oe=0, rc=0) mullw. r d ,r a ,r b(oe=0, rc=1) mullwo r d ,r a ,r b(oe=1, rc=0) mullwo. r d ,r a ,r b(oe=1, rc=1) prod 0:63 ra 32:63 rb 32:63 if oe=1 then do ov (prod 0:31 32 0) & (prod 0:31 32 1) so so | ov if rc=1 then do lt prod 32:63 < 0 gt prod 32:63 > 0 eq prod 32:63 = 0 cr0 lt || gt || eq || so rd prod 0:63 the 64-bit product of the contents of r a[32?63] and the contents of r b[32?63] is placed into r d. if oe=1, ov is set if the product cannot be represented in 32 bits. both operands and the product are interpreted as signed integers. other registers altered: cr0 (if rc=1) so ov (if oe=1) programming notes: bits 32?63 of the product are independent of whether the operands are regarded as signed or unsigned 32-bit integers. book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b oe011101011rc instruction set RM0004 759/1176 _ mullw x _mullw x multiply low word se_mullw r x ,r y prod 0:63 gpr(rx) 32:63 gpr(ry) 32:63 gpr(rx) prod 32:63 bits 32?63 of the 64-bit product of the contents of bits 32?63 of gpr( r x) and the contents of bits 32?63 of gpr( r y) is placed into gpr( r x). special registers altered: none 05678111215 00000101 ry rx vle user RM0004 instruction set 760/1176 nand nand nand nand r a ,r s ,r b(rc=0) nand. r a ,r s ,r b(rc=1) result 0:63 ? (rs & rb) if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result the contents of r s are anded with the contents of r b and the one?s complement of the result is placed into r a. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0111011100rc instruction set RM0004 761/1176 neg neg negate neg r d ,r a(oe=0, rc=0) neg. r d ,r a(oe=0, rc=1) nego r d ,r a(oe=1, rc=0) nego. r d ,r a(oe=1, rc=1) carry 0:63 carry( ? ra + 1) sum 0:63 ? ra + 1 if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum the sum of the one?s complement of the contents of r a and 1 is placed into r d. if r a contains the most negative 64-bit number (0x8000_0000_0000_0000), the result is the most negative number. similarly, if r a[32?63] contain the most negative 32-bit number (0x8000_0000), bits 32?63 of the result contain the most negative 32-bit number and, if oe=1, ov is set. other registers altered: cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a /// oe001101000rc RM0004 instruction set 762/1176 _ neg x _neg x negate se_neg r x result 32:63 ? gpr(rx)+ 1 gpr(rx) result 32:63 the sum of the one?s complement of the contents of gpr( r x) and 1 is placed into gpr( r x). if bits 32?63 of gpr( r x) contain the most negative 32-bit number (0x8000_0000), bits 32? 63 of the result contain the most negative 32-bit number special registers altered: none 056111215 000000000011 rx vle user instruction set RM0004 763/1176 nor nor nor nor r a ,r s ,r b(rc=0) nor. r a ,r s ,r b(rc=1) result 0:63 ? (rs | rb) if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result the contents of r s are ored with the contents of r b and the one?s complement of the result is placed into r a. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0001111100rc RM0004 instruction set 764/1176 _ not x _not x not se_not r x result 32:63 ? gpr(rx) gpr(rx) result 32:63 the contents of gpr( r x) are inverted. special registers altered: none 056112115 000000000010 rx vle user instruction set RM0004 765/1176 or or or [immediate [shifted] | with complement] or r a ,r s ,r b(rc=0) or. r a ,r s ,r b(rc=1) ori r a ,r s , uimm (s=0, rc=0) oris r a ,r s , uimm (s=1, rc=0) orc r a ,r s ,r b(rc=0) orc. r a ,r s ,r b(rc=1) if ?ori? then b 48 0 || uimm if ?oris? then b 32 0 || uimm || 16 0 if ?or[.]? then b rb if ?orc[.]? then b ? rb result 0:63 rs | b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result for ori , the contents of r s are ored with 48 0 || uimm. for oris , the contents of r s are ored with 32 0 || uimm || 16 0. for or [ . ], the contents of r s are ored with the contents of r b. for orc [ . ], the contents of r s are ored with the one?s complement of the contents of r b. the result is placed into r a. the preferred no-op is ori 0,0,0 other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0110111100rc 05610111516 31 01100s r s r auimm 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0110011100rc RM0004 instruction set 766/1176 _ or x _or x or [2 operand] [immediate | with complement] [shifted][and record] se_or r x ,r y e_or2i r d , ui e_or2is r d , ui e_ori r a ,r s , sci8 (rc = 0) e_ori. r a ,r s , sci8 (rc = 1) if ?e_ori[ . ]? then b sci8(f,scl,ui8) if ?e_or2i? then b 16 0 || ui 0:4 || ui 5:15 if ?e_or2is? then b ui 0:4 || ui 5:15 || 16 0 if ?se_or? then b gpr(rb) result 0:63 gpr(rs or rd or rx) | b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rd or rx) result for e_ori [ . ], the contents of gpr( r s) are ored with the value of sci8. for e_or2i, the contents of gpr( r d) are ored with 16 0 || ui. for e_or2is , the contents of gpr( r d) are ored with ui || 16 0. for se_or , the contents of gpr( r x) are ored with the contents of gpr( r y). the result is placed into gpr( r a or r x). the preferred ?no-op? (an instruction that does nothing) is: e_ori 0,0,0 special registers altered: cr0 (if rc = 1) 05678111215 01000100 ry rx vle user 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11000 ui 5:15 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11010 ui 5:15 0 5 6 1011 1516 192021222324 31 000110 rs ra 1101rcf scl ui8 instruction set RM0004 767/1176 rfci rfci return from critical interrupt rfci msr csrr1 nia csrr0[0:61] || 0b00 the rfci instruction is used to return from a critical class interrupt, or as a means of establishing a new context and synchroniz ing on that new context simultaneously. the contents of csrr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address csrr0[0?61]||0b00. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case, the value placed into srr0 or csrr0 by the interrupt processing mechanism is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in csrr0 at the time of the execution of the rfci ). execution of this instruction is restricted to supervisor mode. execution of this instruction is context synchronizing. see context synchronization on page 144 .? other registers altered: msr programming note: in addition to branch to lr ( bclr [ l ]) and branch to ctr ( bcctr [ l ]) instructions, rfi and rfci allow software to branch to any valid 64-bit address by using the respective 64-bit srr0 and csrr0. book e supervisor 0 5 6 2021 3031 010011 /// 0000110011 / RM0004 instruction set 768/1176 _ rfci _rfci return from critical interrupt se_rfci msr csrr1 nia csrr0 0:62 || 0b0 the se_rfci instruction is used to return from a critical class interrupt, or as a means of establishing a new context and synchroniz ing on that new context simultaneously. the contents of csrr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address csrr0[32?62]||0b0. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0 or csrr0 by the interrupt processing mechanism (see book e) is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in csrr0 at the time of the execution of the se_rfci ). execution of this instruction is privile ged and restricted to supervisor mode. execution of this instructio n is context synchronizing. special registers altered: msr 015 0000000000001001 vle supervisor instruction set RM0004 769/1176 rfdi rfdi return from debug interrupt rfdi if mode32 then m 32 if mode64 then m 0 msr dsrr1 nia m 0 || dsrr0 m:61 || 0b00 the rfdi instruction is used to return from a debug interrupt, or as a means of establishing a new context and synchronizing on that new context simultaneously. the contents of dsrr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address dsrr0[0?61]||0b00. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0, csrr0, or dsrr0 by the interrupt processing mechanism is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in dsrr0 at the time of the execution of the rfdi ). execution of this instruction is privile ged and restricted to supervisor mode. execution of this instructio n is context synchronizing. other registers altered: msr set as described above. debug apu supervisor 0 56 101115162021 3031 010011 /// 0 00010011 1 / RM0004 instruction set 770/1176 rfi rfi return from interrupt rfi msr srr1 nia srr0[0:61] || 0b00 the rfi instruction is used to return from a non-critical class interrupt, or as a means of simultaneously establishing a new context and synchronizing on that new context. the contents of srr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address srr0[0?61]||0b00. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0 or csrr0 by the interrupt processing mechanism is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in srr0 at the time of the execution of the rfi ). execution of this instruction is restricted to supervisor mode. execution of this instruction is context synchronizing. see context synchronization on page 144 .? other registers altered: msr book e supervisor 0 5 6 2021 3031 010011 /// 0000110010 / instruction set RM0004 771/1176 _ rfi _rfi return from interrupt se_rfi msr srr1 nia srr0 0:62 || 0b0 the se_rfi instruction is used to return from a non-critical class interrupt, or as a means of simultaneously establishing a new context and synchronizing on that new context. the contents of srr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched under control of the new msr value from the address srr0[32?62]||0b0. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0 or csrr0 by the interrupt processing mechanism (see book e) is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in srr0 at the time of the execution of the se_rfi ). execution of this instruction is privile ged and restricted to supervisor mode. execution of this instructio n is context synchronizing. special registers altered: msr 015 0000000000001000 vle supervisor RM0004 instruction set 772/1176 rfmci rfmci return from machine check interrupt rfmci msr mcsrr1 nia mcsrr0 0:61 || 0b00 the rfmci instruction is used to return from a machine check interrupt, or as a means of simultaneously establishing a new context and synchronizing on that new context. the contents of machine check save/restore register 1 (mcsrr1) are placed into the msr. if the new msr value does not enable any pending exceptions, the next instruction is fetched, under control of the new msr value from the address mcsrr0[32-61]|| 0b00. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0 or csrr0 by the interrupt processing mechanism is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in mcsrr0 at the time of the execution of rfi or rfci ). execution of this instruction is privileged and context synchronizing. special registers altered: msr machine check apu supervisor 0 5 6 2021 3031 010011 /// 0 0001001100 instruction set RM0004 773/1176 _ rlw _rlw rotate left word [immediate] e_rlw r a ,r s ,r b(rc=0) e_rlw. r a ,r s ,r b(rc=1) e_rlwi r a ,r s , sh (rc = 0) e_rlwi. r a ,r s , sh (rc = 1) if ? e_rlw [ . ]? then n gpr(rb) 59:63 else n sh result 32:63 rotl 32 (gpr(rs) 32:63 ,n) if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra) result 32:63 if e_rlw [ . ], let the shift count n be the contents of bits 59?63 of gpr( r b). if e_rlwi [ . ], let the shift count n be sh. the contents of gpr( r s) are rotated 32 left n bits. the rotated data is placed into gpr( r a). special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 2021 3031 011111 rs ra rb 0100011000rc 0 5 6 1011 1516 2021 3031 011111 rs ra sh 0100111000rc RM0004 instruction set 774/1176 rlwimi rlwimi rotate left word immediate then mask insert rlwimi r a ,r s , sh , mb , me (rc=0) rlwimi. r a ,r s , sh , mb , me (rc=1) n sh b mb+32 e me+32 r (rs 32:63 ,n) m mask(b,e) result 0:63 r&m | ra& ? m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result 0:63 the shift count n is the value sh. the contents of r s are rotated 32 left n bits. a mask is generated having 1 bits from bit mb+32 through bit me+32 and 0 bits elsewhere. the rotated data is inserted into r a under control of the generated mask. (if a mask bit is 1 the associated bit of the rotated data is placed into the target register, and if the mask bit is 0 the associated bit in the target register remains unchanged.) other registers altered: cr0 (if rc=1) programming note: uses for rlwimi [ . ]: to insert a k-bit field that is left-justified in r s[32?63], into r a[32?63] starting at bit position j, by setting sh=64-j, mb=j-32, and me=(j+k)-33. to insert an k-bit field that is right-justified in r s[32?63], into r a[32?63] starting at bit position j, by setting sh=64-(j+k), mb=j-32, and me=(j+k)-33. book e user 0 5 6 1011 1516 2021 2526 3031 010100 r s r ashmbmerc instruction set RM0004 775/1176 _ rlwimi _rlwimi rotate left word immediate then mask insert e_rlwimi r a ,r s , sh , mb , me n sh b mb+32 e me+32 r rotl 32 (gpr(rs) 32:63 ,n) m mask(b,e) result 32:63 r&m | gpr(ra)& ? m gpr(ra) result 32:63 let the shift count n be the value sh. the contents of gpr( r s) are rotated 32 left n bits. a mask is generated having 1 bits from bit mb+32 through bit me+32 and 0 bits elsewhere. the rotated data are inserted into gpr( r a) under control of the generated mask (if a mask bit is 1 the associated bit of the rotated data is placed into the target register, and if the mask bit is 0 the associated bit in the target register remains unchanged). special registers altered: none vle user 0 5 6 1011 1516 2021 2526 3031 011101 rs ra sh mb me 0 RM0004 instruction set 776/1176 _ rlwinm _rlwinm rotate left word immediate then and with mask e_rlwinm r a ,r s , sh , mb , me n sh b mb+32 e me+32 r rotl 32 (gpr(rs) 32:63 ,n) m mask(b,e) result 32:63 r & m gpr(ra) result 32:63 let the shift count n be sh. the contents of gpr( r s) are rotated 32 left n bits. a mask is generated having 1 bits from bit mb+32 through bit me+32 and 0 bits elsewhere. the rotated data are anded with the generated mask and the result is placed into gpr( r a). special registers altered: none vle user 0 5 6 1011 1516 2021 2526 3031 011101 rs ra sh mb me 1 instruction set RM0004 777/1176 rlwnm rlwnm rotate left word [immediate] then and with mask rlwnm r a ,r s ,r b , mb , me (rc=0) rlwnm. r a ,r s ,r b , mb , me (rc=1) rlwinm r a ,r s , sh , mb , me (rc=0) rlwinm. r a ,r s , sh , mb , me (rc=1) if ?rlwnm[.]? then n rb 59:63 else n sh b mb+32 e me+32 r (rs 32?63 ,n) m mask(b,e) result 0:63 r & m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result 0:63 if rlwnm [ . ], the shift count, n, is the contents of r b[59?63]. if rlwinm [ . ], n is sh. the r s contents are rotated 32 left n bits. the mask has 1s from bit mb+32 through bit me+32 and 0s elsewhere. the rotated data is anded with the mask and the result is placed into r a. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 2526 3031 010111 r s r a r bmbmerc 0 5 6 1011 1516 2021 2526 3031 010101 r s r ashmbmerc uses for rlwnm [.] uses for rlwinm [.] to extract a k -bit field starting at bit position j in r s[32?63], right-justified into r a[32?63] (clearing the remaining 32? k bits of r a[32?63])? ?by setting r b[59?63]= j + k-32 , mb=32? k , and me=31. ?by setting sh= j + k-32 , mb=32? k , and me=31. to extract a k -bit field that starts at bit position j in r s[32?63], left-justified into r a[32?63] (clearing the remaining 32? k bits of r a[32?63])? ?by setting r b[59?63]= j -32, mb=0, and me= k? 1. ?by setting sh= j -32, mb=0, and me= k ?1. to rotate the contents of bi ts 32?63 of a register left by k bits? ?setting r b[59?63]= k , mb=0, and me=31. ?setting sh= k , mb=0, and me=31. to rotate the contents of bits 32?63 of a register right by k bits? ?by setting r b[59?63] =32? k , mb=0, and me=31. ?by setting sh=32? k , mb=0, and me=31. RM0004 instruction set 778/1176 to shift the contents of bits 32?63 of a register right by k bits, by setting sh=32? k , mb= k , and me=31. to clear the high-order j bits of the contents of bits 32?63 of a register and then shift the result left by k bits, by setting sh= k , mb= j ? k and me=31? k . to clear the low-order k bits of bits 32?63 of a register, by setting sh=0, mb=0, and me=31? k . for the uses given above, bits r a[0?31] are cleared. uses for rlwnm [.] uses for rlwinm [.] instruction set RM0004 779/1176 sc sc system call sc srr1 msr srr0 cia+4 nia evpr[0:47] || ivor8[48-59] || 0b0000 msr[we,ee,pr,is,ds,fp,fe0,fe1] 0b0000_0000 sc is used to request a system service. a system call interrupt is generated. the msr contents are copied into srr1 and the address of the instruction after the sc instruction is placed into srr0. msr[we,ee,pr,is,ds,fp,fe0,fe1] are cleared. the interrupt causes the next instruction to be fetched from the address ivpr[0?47]||ivor8[48-59]||0b0000. sc is context synchronizing. see context synchronization on page 144 .? other registers altered: srr0 srr1 msr[we,ee,pr,is,ds,fp,fe0,fe1] book e supervisor 056 29 30 31 010001 /// 1 / RM0004 instruction set 780/1176 slw slw shift left word slw r a ,r s ,r b(rc=0) slw. r a ,r s ,r b(rc=1) n rb 59:63 r rotl32(rs 32:63 ,n) if rb 58 =0 then m mask(32,63-n) else m 64 0 result 0:63 r & m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result 0:63 the shift count n is the value specified by the contents of r b[58?63]. the contents of r s[32?63] are shifted left n bits. bits shifted out of position 32 are lost. zeros are supplied to the vacated positions on the right. the 32-bit result is placed into r a[32?63]. bits r a[0?31] are cleared. shift amounts from 32 to 63 give a zero result. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0000011000rc instruction set RM0004 781/1176 _ slw x _slw x shift left word [immediate] [and record] e_slwi r a ,r s , sh (rc = 0) e_slwi. r a ,r s , sh (rc = 1) se_slw r x ,r y se_slwi r x , ui5 if ?e_slwi[ . ]? then n sh if se_slw then n gpr(ry) 58:63 if se_slwi then n ui5 r rotl 32 (gpr(rs or rx) 32:63 ,n) if n<32 then m mask(32,63-n) else m 32 0 result 32:63 r & m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rx) result 32:63 let the shift count n be the value specified by the contents of bits 58?63 of gpr( r b or r y), or by the value of the sh or ui5 field. the contents of bits 32?63 of gpr( r s or r x) are shifted left n bits. bits shifted out of position 32 are lost. zeros are supplied to the vacated positions on the right. the 32-bit result is placed into bits 32?63 of gpr( r a or r x). shift amounts from 32 to 63 give a zero result. special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 2021 3031 011111 rs ra sh 0000111000rc 05678111215 01000010 ry rx 0 5 6 7 11 12 15 0110110 ui5 rx RM0004 instruction set 782/1176 _ sc _sc system call se_sc srr1 msr srr0 cia+2 nia ivpr 32:47 || ivor8 48:59 || 0b0000 msr we,ee,pr,is,ds,fp,fe0,fe1 0b0000_0000 se_sc is used to request a system service. a system call interrupt is generated. the contents of the msr are copied into srr1 and the address of the instruction after the se_sc instruction is placed into srr0. msr[we,ee,pr,is,ds,fp,fe0,fe1] are cleared. the interrupt causes the next instruction to be fetched from the address ivpr[32?47]||ivor8[48?59]||0b0000 this instruction is context synchronizing. special registers altered: srr0 sr r1 msr[we,ee,pr,is,ds,fp,fe0,fe1] 015 0000000000000010 vle user instruction set RM0004 783/1176 sraw sraw shift right algebraic word [immediate] sraw r a ,r s ,r b(rc=0) sraw. r a ,r s ,r b(rc=1) srawi r a ,r s , sh (rc=0) srawi. r a ,r s , sh (rc=1) if ?sraw[.]? then n rb 59:63 else n sh r rotl64(rs[32:63],64-n) if ?sraw[.]? & rb 58 =1 then m 64 0 else m mask(n+32,63) s rs 32 result 0:63 r&m | ( 64 s)& ? m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result 0:63 ca s & ((r& ? m) 32:63 0) if sraw [ . ], the shift count n is the contents of r b[58?63]. if srawi [ . ], the shift count n is the value of the sh field. the contents of r s[32?63] are shifted right n bits. bits shifted out of position 63 are lost. bit 32 of r s is replicated to fill the vacated positions on the left. the 32-bit re sult is placed into r a[32?63]. r s[32] is replicated to fill bits r a[0?31]. ca is set if r s[32?63] contain a negative value and any 1 bits are shifted out of bit position 63; otherwise ca is cleared. a shift amount of zero causes r a to receive exts( r s[32?63]), and ca to be cleared. for sraw [ . ] shift amounts from 32 to 63 give a result of 64 signed bits, and cause ca to receive r s[32] (that is, sign bit of r s[32?63]). other registers altered: ca cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 1100011000rc 0 5 6 1011 1516 2021 3031 011111 r s r a sh 1100111000rc RM0004 instruction set 784/1176 _ sraw x _sraw x shift right algebraic word [immediate] [and record] se_sraw r x ,r y se_srawi r x , ui5 if ?se_sraw? then n gpr(ry) 59:63 if ?se_srawi? then n ui5 r rotl 32 (gpr(rs or rx) 32:63 ,32-n) if ((se_sraw & gpr(ry) 58 =1) then m 32 0 else m mask(n+32,63) s gpr(rs or rx) 32 result 0:63 r&m | ( 32 s)& ? m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rx) result 32:63 ca s & ((r& ? m) 32:63 0) if se_sraw , let the shift count n be the contents of bits 58?63 of gpr( r y). if se_srawi , let the shift count n be the value of the ui5 field. the contents of bits 32?63 of gpr( r s or r x) are shifted right n bits. bits shifted out of position 63 are lost. bit 32 of r s or r x is replicated to fill vacate d positions on the left. the 32-bit result is placed into bits 32?63 of gpr( r a or r x). ca is set if bits 32?63 of gpr( r s or r x) contain a negative value and any 1 bits are shifted out of bit position 63; otherwise ca is cleared. a shift amount of zero causes gpr( r a or r x) to receive exts(gpr( r s or r x) 32:63 ), and ca to be cleared. for se_sraw, shift amounts from 32 to 63 give a result of 64 sign bits, and cause ca to receive bit 32 of the contents of gpr( r s or r x) (that is, sign bit of gpr( r s or r x) 32:63 ). special registers altered: ca cr0 (if rc = 1) 05678111215 01000001 ry rx 0 5 6 7 11 12 15 0110101 ui5 rx vle user instruction set RM0004 785/1176 srw srw shift right word srw r a ,r s ,r b(rc=0) srw. r a ,r s ,r b(rc=1) n rb 59?63 r rotl64(rs 32?63 ,64-n) if rb 58 =0 then m mask(n+32,63) else m 64 0 result 0:63 r & m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result 0:63 the shift count n is the value specified by the contents of r b[58?63]. the contents of r s[32?63] are shifted right n bits. bits shifted out of position 63 are lost. zeros are supplied to the vacated positions on the left. the 32-bit result is placed into r a[32?63]. bits r a[0?31] are cleared. shift amounts from 32 to 63 give a zero result. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 1000011000rc RM0004 instruction set 786/1176 _ srw x _srw x shift right word [immediate] [and record] e_srwi r a ,r s , sh (rc = 0) e_srwi. r a ,r s , sh (rc = 1) se_srw r x ,r y se_srwi r x , ui5 n gpr(rb) 59:63 if ?e_srwi[ . ]? then n sh if ?se_srw? then n gpr(ry) 59:63 if ?se_srwi? then n ui5 r rotl 32 (gpr(rs or rx) 32:63 ,32-n) if ((se_srw & gpr(ry) 58 =1) then m 32 0 else m mask(n+32,63) result 32:63 r & m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rx) result 32:63 if e_srwi , let the shift count n be the value of the sh field. if se_srw , let the shift count n be the contents of bits 58?63 of gpr( r y). if se_srwi , let the shift count n be the value of the ui5 field. the contents of bits 32?63 of gpr( r s or r x) are shifted right n bits. bits shifted out of position 63 are lost. zeros are supplied to the vacated positions on the left. the 32-bit result is placed into bits 32?63 of gpr( r a or r x). shift amounts from 32 to 63 give a zero result. special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 2021 3031 011111 rs ra sh 1000111000rc 05678111215 01000000 ry rx 0 5 6 7 11 12 15 0110100 ui5 rx instruction set RM0004 787/1176 stb stb store byte [with update] [indexed] stb r s , d (r a ) (d-mode, i=0) stbu r s , d (r a ) (d-mode, i=1) stbx r s ,r a ,r b (x-mode, u=0) stbux r s ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 mem(ea,1) rs 56:63 if u=1 then ra ea the ea is calculated as follows: for stb and stbu , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for stbx and stbux , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the contents of r s[56?63] are stored into the byte addressed by ea. if u=1 (with update), ea is placed into r a. if u=1 (with update) and r a=0, the instruction form is invalid. other registers altered: none book e user 05610111516 31 10011u r s r ad 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0011u10111 / RM0004 instruction set 788/1176 _ stb x _stb x store byte [with update] [indexed] e_stb r s , d (r a ) (d-mode) se_stb r z , sd4 (r x ) (sd4-mode) e_stbu r s , d8 (r a ) (d8-mode) if (ra=0 & !se_stb) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 28 0 || sd4)) 32:63 mem(ea,1) gpr(rs or rz) 56:63 if e_stbu then gpr(ra) ea let the ea be calculated as follows: for e_stb and e_stbu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_stb , let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field. the contents of bits 56?63 of gpr( r s) are stored into the byte in memory addressed by ea. if e_stbu , ea is placed into gpr( r a). if e_stbu and r a = 0, the instruction form is invalid. none vle user 0 5 6 1011 1516 31 001101 rs ra d 03478111215 1 0 0 1 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rs ra 00000100 d8 instruction set RM0004 789/1176 stfd stfd store floating-point double [with update] [indexed] stfd fr s , d (r a ) (d-mode, u=0) stfdu fr s , d (r a ) (d-mode, u=1) stfdx fr s ,r a ,r b (x-mode, u=0) stfdux fr s ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 mem(ea,8) frs if u=1 then ra ea the ea is calculated as follows: for stfd and stfdu , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d instruction field. for stfdx and stfdux , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the contents of fr s are stored into the double word addressed by ea. if u=1 (with update), ea is placed into r a. if u=1 (with update) and r a=0, the instruction form is invalid. if msr[fp]=0, stfd [ u ][ x ] causes a floating-point unavailable interrupt. other registers altered: none book e user 05610111516 31 11011u fr s r ad 0 5 6 1011 1516 2021 3031 011111 fr s r a r b 1011u10111 / RM0004 instruction set 790/1176 stfiwx stfiwx store floating-point as integer word indexed stfiwx fr s ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 mem(ea,4) frs[32:63] the ea is calculated as follows: for stfiwx , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the contents of fr s[32?63] are stored, without conversion, into the word addressed by ea. if the contents of fr s were produced, either directly or indirectly, by a load floating-point single instruction, a single-preci sion arithmetic instruction, or frsp , the value stored is undefined. (the contents of fr s are produced directly by such an instruction if fr s is the target register for the instruction. the contents of fr s are produced indirectly by such an instruction if fr s is the final target register of a sequence of one or more floating-point move instructions, with the input to the sequence having been produced directly by such an instruction.) if msr[fp]=0, an attempt to execute stfiwx causes a floating-point unavailable interrupt. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 fr s r a r b 1111010111 / instruction set RM0004 791/1176 stfs stfs store floating-point single [with update] [indexed] stfs fr s , d (r a ) (d-mode, u=0) stfsu fr s , d (r a ) (d-mode, u=1) stfsx fr s ,r a ,r b (x-mode, u=0) stfsux fr s ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 mem(ea,4) single(frs) if u=1 then ra ea the ea is calculated as follows: for stfs and stfsu , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for stfsx and stfsux , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the contents of fr s are converted to single format and stored into the word addressed by ea. if u=1 (with update), ea is placed into r a. if u=1 (with update) and r a=0, the instruction form is invalid. if msr[fp]=0, stfs [ u ][ x ] causes a floating-point unavailable interrupt. other registers altered: none book e user 0 4 5 6 10 11 15 16 31 11010u fr s r ad 0 5 6 1011 1516 2021 242526 3031 011111 fr s r a r b 1010u10111 / RM0004 instruction set 792/1176 sth sth store half word [with update] [indexed] sth r s , d (r a ) (d-mode, u=0) sthu r s , d (r a ) (d-mode, u=1) sthx r s ,r a ,r b (x-mode, u=0) sthux r s ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 mem(ea,2) rs 48:63 if u=1 then ra ea the ea is calculated as follows: for sth and sthu , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for sthx and sthux , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the contents of r s[48?63] are stored into the half word addressed by ea. if u=1 (with update), ea is placed into r a. if u=1 (with update) and r a=0, the instruction form is invalid. other registers altered: none book e user 0 4 5 6 10 11 15 16 31 10110u r s r ad 0 5 6 1011 1516 2021 242526 3031 011111 r s r a r b 0110u10111 / instruction set RM0004 793/1176 _ sth x _sth x store halfword [with update] [indexed] e_sth r s , d (r a ) (d-mode) se_sth r z , sd4 (r x ) (sd4-mode) e_sthu r s , d8 (r a ) (d8-mode) if (ra=0 & !se_sth) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 27 0 || sd4 || 0)) 32:63 mem(ea,2) gpr(rs or rz) 48:63 if e_sthu then gpr(ra) ea let the ea be calculated as follows: for e_sth and e_sthu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_sth let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 1 bit. the contents of bits 48?63 of gpr( r s) are stored into the half word in memory addressed by ea. if e_sthu , ea is placed into gpr( r a). if e_sthu and r a = 0, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 31 010111 rs ra d 03478111215 1 0 1 1 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rs ra 0 0 0 0 0 1 0 1 d8 RM0004 instruction set 794/1176 sthbrx sthbrx store half word byte-reverse sthbrx r s ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 mem(ea,2) rs 56:63 || rs 48:55 the ea is calculated as follows: for sthbrx , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. r s[56?63] are stored into bits 0?7 of the half word addressed by ea. bits 48?55 of r s are stored into bits 8?15 of the half word addressed by ea. other registers altered: none programming note: when ea references big-endian memory, these instructions have the effect of storing data in little-endian byte order. likewise, when ea references little-endian memory, these instructions have the effect of storing data in big-endian byte order. book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 1110010110 / instruction set RM0004 795/1176 stmw stmw store multiple word stmw r s , d (r a ) if ra=0 then ea 32 0 || exts(d) 32:63 else ea 32 0 || (ra+exts(d)) 32:63 r rs do while r 31 mem(ea,4) gpr(r) 32:63 r r + 1 ea 32 0 || (ea+4) 32:63 the ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign- extended value of the d instruction field. ea must be a multiple of 4. if it is not, either an alignment interrupt is invoked or the results are boundedly undefined. other registers altered: none book e user 05610111516 31 101111 r s r ad RM0004 instruction set 796/1176 _ stmw _stmw store multiple word e_stmw r s , d8 (r a ) (d8-mode) if ra=0 then ea exts(d8) 32:63 else ea (gpr(ra)+exts(d8)) 32:63 r rs do while r 31 mem(ea,4) gpr(r) 32:63 r r + 1 ea (ea+4) 32:63 let the ea be the sum of the contents of gpr( r a), or 32 0s if r a = 0, and the sign-extended value of the d8 instruction field. let n = (32 - r s). bits 32?63 of registers gpr( r s) through gpr(31) are stored in n consecutive words in memory starting at address ea. ea must be a multiple of 4. if it is not, either an alignment interrupt is invoked or the results are boundedly undefined. special registers altered: none vle user 0 5 6 1011 1516 2324 31 000110 rs ra 00001001 d8 instruction set RM0004 797/1176 stswi stswi store string word (immediate | indexed) stswi r s ,r a , nb stswx r s ,r a ,r b if ra=0 then a 64 0 else a ra if ?stswi? then ea 32 0 || a 32:63 if ?stswx? then ea 32 0 || (a + rb) 32:63 if ?stswi? & nb=0 then n 32 if ?stswi? & nb 0 then n nb if ?stswx? then n xer 57:63 r rs - 1 i 32 do while n > 0 if i=32 then r r + 1 (mod 32) mem(ea,1) gpr(r) i:i+7 i i + 8 if i = 64 then i 32 ea 32 0 || (ea+1) 32:63 n n - 1 the ea is calculated as follows: for stswi , ea is 32 zeros concatenated with bits 32?63 of the contents of r a, or 32 zeros if r a=0. for stswx , ea is 32 zeros concatenated with bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. if stswi , let n=nb if nb 0, n=32 if nb=0. if stswx , let n=xer[57?63]. n is the number of bytes to store. let nr=ceil(n 4): nr is the number of registers to supply data. n consecutive bytes starting at ea are stored from registers r s through gpr( r s+nr?1). data is stored from the low-order 4 bytes of each gpr. bytes are stored left to right from each gpr. the register sequence can wrap to gpr0. if stswx and n=0, no bytes are stored. other registers altered: none programming note: store string word and load string word instructions allow movement of data between memory and registers without concern for alignment. they can be used for a short move between arbitrary locations or long moves between misaligned memory fields. book e user 0 5 6 1011 1516 2021 3031 011111 r s r a nb 1011010101 / 0 5 6 1011 1516 2021 3031 011111 r s r a r b 1010010101 / RM0004 instruction set 798/1176 stw stw store word [with update] [indexed] stw r s , d (r a ) (d-mode, u=0) stwu r s , d (r a ) (d-mode, u=1) stwx r s ,r a ,r b (x-mode, u=0) stwux r s ,r a ,r b (x-mode, u=1) if ra=0 then a 64 0 else a ra if d-mode then ea 32 0 || (a + exts(d)) 32:63 if x-mode then ea 32 0 || (a + rb) 32:63 mem(ea,4) rs [32:63] if u=1 then ra ea the ea is calculated as follows: for stw and stwu , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the sign-extended value of the d field. for stwx and stwux , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. the contents of r s[32?63] are stored into the word addressed by ea. if u=1 (with update), ea is placed into r a. if u=1 (with update) and r a=0, the instruction form is invalid. other registers altered: none book e user 05610111516 31 10010u r s r ad 0 5 6 1011 1516 2021 242526 3031 011111 r s r a r b 0010u10111 / instruction set RM0004 799/1176 _ stw x _stw x store word [with update] [indexed] e_stw r s , d (r a ) (d-mode) se_stw r z , sd4 (r x ) (sd4-mode) e_stwu r s , d8 (r a ) (d8-mode) if (ra=0 & !se_stw) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 26 0 || sd4 || 2 0)) 32:63 mem(ea,4) gpr(rs or rz) 32:63 let the ea be calculated as follows: for e_stw and e_stwu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a = 0, and the sign-extended value of the d or d8 instruction field. for se_stw , let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 2 bits. the contents of bits 32?63 of gpr( r s) are stored into the word in memory addressed by ea. if e_stwu , ea is placed into gpr( r a). if e_stwu and r a = 0, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 31 010101 rs ra d 03478111215 1 1 0 1 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rs ra 00000110 d8 RM0004 instruction set 800/1176 stwbrx stwbrx store word byte-reverse stwbrx r s ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 mem(ea,4) rs 56:63 || rs 48:55 || rs 40:47 || rs 32:39 the ea is calculated as follows: for stwbrx , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. bits 56?63 of r s are stored into bits 0?7 of the word addressed by ea. bits 48?55 of r s are stored into bits 8?15 of the word addressed by ea. bits 40?47 of r s are stored into bits 16? 23 of the word addressed by ea. bits 32?39 of r s are stored into bits 24?31 of the word addressed by ea. other registers altered: none programming note: when ea references big-endian memory, these instructions have the effect of storing data in little-endian byte order. likewise, when ea references little-endian memory, these instructions have the effect of storing data in big-endian byte order. book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 1010010110 / instruction set RM0004 801/1176 stwcx. stwcx. store word conditional indexed stwcx . r s ,r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 if reserve then if reserve_addr = real_addr(ea) then mem(ea,4) rs [32:63] cr0 0b00 || 0b1 || xer so else u undefined 1-bit value if u then mem(ea,4) rs [32:63] cr0 0b00 || u || xer so reserve 0 else cr0 0b00 || 0b0 || xer so the ea is calculated as follows: for stwcx. , ea is bits 32?63 of the sum of the contents of r a, or 64 zeros if r a=0, and the contents of r b. if a reservation exists and the address specified by the stwcx. is the same as that specified by the lwarx instruction that established the reservation, the contents of r s[32?63] are stored into the word addressed by ea and the reservation is cleared. if a reservation exists but the address specified by stwcx. is not the same as that specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it is undefined whether the instruction completes without altering memory. if a reservation does not exist, the instruction completes without altering memory. cr field 0 is set to reflect whether the store operation was performed, as follows: cr0[lt,gt,eq,so] = 0b00 || store_performed || xer[so] ea must be a multiple of 4. if it is not, either an alignment interrupt is invoked or the results are boundedly undefined. other registers altered: cr0 programming notes: stwcx. , in combination with lwarx , permits the programmer to write a sequence of instructions that appear to perform an atomic update operation on a memory location. this operation depends on a single reservation resource in each processor. at most one reservation exists on any given processor: there are not separate reservations for words and for double words. because stwcx. instructions have implementation dependencies (such as the granularity at which reservations are managed), they must be used with care. the operating system should provide system library programs that use these instructions to implement the high-level synchronization functions (such as, test and set, and compare book e user 0 5 6 1011 1516 2021 31 011111 r s r a r b 00100101101 RM0004 instruction set 802/1176 and swap) needed by application programs. application programs should use these library programs, rather than use stwcx. directly. the granularity with which reservations are managed is implementation-dependent. therefore, the memory to be accessed by stwcx. should be allocated by a system library program. additional information can be found in atomic update pr imitives using lwarx and stwcx. on page 176 .? when correctly used, the load and reserve and store conditional instructions can provide an atomic update function for a single aligned word ( lwarx and stwcx. ) of memory. in general, correct use requires that lwarx be paired with stwcx. with the same address specified by both instructions of the pair. the only exception is that an unpaired stwcx. to any (scratch) effective address can be used to clear any reservation held by the processor. examples of correc t uses of these instructions to emulate primitives such as fetch and add, test and set, and compare and swap can be found in appendix c: programming examples on page 1143 . a reservation is cleared if any of the following events occur: ? the processor holding the reservation executes another load and reserve instruction; this clears the first reservation and establishes a new one. ? the processor holding the reservation executes a store conditional instruction to any address. ? another processor executes any store instruction to the address associated with the reservation. ? any mechanism, other than the processor holding the reservation, stores to the address associated with the reservation. see atomic update primitives using lwarx and stwcx. on page 176 ,? for additional information. instruction set RM0004 803/1176 _ sub _sub subtract se_sub r x ,r y sum 32:63 gpr(rx) + ? gpr(ry) + 1 gpr(rx) sum 32:63 the sum of the contents of gpr( r x), the one?s complement of contents of gpr( r y), and 1 is placed into gpr( r x). special registers altered: none 05678111215 00000110 ry rx vle user RM0004 instruction set 804/1176 subf subf subtract from subf r d ,r a ,r b(oe=0, rc=0) subf. r d ,r a ,r b(oe=0, rc=1) subfo r d ,r a ,r b(oe=1, rc=0) subfo. r d ,r a ,r b(oe=1, rc=1) carry 0:63 carry( ? ra + rb + 1) sum 0:63 ? ra + rb + 1 if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum the sum of the one?s complement of the contents of r a, the contents of r b, and 1 is placed into r d. other registers altered: cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b oe000101000rc instruction set RM0004 805/1176 _ subf x _subf x subtract from se_subf r x ,r y sum 32:63 ? gpr(rx) + gpr(ry) + 1 gpr(rx) sum 32:63 the sum of the one?s complement of the contents of gpr( r x), the contents of gpr( r y), and 1 is placed into gpr( r x). special registers altered: none 056101115 vle user RM0004 instruction set 806/1176 subfc subfc subtract from carrying subfc r d ,r a ,r b(oe=0, rc=0) subfc. r d ,r a ,r b(oe=0, rc=1) subfco r d ,r a ,r b(oe=1, rc=0) subfco. r d ,r a ,r b(oe=1, rc=1) carry 0:63 carry( ? ra + rb + 1) sum 0:63 ? ra + rb + 1 if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 the sum of the one?s complement of the contents of r a, the contents of r b, and 1 is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b oe000001000rc instruction set RM0004 807/1176 subfe subfe subtract from extended subfe r d ,r a ,r b(oe=0, rc=0) subfe. r d ,r a ,r b(oe=0, rc=1) subfeo r d ,r a ,r b(oe=1, rc=0) subfeo. r d ,r a ,r b(oe=1, rc=1) if e=0 then cin ca carry 0:63 carry( ? ra + rb + cin) sum 0:63 ? ra + rb + cin if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 for subfe [ o ][ . ], the sum of the one?s complement of the contents of r a, the contents of r b, and ca is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a r b oe010001000rc RM0004 instruction set 808/1176 subfic subfic subtract from immediate carrying subfic r d ,r a , simm carry 0:63 carry( ? ra + exts(simm) + 1) sum 0:63 ? ra + exts(simm) + 1 rd sum ca carry 32 the sum of the one?s complement of the contents of r a, the sign-extended value of the simm field, and 1 is placed into r d. other registers altered: ca book e user 05610111516 31 001000 r d r asimm instruction set RM0004 809/1176 _ subfic x _subfic x subtract from immediate carrying [and record] e_subfic r d ,r a , sci8 (rc = 0) e_subfic. r d ,r a , sci8 (rc = 1) imm sci8(f,scl,ui8) carry 32:63 carry( ? gpr(ra) + imm + 1) sum 32:63 ? gpr(ra) + imm + 1 if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rd) sum 32:63 ca carry 32 the sum of the one?s complement of the contents of gpr( r a), the value of sci8, and 1 is placed into gpr( r d). special registers altered: ca cr0 (if rc=1) vle user 0 5 6 1011 1516 2021222324 31 000110 rd ra 1011rcf scl ui8 RM0004 instruction set 810/1176 subfme subfme subtract from minus one extended subfme r d ,r a(oe=0, rc=0) subfme. r d ,r a(oe=0, rc=1) subfmeo r d ,r a(oe=1, rc=0) subfmeo. r d ,r a(oe=1, rc=1) if e=0 then cin ca carry 0:63 carry( ? ra + cin + 0xffff_ffff_ffff_ffff) sum 0:63 ? ra + cin + 0xffff_ffff_ffff_ffff if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 for subfme [ o ][ . ], the sum of ca, 64 1, and the one?s complement of the contents of r a is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a /// oe011101000rc instruction set RM0004 811/1176 subfze subfze subtract from zero extended subfze r d ,r a(oe=0, rc=0) subfze. r d ,r a(oe=0, rc=1) subfzeo r d ,r a(oe=1, rc=0) subfzeo. r d ,r a(oe=1, rc=1) if e=0 then cin ca carry 0:63 carry( ? ra + cin) sum 0:63 ? ra + cin if oe=1 then do ov carry 32 carry 33 so so | (carry 32 carry 33 ) if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so rd sum ca carry 32 for subfze [ o ][ . ], the sum of the one?s complement of the contents of r a and ca is placed into r d. other registers altered: ca cr0 (if rc=1) so ov (if oe=1) book e user 0 5 6 1011 1516 202122 3031 011111 r d r a /// oe011001000rc RM0004 instruction set 812/1176 _ subi x _subi x subtract immediate [and record] se_subi r x , oimm (rc = 0) se_subi. r x , oimm (rc = 1) sum 32:63 gpr(rx) + ?( 27 0 || offset(oim5)) + 1 if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rx) sum 32:63 the sum of the contents of gpr( r x), the one?s complement of the zero-extended value of the offseted oim5 field (a final value in the range 1?32), and 1 is placed into gpr( r x). special registers altered: cr0 (if rc = 1) 0 5 6 7 11 12 15 001001rc oim5 (1) 1. oimm = oim5 +1 rx vle user instruction set RM0004 813/1176 tlbivax tlbivax tlb invalidate virtual address indexed tlbivax r a ,r b if ra=0 then a 64 0 else a ra ea 32 0 || (a + rb) 32:63 as implementation-dependent value processid implementation-dependent value va as || processid || ea invalidatetlb(va) eis note: executing tlbivax invalidates any tlb entry that corresponds to a virtual address calculated by this instruction if iprot is not set; this includes invalidating tlb entries on other devices as well as on the processor executing tlbivax . thus an invalidate operation is broadcast throughout the coherent domain of the processor executing tlbivax . on some implementations, hid1[abe] must be set to allow management of external l2 caches (for implementations with l2 caches) as well as other l1 caches in the system. ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 address space (as) is defined as implementation-dependent (for example, it could be msr[ds] or a bit from an implementation-dependent spr). processid is implementation-dependent (for example, it could be from the pid or from an implementation-dependent spr). the eis implements the architected pid and additional implementation-specific pids. see section 2.12.1: process id registers (pid0?pidn) .? the virtual address (va) is the value as || processid || ea. a tlb entry corresponding to va is made invalid (that is, removed from the tlb). this instruction causes the target tlb entry to be invalidated in all processors. the operation performed by this instruction is ordered by mbar (or msync ) with respect to a subsequent tlbsync executed by the processor executing tlbivax . operations caused by tlbivax and tlbsync are ordered by mbar as a set of operations independent of the other sets that mbar orders. other registers altered: none programming notes: the effects of the invalidation are not guaranteed to be visible to the programming model until the completion of a context synchronizing operation. see context synchronization on page 144 .? care must be taken not to invalidate tlb entries that contain interrupt vector mappings. book e supervisor 0 5 6 1011 1516 2021 3031 011111 /// r a r b 1100010010 / RM0004 instruction set 814/1176 tlbre tlbre tlb read entry tlbre the rtl for the eis definition of tlbre is as follows: tlb_entry_id = mas0(t lbsel, esel | mas2(epn) result = mmu(tlb_entry_id) mas0, mas1, mas2, mas3, (and mas7 if hid0[en_mas7_update] = 1) = result bits 6?20 of the encoding are allocated for implementation-dependent use and may be used to specify the source tlb entry, the source portion of the source tlb entry, and the target resource into which the result is placed. the eis makes no use of these bits. the implementation-defined tlb entry is read, and the implementation-defined portion of the tlb entry is extracted and placed into an implementation-defined target resource. if the instruction specifies a tlb entry that does not exist, the results are undefined. eis implementation note: tlbre causes the contents of a single tlb entry to be extracted from the mmu and be placed in the corresponding fields of the mmu assist (mas) registers. the entry extracted is specif ied by the tlbsel, esel and epn fields of mas0 and mas2. the contents extracted from the mmu are placed in mas0?mas3. see the user?s manual for the implementation. execution of this instruction is restricted to supervisor mode. other registers altered: mas0, mas1, mas2, and mas3, as defined by the eis book e supervisor 0 5 6 2021 3031 011111 /// (1) 1110110010/ 1 1. this field is defined as allocated by the book e architecture, for possible use in an implementation. these bits are not implemented by the eis. instruction set RM0004 815/1176 tlbsx tlbsx tlb search indexed tlbsx r a ,r b if ra!=0 then generate exception ea = 32 0 || gpr(rb) 32:63 processid = mas6(spid) as = mas6(sas) va0 = as || (mmucfg[pidsize] + 1) 0 || ea va1 = as || processid || ea if valid_tlb_matching_entry_exists (va0) or valid_tlb_matching_entry_exists (va1) # # mas0, mas1, mas2, mas3 = result ea calculation: addressing modeea for r a=0ea for r a 0 32 0 || r b 32:63 32 0 || ( r a+ r b) 32:63 note that ra = 0 is a preferred form for tlbsx and that some st implementations take an illegal instruction exception prog ram interrupt if ra != 0. virtual address 0 (va0) is the value as || (mmucfg[pidsize] + 1) 0 || ea virtual address 1 (va1) is the value as || processid || ea if the tlb contains an entry corresponding to va, an implementation-dependent value is placed into an implementation-dependent-specifi ed target. otherwise the contents of the implementation-dependent-specified target are left undefined. other registers altered: implementation-dependent. see supervisor-level tlb management instructions on page 183 . book e supervisor 0 5 6 1011 1516 2021 3031 011111 /// (1) r a r b 1110010010/ 1 1. this field is defined as allocated by the book e architecture, for possible use in an implementation. these bits are not implemented by the eis. RM0004 instruction set 816/1176 tlbsync tlbsync tlb synchronize tlbsync tlbsync provides an ordering function for the effects of all tlbivax instructions executed by the processor executing tlbsync , with respect to the memory barrier created by a subsequent msync instruction executed by the same processor. executing tlbsync ensures that all of the following occur. all tlb invalidations caused by tlbivax instructions preceding the tlbsync instruction will have completed on any other processor be fore any memory accesses associated with data accesses ca used by instructions following the msync instruction are performed with respect to that processor. all memory accesses by other processors for which the address was translated using the translations being invalidated, will ha ve been performed with respect to the processor executing the msync instruction, to the extent required by the associated memory-coherence required attributes, before the mbar or msync instruction?s memory barrier is created. the operation performed by this instruction is ordered by the mbar and msync instructions with respect to preceding tlbivax instructions executed by the processor executing the tlbsync instruction. the operations caused by tlbivax and tlbsync are ordered by mbar as a set of operations that is independent of the other sets that mbar orders. the tlbsync instruction may complete before operations caused by tlbivax instructions preceding the tlbsync instruction have been performed. execution of this instruction is restricted to supervisor mode. other registers altered: none book e supervisor 0 5 6 2021 3031 011111 /// 1000110110 / instruction set RM0004 817/1176 tlbwe tlbwe tlb write entry tlbwe bits 6?20 of the instruction encoding are allocated for implementation-dependent use, and may be used to specify the target tlb entry, the target portion of the target tlb entry, and the source of the value that is to be written into the tlb. the eis does not make use of these bits. the contents of the implementation-dependent?specified source are written into the implementation-dependent?specified portion of the implementation-dependent?specified tlb entry. if the instruction specifies a tlb entry that does not exist, the results are undefined. execution of this instruction may cause other implementation-dependent effects. see the user?s manual for the implementation. execution of this instruction is restricted to supervisor mode. other registers altered: none programming notes: the effects of the update are not guaranteed to be visible to the programming model until the completion of a context synchronizing operation. see context synchronization on page 144 .? care must be taken not to invalidate any tlb entry that contains the mapping for any interrupt vector. book e supervisor 0 5 6 2021 3031 011111 /// (1) 1111010010 / 1. this field is defined as allocated by the book e architecture, for possible use in an implementation. these bits are not implemented by the eis. RM0004 instruction set 818/1176 tw tw trap word [immediate] tw to ,r a ,r b twi to ,r a , simm a exts(ra 32:63 ) if ?tw? then b exts(rb 32:63 ) if ?twi? then b exts(simm) if (a < b) & to 0 then trap if (a > b) & to 1 then trap if (a = b) & to 2 then trap if (a < u b) & to 3 then trap if (a > u b) & to 4 then trap for tw , the contents of r a[32?63] are compared with the contents of r b[32?63]. for twi , the contents of r a[32?63] are compared with the sign-extended value of the simm field. if any bit in the to field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. other registers altered: none book e user 0 5 6 1011 1516 2021 3031 011111 to r a r b 0000000100 / 05610111516 31 000011 to r asimm instruction set RM0004 819/1176 wrtee wrtee write msr external enable [immediate] wrtee r s wrteei e if ?wrtee? then msr[ee] rs 48 if ?wrteei? then msr[ee] e for wrtee , r s[48] is placed into msr[ee]. for wrteei , the value specified in the e field is placed into msr[ee]. execution of this instruction is restricted to supervisor mode. in addition, changes to msr[ee] are effective as soon as the instruction completes. thus if msr[ee]=0 and an external interrupt is pending, executing a wrtee or wrteei that sets msr[ee] causes the external interrupt to be taken before the next instruction is executed, if no higher priority exception exists. other registers altered: msr programming note: wrtee and wrteei are used to update of msr[ee] without affecting other msr bits. typical usage is as follows: mfmsr rn #save ee in gpr(rn) 48 wrteei 0 #turn off ee :: : : : #code with ee disabled :: : wrtee rn #restore ee without altering other msr bits that may have changed book e supervisor 056101120213031 011111 r s /// 0010000011 / 0 5 6 151617 2021 3031 011111 /// e /// 0010100011 / RM0004 instruction set 820/1176 xor xor xor [immediate [shifted]] xor r a ,r s ,r b(rc=0) xor. r a ,r s ,r b(rc=1) xori r a ,r s , uimm (s=0, rc=0) xoris r a ,r s , uimm (s=1, rc=0) if ?xori? then b 48 0 || uimm if ?xoris? then b 32 0 || uimm || 16 0 if ?xor[.]? then b rb result 0:63 rs b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so ra result for xori , the contents of r s are xored with 48 0 || uimm. for xoris , the contents of r s are xored with 32 0 || uimm || 16 0. for xor [ . ], the contents of r s are xored with the contents of r b. the result is placed into r a. other registers altered: cr0 (if rc=1) book e user 0 5 6 1011 1516 2021 3031 011111 r s r a r b 0100111100rc 0 4 5 6 10 11 15 16 31 01101s r s r auimm instruction set RM0004 821/1176 _ xor x _xor x xor [immediate] [and record] e_xori r a ,r s , sci8 (rc = 0) e_xori. r a ,r s , sci8 (rc = 1) if ?e_xori[ . ]? then b sci8(f,scl,ui8) result 32:63 gpr(rs) b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra) result for e_xori [ . ], the contents of gpr( r s) are xored with sci8. the result is placed into gpr( r a). special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 192021222324 31 000110 rs ra 1110rcf scl ui8 RM0004 part ii: eis-defined extensions to the book e architecture 822/1176 part ii: eis-defined extensions to the book e architecture this part describes the extensions defined by the book e implementation standards (eis). it consists of the following: chapter 7: auxiliary processing units (apus) on page 823 ,? describes apus such as the isel instruction, performance mo nitor, signal processing engine (spe), locking, and machine check apus. chapter 8: storage-related apus on page 848 ,? describes the following apus defined by the storage architecture: ? chapter 8.1: cache line locking apu on page 848 ? ? chapter 8.2: direct cache flush apu on page 850 ? ? chapter 8.3: cache way partitioning apu on page 851 ? subsequent chapters describe the vle extension ? chapter 9: vle introduction on page 852 ? ? chapter 10: vle storage addressing on page 759 ? chapter 11: vle compatibility with the eis on page 856 ? ? chapter 12: vle instruction classes on page 860 ? ? chapter 13: vle instruction set on page 891 ? ? chapter 14: vle instruction index on page 967 ? auxiliary processing units (apus) RM0004 823/1176 7 auxiliary processing units (apus) this chapter describes the apus defined by the eis, which are as follows: chapter 7.1: integer select apu ? chapter 7.2: performance monitor apu ? chapter 7.3: signal processing engine apu (spe apu) ? chapter 7.4: embedded vector and scalar single-precision floating-point apus (spfp apus) ? chapter 7.5: machine check apu ? chapter 7.6: debug apu ? chapter 7.7: alternate time base ? note that individual processors may implement apus that are not defined by the eis. individual processors may either further extend these apus or may implement a subset of the resources described here. see the documentation for the individual implementation. 7.1 integer select apu control code, which is characterized by unpredictable short branches, is common in embedded applications. when mispredicted, these branches cause long pipeline delays. the integer select ( isel ) apu consists of a single instruction ( isel ), a conditional register move that helps eliminate some of these branches. the isel instruction works as follows: if cr b then r d = r a else r d = r b the isel instruction allows more efficient implementation of a condition sequence such as the one in the following generic example: int16 global1,?, global37,...; .... void procedure17(int16 parm) { if (global1 == 27) { global37 = parm + 17; } else { global37 = parm - 17; } } 7.1.1 integer select apu programming model the integer select apu includes only the isel instruction, described in chapter 6: instruction set on page 330 .? it accesses the gprs and the cr and does not implement additional registers or interrupt resources. RM0004 auxiliary processing units (apus) 824/1176 7.1.2 using isel to improve conditional branch performance the integer select instruction, isel , can be used to handle short conditional branch segments more efficiently. isel has two source registers and one destination register. under the control of a specified condition code bit, it copies one or the other source operand to the destination. table 208 shows a coding example with and without the isel instruction. the sequence without isel turns conditional branches into a code sequence that sets a condition code according to the results of a computation. it uses a conditional branch to choose a target sequence, but needs an unconditional branch for the if clause. the conditional branch is often hard to predict, the code sequences are generally small, and the resulting throughput is typically low. the sequence using isel does the following: sets a condition code according to the results of a comparison has code that executes both the if and the else segments has a final statement that copies the results of one of the segments to the desired destination register works well for small code segments and for unpredictable branches can reduce code size 7.2 performance monitor apu the eis defines the performance monitor as an apu. software communication with the performance monitor apu is achieved through performance monitor registers (pmrs) rather than sprs. the pmrs are used for enabling conditions that can trigger an apu-defined performance monitor interrupt. 7.2.1 performance monito r apu programming model the performance monitor apu provides a set of pmrs for defining, enabling, and counting conditions that trigger the performance interrupt. the apu defines instructions for reading and writing the pmrs. table 208. recoding with isel code sequence without isel code sequence with isel cmpi cr3, r17, 27; bne cr3, notequal; addi r15, r17, 17; jmp assign; notequal: addi r15, r17, -17; assign: stw r15, (rglobals + g37); cmpi cr3, r17, 27; addi r15, r17, 17; addi r16, r17, -17; isel r15, r15, r16, cr3.eq stw r15, (rglobals + g37); auxiliary processing units (apus) RM0004 825/1176 performance monitor apu registers the performance monitor apu defines ivor35 (spr 531) for indicating the address of the performance monitor interrupt vector. ivor35 is described in interrupt vector offset registers (ivors) on page 83 .? the apu also defines a set of pmrs that are separate from the spr resources. however, like sprs and as shown in ta bl e 2 0 9 and ta bl e 2 1 0 , bit 5 indicates whether a register is user- or supervisor-accessible. supervisor-level pmrs in ta b l e 2 0 9 are accessed through the mtpmr and mfpmr instructions. attempting to read or write supervisor-level registers while in user-mode caus es a privilege exception. the user-level pmrs in table 210 are read-only and are accessed with the mfpmr instruction. attempting to write user-level registers in either supervisor or user mode causes an illegal instru ction exception. table 209. performance monitor registers?supervisor level register name abbreviation pmr number pmr[0?4] pmr[5?9] counter 0 pmc0 16 00000 10000 counter 1 pmc1 17 00000 10001 counter 2 pmc2 18 00000 10010 counter 3 pmc3 19 00000 10011 local control a0 pmlca0 144 00100 10000 local control a1 pmlca1 145 00100 10001 local control a2 pmlca2 146 00100 10010 local control a3 pmlca3 147 00100 10011 local control b0 pmlcb0 272 01000 10000 local control b1 pmlcb1 273 01000 10001 local control b2 pmlcb2 274 01000 10010 local control b3 pmlcb3 275 01000 10011 global control 0 pmgc0 400 01100 10000 table 210. performance monitor registers?user level (read-only) register name abbreviation pmr number pmr[0?4] pmr[5?9] counter 0 upmc0 0 00000 00000 counter 1 upmc1 1 00000 00001 counter 2 upmc2 2 00000 00010 counter 3 upmc3 3 00000 00011 local control a0 upmlca0 128 00100 00000 local control a1 upmlca1 129 00100 00001 local control a2 upmlca2 130 00100 00010 local control a3 upmlca3 131 00100 00011 local control b0 upmlcb0 256 01000 00000 RM0004 auxiliary processing units (apus) 826/1176 pmrs are fully described in chapter 2.16 on page 124 .? performance monitor apu instructions the apu also defines the instructions in ta b l e 2 1 1 to move to and move from these pmrs. full descriptions of these instructions can be found in chapter 6 on page 330 .? performance monitor apu interrupt model the performance monitor apu provides a performance monitor interrupt that is triggered by an enabled condition or event. 7.3 signal processing engine apu (spe apu) this section describes the spe apu programming model, exceptions, and functions. 7.3.1 overview this section describes the instruction set architecture of the signal processing engine (spe) apu. the spe apu is designed to accelerate signal processing applications normally suited to dsp operation. this is accomplishe d using short (two-element) vectors within 64- bit gprs and using single instruction multiple data (simd) operations to perform the requisite computations. spe also architects an accumulator register to allow for back-to- back operations without loop unrolling. local control b1 upmlcb1 257 01000 00001 local control b2 upmlcb2 258 01000 00010 local control b3 upmlcb3 259 01000 00011 global control 0 upmgc0 384 01100 00000 table 211. performance monitor apu instructions name mnemonic syntax move from performance monitor register mfpmr r d,pmrn move to performance monitor register mtpmr pmrn, r s table 210. performance monitor registers?user level (read-only) (continued) register name abbreviation pmr number pmr[0?4] pmr[5?9] auxiliary processing units (apus) RM0004 827/1176 7.3.2 nomenclature and conventions several conventions regarding nomenclature are used in this document: the signal processing engi ne apu is abbreviated as spe. all register bit numbering is 64-bit, with bit 0 being the most significant bit. registers that are only 32-bit define bit 32 as the most significant bit. for both 32- and 64-bit registers, bit 63 is the least significant bit. bits 0 to 31 of a 64-bit register are referenced as upper word, even word or high word element of the register. bits 32?63 are referred to as lower word, odd word, or low word element of the register. each half is an element of a 64-bit gpr. bits 0 to 15 and bits 32 to 47 are referenced as even half words. bits 16 to 31 and bits 48 to 63 are referenced as odd half words. mnemonics for spe instructio ns generally begin with th e letters ?ev? (embedded vector). 7.3.3 programming model this section describes spe register s, instructions, and interrupts. general operation spe instructions generally take elements from each source register and operate on them with the corresponding elements of a second source register (and/or the accumulator) to produce results. results are placed in the destination register and/or the accumulator. instructions that are vector in nature (that is, they produce results of more than one element) provide results for each element that are independent of the computation of the other elements. these instructions can also be used to perform scalar dsp operations by ignoring the results of the upper 32-bit half of the register file. there are no record forms of spe instructions . spe compare instructio ns store the compare result into the condition register (cr). the meaning of the cr bits is now overloaded for spe operations. spe compare instruct ions specify a cr field, tw o source registers, and the type of compare: greater than, less than, or, equal. two bits of the cr field are written with the result of the vector compare, one for each element. the remaining two bits reflect the anding and oring of the vector compare results. gpr registers the spe apu requires a gpr regi ster file with thirty-two 64 -bit registers. for 32-bit implementations, powerpc book e instructions that normally operate on a 32-bit register file access and change only the least significant 32 bits of the gprs, leaving the most significant 32 bits unchanged. for 64-bit implem entations, operation of these instructions is unchanged, that is, those instructions continue to operate on the 64-bit registers as they would if the spe apu was not implemented. spe apu instructions view the 64-bit register as being composed of a vector of two elements, each of which is 32 bits wide. (some instructions read or write 16-bit elements.) the most significant 32 bits are called the upper word, high word or even word. the least significant 32 bits are called the lower word, low word or odd word. unless otherwise specified, spe instructions write all 64 bits of the destination register. 0313263 gpr upper word lower word RM0004 auxiliary processing units (apus) 828/1176 accumulator register a partially visible accumulator register (acc) is provided for the integer/fractional multiply accumulate (mac) forms of instructions. the accumulator is a 64-bit register that holds the results of the multiply accumulate forms of spe fixed-point instructions. the accumulator allows the back-to-back execution of dependent mac instructions, something that is found in the inner loops of dsp code such as fir and f ft filters. the accumulator is partially visible to the programmer in the sense that its results do not have to be explicitly read to use them. instead they are always copied into a 64-bit de stination gpr, which is specified as part of the instruction. based upon the type of instruction, the accumulator can hold either a single 64-bit value or a vector of two 32-bit elements. signal processing embedded floating-point status and control register (spefscr) status and control for spe us es the spefscr, described in chapter 2.14.1: signal processing, embedded floating-point status, control register (spefscr) on page 119 .? the embedded floating-point apus also use spefscr. status and control bi ts are shared for embedded floating-point operations and spe vector operations. the spefscr is implemented as spr number 512 and is read and written by the mfspr and mtspr instructions in both user and supervisor mode. spe exception bit in esr esr[spe] is defined as the spe exception bit. this bit is se t whenever the processor takes an interrupt related to the execution of spe instructions. (note that the same bit is used for embedded floating-point apu exceptions . thus, spe and embe dded floating-point exceptions are indistinguishable in the esr.) spe available bit in msr msr[spe] is defined as the spe available bit. if th is bit is not set and software attempts to execute an spe instruction, the spe ap u unavailable interrupt is taken. software note: this bit can be used by software to detect when a process uses the upper 32 bits of a 64-bit register on a 32-bit implementation and thus save them on context switch. data formats the spe apu provides two different data formats, integer and fractional. both data formats can be treated as signed or unsigned quantities. integer format integer data format is the same as what is conventionally used in computing. unsigned integers consist of 16-, 32-, or 64-bit binary integer values. the largest representable value is 2 n ? 1, where n represents the number of bits in the value. the smallest representable value is 0. computations that produce values larger than 2 n ?1 or smaller than 0 set ov or ovh in spefscr. signed integers consist of 16-, 32-, or 64-bit binary values in two?s-complement form. the largest representable value is 2 n?1 ? 1, where n represents the number of bits in the value. 0313263 acc upper word lower word auxiliary processing units (apus) RM0004 829/1176 the smallest representable value is ?2 n?1 . computations that produce values larger than 2 n?1 ? 1 or smaller than ?2 n?1 set ov or ovh in spefscr. fractional format fractional data format is the same that is conventionally used for dsp fractional arithmetic. fractional data is useful for represen ting data converted from analog devices. unsigned fractions consist of 16-, 32-, or 64-bit binary fractional values that range from 0 to less than 1. unsigned fractions place the decimal point immediately to the left of the most significant bit. the most significant bit of the value represents the value 2 ?1 , the next most significant bit represents the value 2 ?2 , and so on. the largest representable value is 1 ? 2 ? n , where n represents the number of bits in the value. the smallest representable value is 0. computations that produce values larger than 1 ? 2 ?n or smaller than 0 set ov or ovh in spefscr. spe does not contain ex plicit instructions that ma nipulate unsigned fractional data. unsigned integer forms produce the same bit results as unsigned fractional values would; therefore, unsigned fractional instruction forms are not defined for spe. signed fractions consist of 16-, 32-, or 64-bit binary fractional values in two?s-complement form that range from ?1 to less than 1. signed fractions place the decimal point immediately to the right of the most significant bit. the largest representable value is 1 ? 2 ?(n?1) , where n represents the number of bits in the value. the smallest representable value is ?1. computations that produce values larger than 1 ? 2 ?(n?1) or smaller than ?1 set ov or ovh in the spefscr. multiplication of two signed fractional values causes the result to be shifted left one bit to remove the resultant redundant sign bit in the product. in this case, a 0 bit is concatenated as the least-significant bit (lsb) of the shifted result. computational operations spe supports several different computational cap abilities. these can be grouped as follows: simple vector instructions. these instructions use the corresponding low- and high- word elements of the operands to produce a vector result that is placed in the destination register, the accumulator, or both. figure 178 shows how operations are typically performed in vector operations. figure 178. two-element vector operations multiply and accumulate instructions. these instructions perform multiply operations, add the result to the accumulator and place the result into the destination register and the accumulator. these instructions are composed of different multiply forms, data 0313263 r a r b operation operation r d RM0004 auxiliary processing units (apus) 830/1176 formats, and data accumulate options. the mnemonics for these instructions indicate their various characteristics. these are shown in table 212 . load and store instructions. these instructi ons provide load and store capabilities for moving data to and from memory. a variety of forms are provided that position data for efficient computation. compare and miscellaneous instructions. these instructions perform miscellaneous functions such as field manipulation, bit reversed incrementing, and vector compares. table 212. mnemonic extensions for multiply accumulate instructions extension meaning comments multiply form he half word even 16 x 16 32 heg half word even guarded 16 x 16 32, 64-bit final accum result ho half word odd 16 x 16 32 hog half word odd guarded 16 x 16 32, 64-bit final accum result w word 32 x 32 64 wh word high 32 x 32 32 (high order 32 bits of product) wl word low 32 x 32 32 (low order 32 bits of product) data format smf signed modulo fractional modulo, no saturation or overflow smi signed modulo integer modulo, no saturation or overflow ssf signed saturate fractional saturation on product and accumulate ssi signed saturate integer saturation on product and accumulate umi unsigned modulo integer modulo, no saturation or overflow usi unsigned saturate integer saturation on product and accumulate accumulate option a place in accumulator result accumulator aa add to accumulator accumulator + result accumulator aaw add to accumulator accumulator 0:31 + result 0:31 accumulator 0:31 accumulator 32:63 + result 32:63 accumulator 32:63 an add negated to accumulator accumulator ? result accumulator anw add negated to accumulator accumulator 0:31 ? result 0:31 accumulator 0:31 accumulator 32:63 ? result 32:63 accumulator 32:63 auxiliary processing units (apus) RM0004 831/1176 spe exceptions and interrupts the apu defines the fo llowing spe exceptions: spe/embedded floating-point unavailabl e exception (cause s the spe/embedded floating point unavailable interrupt) spe vector alignment exception (c auses the alignment interrupt) interrupt vector offset registers (ivors) ivor 32 (spe/embedded floating-point unavailable interrupt) and ivor5 (alignment interrupt) are used by the interrupt model. the spr number for ivor32 is 528; ivor5 is defined by book e. these registers are privileged. spe/embedded floating point unavailable exception the spe/embedded floatin g point unavailable exception o ccurs when execution of an spe instruction (except brinc ) is attempted and bit 38 (spe av ailable, msr[spe]) is not set. if the spe/embedded floati ng point unavailable exception oc curs, a spe/embed ded floating point unavailable exception interrupt is taken and the processor suppresses execution of the instruction causing the exception. srr0, sr r1, msr, and esr are modified as follows: srr0 is set to the ea of the instruction causing the interrupt. srr1 is set to the contents of the msr at the time of the interrupt. msr bits ce, me, and de are unchanged. all other bits are cleared. esr[36] bit is set. all other esr bits are cleared. instruction execution resumes at address ivpr[0?47]||ivor32[48?59]||0b0000. software note: this exception is also used by the embedded floating-point apus in the same manner. it should be used by software to determine if the application is using the upper 32 bits of the gprs and thus is required to save and restore them on a context switch. spe vector alignment exception the spe vector alignment exceptio n is taken if the ea of any of the following instructions in not aligned to a 64-bit boundary: evldd , evlddx , evldw , evldwx , evldh , evldhx , evstdd , evstddx , evstdw , evstdwx , evstdh , or evstdhx . when an spe vector alignment exception occurs, an alignment interrupt is taken and the processor suppresses execution of the instruction causing the exception. srr0, sr r1, msr, esr, and dear are modified as follows: srr0 is set to the ea of the instruction causing the interrupt. srr1 is set to the contents of the msr at the time of the interrupt. msr bits ce, me, and de are unchanged. all other bits are cleared. esr[56] bit is set. esr[st] is set if the inst ruction causing the interrupt is a store. all other esr bits are cleared. dear is updated with the ea used in the load or the store. instruction execution resumes at address ivpr[0?47]||ivor32[48?59]||0b0000. interrupt priorities the following list shows the priority order in which spe apu and spfp apu interrupts are taken (see embedded floating-point interrupts on page 837 ? ): RM0004 auxiliary processing units (apus) 832/1176 1. spe apu unavailable interrupt 2. spe vector alignment interrupt 3. embedded floating-point data interrupt 4. embedded floating-point round interrupt 7.3.4 instruction definitions chapter 6: instruction set on page 330 ,? gives complete descrip tions of spe and embedded floating-point instructions. chapter 6.3.1 on page 336 ,? provides pseudo rtl for saturation and bit reversal to more accurately describe those functions that are referenced in the instruction pseudo rtl. 7.4 embedded vector and scalar si ngle-precision floating-point apus (spfp apus) this section describes the instruction set architecture of the embedded floating-point apus. the eis defines the following apus: embedded vector single-precision floating-point apu embedded scalar single-precision floating-point apu embedded scalar double-precision floating-point apu each of these apus may be implemented independently of the other. in addition, there is a strong relationship with the spe apu in that each of the embedded floating-point apus shares a common status register with the spe. 7.4.1 nomenclature and conventions several conventions regarding nomenclature are used in this document: the embedded vector single-precision floating-point apu operations are abbreviated as vector floating-point or vector spfp. the embedded scalar single-precision floating-point apu operations are abbreviated as scalar spfp. the embedded scalar double-precision floating-point apu operations are abbreviated as scalar dpfp. bits 0 to 31 of a 64-bit register are referenced as field 0, upper half, upper word, or high-word element of the register. bits 32?63 are referred to as field 1, lower half, or lower-word element of the register. each half is an element of a 64-bit gpr. mnemonics for vector floating-point instructions generally begin with the letters ? evf ? (embedded vector float). mnemonics for single-precision floating-point instructions generally begin with the letters ? efs ? (embedded floating single). references to ?floating-point? or ?embedded spfp? refer to both apus. 7.4.2 embedded floating-poi nt apus programming model the embedded floating-point apus use the gprs as source and destination operands; however, double precision and vector instruction require 64-bit gprs as described in embedded floating-point apus gpr implementations on page 836 .? auxiliary processing units (apus) RM0004 833/1176 embedded floating-point instructions the following sections show opcodes for the three embedded floating-point apus, as follows: opcodes for embedded vector floating-point instructions on page 833 ? opcodes for embedded scalar single-precision floating-point instructions on page 833 ? opcodes for embedded scalar double-precision floating-point instructions on page 834 ? opcodes for embedded vector floating-point instructions table 213 lists the embedded vector floating-point opcodes. opcodes for embedded scalar single- precision floating-point instructions table 214 lists the embedded scalar single-precision floating-point opcodes. table 213. embedded vector floating-point instruction opcodes instruction opcode bits comments 0?5 6?10 11?15 16?20 21?31 evfsabs 4 rd ra 00000 010 1000 0100 evfsadd 4 rd ra rb 010 1000 0000 evfscfsf 4 rd 00000 rb 010 1001 0011 evfscfsi 4 rd 00000 rb 010 1001 0001 evfscfuf 4 rd 00000 rb 010 1001 0010 evfscfui 4 rd 00000 rb 010 1001 0000 evfscmpeq 4 crfd 00 ra rb 010 1000 1110 evfscmpgt 4 crfd 00 ra rb 010 1000 1100 evfscmplt 4 crfd 00 ra rb 010 1000 1101 evfsctsf 4 rd 00000 rb 010 1001 0111 evfsctsi 4 rd 00000 rb 010 1001 0101 evfsctsiz 4 rd 00000 rb 010 1001 1010 evfsctuf 4 rd 00000 rb 010 1001 0110 evfsctui 4 rd 00000 rb 010 1001 0100 evfsctuiz 4 rd 00000 rb 010 1001 1000 evfsdiv 4 rd ra rb 010 1000 1001 evfsmul 4 rd ra rb 010 1000 1000 evfsnabs 4 rd ra 00000 010 1000 0101 evfsneg 4 rd ra 00000 010 1000 0110 evfssub 4 rd ra rb 010 1000 0001 ra - rb evfststeq 4 crfd 00 ra rb 010 1001 1110 evfststgt 4 crfd 00 ra rb 010 1001 1100 evfststlt 4 crfd 00 ra rb 010 1001 1101 RM0004 auxiliary processing units (apus) 834/1176 opcodes for embedded scalar double-precision floating-point instructions table 215 lists the embedded scalar double-precision floating-point opcodes. table 214. embedded scalar single-precision floating-point instruction opcodes instruction opcode bits comments 0?5 6?10 11?15 16?20 21?31 efsabs 4 rd ra 00000 010 1100 0100 efsadd 4 rd ra rb 010 1100 0000 efscfd 4 rd 00000 rb 010 1100 1111 efscfsf 4 rd 00000 rb 010 1101 0011 efscfsi 4 rd 00000 rb 010 1101 0001 efscfuf 4 rd 00000 rb 010 1101 0010 efscfui 4 rd 00000 rb 010 1101 0000 efscmpeq 4 crfd 00 ra rb 010 1100 1110 efscmpgt 4 crfd 00 ra rb 010 1100 1100 efscmplt 4 crfd 00 ra rb 010 1100 1101 efsctsf 4 rd 00000 rb 010 1101 0111 efsctsi 4 rd 00000 rb 010 1101 0101 efsctsiz 4 rd 00000 rb 010 1101 1010 efsctuf 4 rd 00000 rb 010 1101 0110 efsctui 4 rd 00000 rb 010 1101 0100 efsctuiz 4 rd 00000 rb 010 1101 1000 efsdiv 4 rd ra rb 010 1100 1001 efsmul 4 rd ra rb 010 1100 1000 efsnabs 4 rd ra 00000 010 1100 0101 efsneg 4 rd ra 00000 010 1100 0110 efssub 4 rd ra rb 010 1100 0001 ra - rb efststeq 4 crfd 00 ra rb 010 1101 1110 efststgt 4 crfd 00 ra rb 010 1101 1100 efststlt 4 crfd 00 ra rb 010 1101 1101 table 215. embedded scalar double-precision floating-point instruction opcodes instruction opcode bits comments 0?5 6?10 11?15 16?20 21?31 efdabs 4 rd ra 00000 010 1110 0100 efdadd 4 rd ra rb 010 1110 0000 efdcfs 4 rd 00000 rb 010 1110 1111 auxiliary processing units (apus) RM0004 835/1176 optional load/store instructions all embedded floating-point apus use gprs to hold and operate on floating-point values. the apus do not architect load and store instructions to move the data to and from memory, but instead rely on existing instructions in the architecture to perform this function. in the case where either the vector single-precision embedded floating-point apu or the scalar double-precision embedded floating-point apu is implemented on a 32-bit implementation, the gprs are required to be 64-bits long. because a 32-bit implementation contains no load or store instructions that operate on 64-bit data, new instructions are required to perform these actions. in this case (and for a 64-bit implementation), an implementation may implement the following load/store instructions from the spe apu. efdcfsf 4 rd 00000 rb 010 1111 0011 efdcfsi 4 rd 00000 rb 010 1111 0001 efdcfsid 4 rd 00000 rb 010 1110 0011 64-bit only efdcfuf 4 rd 00000 rb 010 1111 0010 efdcfui 4 rd 00000 rb 010 1111 0000 efdcfuid 4 rd 00000 rb 010 1110 0010 64-bit only efdcmpeq 4 crfd 00 ra rb 010 1110 1110 efdcmpgt 4 crfd 00 ra rb 010 1110 1100 efdcmplt 4 crfd 00 ra rb 010 1110 1101 efdctsf 4 rd 00000 rb 010 1111 0111 efdctsi 4 rd 00000 rb 010 1111 0101 efdctsidz 4 rd 00000 rb 010 1110 1011 64-bit only efdctsiz 4 rd 00000 rb 010 1111 1010 efdctuf 4 rd 00000 rb 010 1111 0110 efdctui 4 rd 00000 rb 010 1111 0100 efdctuidz 4 rd 00000 rb 010 1110 1010 64-bit only efdctuiz 4 rd 00000 rb 010 1111 1000 efddiv 4 rd ra rb 010 1110 1001 efdmul 4 rd ra rb 010 1110 1000 efdnabs 4 rd ra 00000 010 1110 0101 efdneg 4 rd ra 00000 010 1110 0110 efdsub 4 rd ra rb 010 1110 0001 ra - rb efdtsteq 4 crfd 00 ra rb 010 1111 1110 efdtstgt 4 crfd 00 ra rb 010 1111 1100 efdtstlt 4 crfd 00 ra rb 010 1111 1101 table 215. embedded scalar double-precision floating-point instruction opcodes instruction opcode bits comments 0?5 6?10 11?15 16?20 21?31 RM0004 auxiliary processing units (apus) 836/1176 for scalar double-precision: evldd ?vector load doubleword into doubleword evlddx ?vector load doubleword into doubleword indexed evstdd ?vector store doubleword of doubleword evstddx ?vector store doubleword of doubleword evmergehi ?vector merge high evmergelo ?vector merge low for vector single-precision, all of the vector load/store word and doubleword instructions, merge instructions, and word forms of splat instructions may be implemented. because the vector single-precision embedde d floating-point apu uses a significant set of the spe vector load/store/merge instructions, it is strongly recommended that the spe apu be present when implementing the vector single-precision embedded floating-point apu. floating-point conversion models each apu contains floating-point conversion to and from integer and fractional type instructions. the floating-point to and from non?floating-point conversion model pseudo rtl is provided in chapter 6.3.2: embedded floating-point conversion models on page 337 ,? as a group of functions that is called from the individual instruction pseudo-rtl descriptions included in the instru ction descriptions in chapter 6: instruction set on page 330 .? embedded floating-point registers the embedded floating- point apus share register resources with the spe apu, as described in the following sections. embedded floating-point apus gpr implementations embedded floating-point operations are performed in the gprs of the processor. the vector floating-point and double-precision floating-point require a gpr register file with thirty-two 64-bit registers. this is consistent with the spe ap u. thus, these can coexist with the spe apu. single-precision floating-point requires a gpr register file with thirty-two 32-bit or 64-bit registers. when implemented with a 64-bit register file on a 32-bit implementation, single- precision floating-point operations only use and modify bits 32?63 of the gpr. in this case, bits 0?31 of the gpr are left unchanged by a si ngle-precision floating-point operation. for 64-bit implementations, bits 0?31 are undefined after a single-precision floating-point operation. floating-point double-precision instructions operate on the entire 64 bits of the gprs where a floating-point data item consists of 64 bits. vector floating-point instructions operate on the entire 64 bits of the gprs as well, but contain two 32-bit data items that are operated on independently of each other in a simd fashion. the format of both data items is the same as a single-precision floating-point value. the data item contained in bits 0?31 is called the ?high word?. the data item contained in bits 32?63 is called the low word there are no record forms of embedded floating-point instructions. floating-point compare instructions treat nans, infinity and denorm as normalized numbers for the comparison calculation when default results are provided. auxiliary processing units (apus) RM0004 837/1176 signal processing embedded floating-point status a nd control register (spefscr) the embedded floating-point apus use the spefscr, which is described in chapter 2.14.1: signal processing, embedded floating-point status, control register (spefscr) on page 119 .? the spe apu also uses spefscr. status and cont rol bits are shared for vector floating-point operations, single-precision floating-point operations and spe vector operations. the spefscr is implem ented as spr number 512 and is read and written by mfspr and mtspr in both user and supervisor mode. vector floating-point instructions affect both the high- and low-element floating-point status flags (bits 34?39 and 50?55). scalar spfp instructions affect only the low-element flags and leave the high element flags undefined. embedded floating-point exception bit?esr[spe] esr[spe] is defined as the embe dded floating-point exception bi t. this bit is set whenever the processor takes an interrupt related to the execution of the embedded floating-point instructions. (note that the same bit is used for spe apu exceptions. thus, spe and embedded floating-point interrupts are indistinguishable in the esr.) embedded floating-point interrupts the following sections describe the embedded floating-point apu interrupts: spe/embedded floating-point unav ailable interrupt on page 837 ? embedded floating-point data interrupt on page 837 ? embedded floating-point round interrupt on page 838 ? spe/embedded floating-point unavailable interrupt the spe/embedded floating-point unavailable interrupt vector is used by the embedded scalar double-precision floating-point apu and the embedded vector single-precision floating-point apu. it is not used by the embedded scalar single-precision floating-point apu. the spe/embedded floating-point unavaila ble interrupt occurs when an embedded vector floating-point or an embedded scalar double-precision floating-point instruction is executed and bit 38 of the msr is not set. if the spe/embedded floa ting-point unavailable interrupt occurs, the processor suppresses execution of the instruction causing the exception. the srr0, srr1, msr, and esr registers are modified as follows: srr0 is set to the ea of the instruction causing the interrupt. srr1 is set to the contents of the msr at the time of the interrupt. msr bits ce, me, and de are unchanged. all other bits are cleared. esr[24] is set. all other esr bits are cleared. instruction execution resumes at address ivpr[0?47]||ivor32[48?59]||0b0000. this interrupt is also used by the spe apu in the same manner. it should be used by software to determine if the application is usin g the upper 32 bits of the gprs and thus is required to save and restore them on a context switch. embedded floating-point data interrupt the embedded floating-point data interrupt vector is used for enabled floating-point invalid operation/input error, underflow, overflow, and divide-by-zero exceptions (collectively called floating-point data exceptions). when one of these enabled exceptions occurs, the RM0004 auxiliary processing units (apus) 838/1176 processor suppresses execution of the instruction causing the exception. the srr0, srr1, msr, esr, and spefscr are modified as follows: srr0 is set to the ea of the instruction causing the interrupt. srr1 is set to the contents of the msr at the time of the interrupt. msr bits ce, me and de are unchanged. all other bits are cleared. esr[spe] is set. all other esr bits are cleared. one or more spefscr status bits are set to indicate the type of exception. the affected bits are finvh, finv, fdbzh, fdbz, fovfh, fovf, funfh, and funf. spefscr[fg,fgh, fx, fxh] are cleared. instruction execution resumes at address ivpr[0?47]||ivor32[48?59]||0b0000. embedded floating-point round interrupt the embedded floating-point round interrupt occurs if no other floating-point data interrupt is taken and one of the following conditions is met: spefscr[finxe] is set and the unrounded result of an oper ation is not exact spefscr[finxe] is set, an ov erflow occurs, and overflow exceptions are disabled (fovf or fovfh set with fovfe cleared) an underflow occurs and underflow exceptions are disabled (funf set with funfe cleared) the embedded floating-point round interrupt does not occur if an enabled embedded floating-point data interrupt occurs. if an implementation does not support infinity rounding modes and the rounding mode is set to be +infinity or ?infinity, an embedded floating-point round interrupt occurs after every floating-point instruction for which rounding might occur regardless of the value of finxe unless an embedded floating-point data interrupt also occurs and is taken. when the embedded floating-point round interrupt occurs, the unrounded (truncated) result of an inexact high or low element is placed in the target register. if only a single element is inexact, the other exact element is updated with the correctly rounded result, and the fg and fx bits corresponding to the other exact element are both zero. the fg and fx bits are provided so that an interrupt handler can round the result as it desires. fg (the guard bit) is the value of the bit immediately to the right of the least significant bit of the destination format mantissa from the infinitely precise intermediate calculation before rounding. fx (the sticky bit) is the value of the or of all bits to the right of the guard bit (fg) of the destination format mantissa from the infinitely precise intermediate calculation before rounding. the srr0, srr1, msr, esr, and spefscr are modified as follows: srr0 is set to the ea of the instruction following the instruction causing the interrupt. srr1 is set to the contents of the msr at the time of the interrupt. msr bits ce, me, and de are unchanged. all other bits are cleared. esr[spe] is set. all other esr bits are cleared. spefscr fgh, fg, fxh, and fx are set appropriately. spefs cr[finxs] is set. instruction execution resumes at address ivpr[0?47]||ivor32[48?59]||0b0000. auxiliary processing units (apus) RM0004 839/1176 interrupt priorities the following list shows the priority order in which spe and embe dded floating-point interrupts are taken (see interrupt priorities on page 831 ? ): 1. spe/embedded floating-poin t unavailable interrupt 2. spe vector alignment interrupt 3. embedded floating-point data interrupt 4. embedded floating-point round interrupt an embedded floating-point data interrupt is taken if either element of a vector or scalar floating-point operation generates an embedded floating-point data exception. an embedded floating-point round interrupt is taken if either element of a vector floating-point operation or a scalar floating-point operat ion generates an embedded floating-point round exception and no operation (both element for vector floating-point) generates an embedded floating-point data exception. 7.4.3 embedded floating- point apu operations this section describes embedded floating-point apu operational modes, data formats, underflow and overflow ha ndling, ieee 754 compliance, and conversion models. operational modes all embedded floating-point operations are governed by the setting of the mode bit in spefscr. the mode bit defines how floating-p oint results are comp uted and how floating- point exceptions are handled. mode 0 defines a real-time, default-results-oriented mode that saturates results. other modes are currently not defined. floating-point data formats single-precision floating-point data elements are 32 bits wide with 1 sign bit (s), 8 bits of biased exponent (exp) and 23 bits of fraction. in the ieee-754 specification, fl oating-point values ar e represented in a fo rmat consisting of three explicit fields (sign field, biased expon ent field, and fraction field) and an implicit hidden bit. figure 179. floating-point data formats fraction 0 exp 31 (or 32:63) 8 s 19 fraction 0 exp 63 11 s 112 hidden bit double-precision single-precision s?sign bit; 0 = positive; 1 = negative exp?biased exponent field fraction?fractional portion of number RM0004 auxiliary processing units (apus) 840/1176 for single-precision normalized numbers, the biased exponent value, e, lies in the range of 1 to 254 corresponding to an actual exponent value e in the range ?126 to +127. with the hidden bit implied to be 1 (for normalized numbers), the value of the number is interpreted as follows: where e is the unbiased exponent and 1.fraction is the mantissa (or significand) consisting of a leading 1 (the hidden bit) and a fractional part (fraction field). for the single-precision format, the maximum positive normalized number (pmax) is represented by the encoding 0x7f7f_ffff, which is approximately 3.4e+38 (2 128 ), and the minimum positive normalized value (pmin) is represented by the encoding 0x0080_0000, which is approximately 1.2e?38 (2 ?126 ). two specific values of the biased exponent are reserved (0 and 255 for single-precision) for encoding special values of +0, ?0, +infinity, ?infinity, and nans. zeros of both positive and negative sign are represented by a biased exponent value (e) of zero and a fraction that is zero. infinities of both positive and negative sign are represented by a maximum exponent field value (255 for single-precision) and a fraction that is zero. denormalized numbers of both positive and negative sign are represented by a biased exponent value of 0 and a non-zero fraction. for these numbers, the hidden bit is defined by the ieee 754 standard to be zero. this number type is not dire ctly supported in hardware. instead, either a software interrupt handler is invoked or a default value is defined. not-a-numbers (nans) are represented by a maximum exponent field value (255 for single- precision) and a fraction that is non-zero. overflow and underflow defining pmax to be the most positive normalized value (farthest from zero), pmin the smallest positive normalized value (closest to zero), nmax the most negative normalized value (farthest from zero) and nmin the smallest normalized negative value (closest to zero), an overflow is said to have occurred if the nume rically correct result of an instruction is such that r > pmax or r < nmax. additionally, an implementation may also signal overflow by comparing the exponents of the operands. in this case, the hardware examines both exponents ignoring the fractional values. if it is determined that the operation to be performed may overflow (ignoring the fractional values), an overflow may be said to occur. for addition and subtraction this can occur if the larger exponent of both operands is 254. for multiplication this can occur if the sum of the exponents of the operands less the bias is 254. thus: single-precision addition: if a exp >= 254 | b exp >= 254 then overflow double-precision addition: if a exp >= 2046 | b exp >= 2046 then overflow single-precision multiplication: if a exp + b exp - 127 >= 254 then overflow double-precision multiplication: if a exp + b exp - 1023 >= 2046 then overflow 1 ? () s 2 e 1.fraction () auxiliary processing units (apus) RM0004 841/1176 an underflow is said to have occurred if the numerically correct result of an instruction is such that 0 auxiliary processing units (apus) RM0004 843/1176 regardless of the value of finxe unless an embedded floating-point data interrupt also occurs and is taken. for absolute value, negate, negative absolute value operations, an implementation may choose to either simply perform the sign bit operation ignoring exceptions, or to compute the operation and handle exceptions and saturation where appropriate. the fgh and fxh bits of the spefscr are undef ined upon the comple tion of a scalar floating-point operation. an implementation may choose to zero them or leave them unchanged. an implementation may choose to only implement sticky bit setting by hardware for fdbzs and finxs allowing software to manage the other sticky bits. it is recommended that all future implementations implement all sticky bit setting in hardware. for 64-bit implementations, the upper 32 bits of the destination register are undefined when the result of a scalar floating-point operation is a 32-bit result. it is recommended that future 64-bit implementations produce 64-bit results for the results of 64-bit conversions to integer values. 7.5 machine check apu the machine check apu defines features for the machine check interrupt in addition to those defined by the powerpc architecture and the book e version of the powerpc architecture. the machine check apu includes an enhanced definition of the machine check interrupt type similar to the book e?defined critical interrupt. 7.5.1 machine check apu programming model the apu defines dedicated save and restore sprs, msrr0 and msrr1, so a machine check interrupt does not affect the csrr0, csrr1, or esr registers as defined by the book e architecture. the apu also defines a separate return from machine check interrupt instruction, rfmci , that restores context from msrr0 and msrr1 when the machine check interrupt handler completes. machine check apu register model the machine check apu defines different register for the machine check interrupt resources than the book e definition. these are as follows: machine-check save/restore register 0 (mcsrr0)?spr 570. holds the instruction where fetching begins after rfmci executes, typically at the end of the machine check interrupt handler. see machine check save/restore register 0 (mcsrr0) on page 87 .? machine-check save/restore register 1 (mcsrr1)?spr 571. holds the machine state copied to the msr when a machine check interrupt occurs. the mcsrr1 value is restored to the msr when rfmci executes, typically at the end of the machine check interrupt handler. see machine check save/restore register 1 (mcsrr1) on page 87 .? machine check syndrome register (mcsr)?spr 572. mcsr has fields that identify causes for a machine check interrupt along with an indication of whether the processor can recover from the machine check interrupt. see machine check syndrome register (mcsr) on page 88 .? RM0004 auxiliary processing units (apus) 844/1176 note, however, that the msr[me] bit, defined by the original powerpc architecture, is also used in book e and in the machine check apu to enable the machine check interrupt. machine check apu instruction model the return from machine ch eck interrupt instruction, rfmci , is context-synchronizing; it works its way to the final execute stage, updates architected registers, and redirects instruction flow. when rfmci executes, data is restored from mcsrr0 and mcsrr1. the rfi and rfci instructions do not affect mcsrr0 and mcsrr1. this instruction is described in chapter 3: instruction model on page 133 .? machine check interrupt the machine check apu is consistent with t he machine check exception as defined in book e with the following differences: machine check is no longer a critical in terrupt but uses mcsrr0 and mcsrr1 for saving the return address and the msr in case the machine check is recoverable. the return from machine check interrupt instruction ( rfmci ) is implemented to support the return to the address saved in mcsrr0. the machine check syndrome register, mcsr , is used (instead of esr) to log the cause of the machine check. 7.6 debug apu this section describes the inst ruction set architecture of software accessible debug related items for book e implementations (eis). the debug apu defines an additional interrupt class for debug interrupts. this allows the debug features to be used in the software that is providing service for critical class interrupts. this is accomplished by providing specific save and restore registers for debug interrupts and providing a new return from interrupt instruction (return from debug interrupt). the debug apu reassigns debug interrupts into its own interrupt class, adding a new set of registers used to save the machine context upon the occurrence of a debug interrupt, and adds a new instruction, return from debug interrupt ( rfdi ), to return from a debug interrupt and restore the machine state from the new set of registers. this apu redefines powerpc book e debug interrupt behavior. an implementation may choose to provide the debug apu and also provide a method to disable the debug apu, reverting to using the critical interrupt as defined in book e. if such a capability is provided, hid0[d apuen] should be implemented. 7.6.1 debug apu programming model the following sections described the debug apu?s extensions to the book e interrupt, register, and interrupt models. auxiliary processing units (apus) RM0004 845/1176 7.6.2 debug apu register model the debug interrupt defines the following registers: debug save/restore register 0 (dsrr0). when a debug interrupt is taken, dsrr0 is set to the current or next instruction address. when rfdi is executed, instruction execution continues at the address in dsrr0. debug save/restore register 1 (dsrr1), when a debug interrupt is taken, the contents of the msr are placed into dsrr1. when rfdi is executed, the contents of dsrr1 are placed into the msr. bits of dsrr1 that correspond to reserved bits in the msr are also reserved. this instruction is fully described in chapter 6: instruction set on page 330 .? the debug apu defines fields in the following book e?defined registers: debug status register (dbsr). new event fields, described in ta bl e 2 1 6 , have been added to dbsr to record critical interrupt taken events and critical interrupt return events. the debug control register 0 (dbcr0), the debug apu adds event enable bits to dbcr0, described in ta bl e 2 1 7 , to control critical interrupt taken events, and critical interrupt return events. table 216. eis-defined db sr field descriptions bits name description 57 cirpt critical interrupt taken debug event. a critical interrupt taken debug event occurs when dbcr0[cirpt] = 1 and a critical interrupt (any interrupt that uses the critical class, that is, uses csrr0 and csrr1) occurs. 0no critical interrupt taken debug event has occurred. 1a critical interrupt taken debug event occurred. 58 cret critical interrupt return debug event. a critical interrupt return debug event occurs when dbcr0[cret] = 1 and a return from critical interrupt (an rfci instruction is executed) occurs. 0no critical interrupt return debug event has occurred. 1a critical interrupt return debug event occurred. table 217. dbcr0 field descriptions bits name description 57 cirpt critical interrupt taken debug event. a critical interrupt taken debug event occurs when dbcr0[cirpt] = 1 and a critical interrupt (any interrupt that uses the critical class, that is, uses csrr0 and csrr1) occurs. 0 critical interrupt taken debug events are disabled. 1 critical interrupt taken debug events are enabled. 58 cret critical interrupt return debug event. a critical interrupt return debug event occurs when dbcr0[cret] = 1 and a return from critical interrupt (an rfci instruction is executed) occurs. 0 critical interrupt return debug events are disabled. 1 critical interrupt return debug events are enabled. RM0004 auxiliary processing units (apus) 846/1176 7.6.3 debug apu instruction model the debug apu defines the supervisor-level rfdi instruction to restore state after a debug interrupt. the contents of dsrr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address dsrr0[0?61]||0b00. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the va lue placed into srr0, csrr0, or dsrr0 by the interrupt processing mechanism is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in dsrr0 at the time of the execution of the rfdi ). this instruction is fully described in chapter 6 .? debug apu interrupt model a debug interrupt occurs when no higher priority exception exists, a debug exception is presented to the interrupt mechanism, and msr[de] = 1. the specific cause or causes of debug exceptions are unchanged from book e. dsrr0, dsrr1, msr, debug address register, and debug status register are updated as follows: debug save/restore register 0 (dsrr0) is set to an instruction address. dsrr0 is set to the ea of an instruction that was executing or just completed execution when the debug exception occurred. dsrr0 is set the same as csrr0 is defined to be set in book e on a debug interrupt. csrr0 is not changed as the result of a debug interrupt. debug save/restore register 1 (dsrr1) is set to the contents of the msr at the time of the interrupt. csrr1 is not changed as the result of a debug interrupt. msr[cm] is set to the value of msr[icm]. msr[icm] and msr[me] are unchanged and all other defined msr bits are cleared. the dbsr and the debug control registers (dbcr0?dbcr2) operate as described in book e with the addition of a critical interrupt taken debug event and a critical return debug event. instruction execution resumes at address ivpr[0?47]||ivor15[48?59]||0b0000. 7.7 alternate time base the alternate time base apu defines a time base counter similar to the time base defined in the powerpc architecture. it is intended to be used for measuring time in implementation defined intervals. it differs from the time base defined by the powerpc architecture in that it is not writable and always counts up, wrapping when the 64-bit count overflows. 7.7.1 programming model the alternate time base is simply a 64-bit counter that counts up at some implementation dependent rate. although not required, it is recommended that the rate be at the core clock frequency or as small a multiple of the frequency as practical by the implementation. consult the user documentation for devices that support this feature. the counter can be read by executing an mfspr instruction specifying the atb (or atbl) register, but cannot be written. in 32-bit mode, reading the atb (or atbl) register will place the lower 32 bits of the counter into the target register. in 64-bit mode all 64 bits of the counter are placed in the target register. a second spr register atbu, is defined that auxiliary processing units (apus) RM0004 847/1176 accesses only the upper 32 bits of the counter. thus the upper 32 bits of the counter may be read into a register by reading the atbu register regardless of computation mode. the alternate time base is analogous to the time base in the powerpc architecture except that it counts at a different frequency and is not writable. the effect of power savings mode or core frequency changes on counting in the alternate time base is implementation dependent. see the user document for details. implementation note: an implementation may choose to directly alias the alternate time base to the time base counter if the granularity of time base counting is acceptable. registers the programming model consists of two sprs, alternate time base lower and upper (atbl and atbu). alternate time base registers (atbl and atbu) the atbl and atbu registers are described in chapter 2.15: alternate time base registers (atbl and atbu) on page 123 .? the alternate time base counter (atb) is formed by concatenating the upper and lower alternate time base registers (atbu and atbl). atbl (spr 526) provides read-only access to the 64-bit alternate time base counter, which is incremented at an implementation-defined frequency. atb registers are accessible in both user and supervisor mode. like the tb implementation, the atbl register is an aliased name for atb. RM0004 storage-related apus 848/1176 8 storage-related apus this chapter describes the following apus that are defined as part of the eis storage architecture: chapter 8.1: cache line locking apu ? chapter 8.2: direct cache flush apu ? chapter 8.3: cache way partitioning apu ? 8.1 cache line locking apu the cache line locking apu defines instructions and methods for locking frequently used instructions and data into their cache lines. cache locking allows software to mark individual cache lines (blocks) as locked, instructing the cache to keep latency-sensitive data available for fast access. unlike normal cache lines, locked cache lines do not participate in the normal replacement policy. 8.1.1 programming model this section gives a general description of the instructions defined by the cache line locking apu. full descriptions are provided in chapter 6: instruction set on page 330 .? lock setting and clearing lines are locked into the cache by software using a series of touch and lock set instructions. the following instructions are provided to lock data items into the data and instruction cache: dcbtls ?data cache block touch and lock set dcbtstls ?data cache block touch for store and lock set icbtls ?instruction cache block touch and lock set the r a and r b operands to these instructions form a effective address identifying the line to be locked. the ct field indicates which cache in the cache hierarchy should be targeted. these instructions are similar to the dcbt , dcbtst , and icbt instructions, but locking instructions can not execute speculatively and may cause additional exceptions. for unified caches, both the instruction lock set and the data lock set target the same cache. similarly, lines are unlocked from the cache by software using a series of lock-clear instructions. the following instructions are provid ed to lock instructions into the instruction cache: dcblc ?data cache block lock clear icblc ?instruction cache block lock clear the r a and r b operands to these instructions form an ea identifying the line to be unlocked. the ct field indicates which cache in the cache hierarchy should be targeted. additionally, software may clear all the locks in the cache. for the primary cache, this is accomplished by setting the clfc (dcl fc, iclfc) bit in l1csr0 (l1csr1). storage-related apus RM0004 849/1176 cache lines can also be implicitly unlocked in the following ways: a locked line is invalidated if it is targeted by a dcbi , dcbf , or icbi instruction. a snoop hit on a locked line that requires the line to be invalidated. this can occur because the data the line contains has been modified external to the processor, or another processor has explicitly invalidated the line. the entire cache containing the locked line is flash invalidated. an implementation is not required to unlock lines if data is invalidated in the cache. although the data may be invalidated (and thus not in the cache), the line can remain locked and be filled from the memory subsystem when the next access occurs. this method of not clearing locks when the associated line is invalidated, is called persisten t locking. an implementation may choose to implement locks as persistent or not persistent; the preferred method is persistent. error conditions setting locks in the cache can fail for several reasons. an address specified with a lock set instruction that does not have the proper permission causes a data storage interrupt (dsi). cache locking addresses are always translated as data references, therefore icbtls instructions that fail to translate or fail permissions cause dtlb and dsi errors respectively. additionally, cache locking and clearing operations can fail due to restricted user mode access. see cache locking (user mode) exceptions on page 850 .? overlocking if no exceptions occur for the execution of an dcbtls , dcbtstls , or icbtls instruction an attempt is made to lock the corresponding line in the cache. if all of the available ways are already locked in the given cache set, the requested line is not locked. this is considered an overlocking situation and if the lock was targeted for the primary cache (ct = 0) then l1csr0[dclo] (or l1csr1[iclo] if icbtls ) is set appropriately. a processor may optionally allow victimizing a locked line in an over locking situation. if l1csr0[dcloa] (l1csr0[icloa] for the primary instruction cache,) is set, an overlocking condition causes the replacement of an existing locked line with the requested line. the selection of the line to replace in an overlocking situation is implementation dependent. the overlocking condition is still said to exist and is appropriatly re flected in the status bits for lock overflow. an attempt to lock a line that is present and valid in the cache does not cause an overlocking condition. a non?lock-setting cache-line f ill or line replacement request to a cache that has all ways locked for a given set does not cause a lock to be cleared. unable-to-lock conditions if no exceptions occur and no overlocking condition exists, an attempt to set a lock can fail if any of the following is true: the target address is marked cache-inhibited or the storage attributes of the address uses a coherency protocol th at does not support locking. the target cache is disabled or not present. the ct field specifies a value not supported by the implementation. any other implementation-specific error condition. RM0004 storage-related apus 850/1176 if an unable-to-lock condition occurs, the lock se t instruction is treated as a nop. if the lock targeted the data cache ( dcbtls , dcbtstls ), l1csr0[dcul] is set to indicate the unable-to- lock condition; if the lock ta rgeted the instruction cache ( icbtls ), l1csr1[icul] is set. l1csr0[dcul] or l1csr0[icul] is set regardle ss of the ct value in the lock-setting instruction. cache locking (user mode) exceptions setting and clearing cache locks can be restricted to supervisor mode only access. if set, msr[ucle] allows cache locking operations to be performed in user mode. if msr[ucle] = 0 and msr[pr] = 1 and execution of a cache lock or cache clear instruction occurs, a cache locking exception occurs. in this case the processor suppresses execution of the instruction causing the exception. a dsi interrupt is taken and srr0, srr1, msr, and esr are modified as follows: srr0 is set to the ea of the instruction causing the interrupt. srr1 is set to the contents of the msr at the time of the interrupt. msr[ce,me,de] are unchanged. all other bits are cleared. esr[dlk] is set if the instruction was a dcbtls , dcbtstls , or a dcblc . esr[ilk] is set if the instruction was a icbtls or a icblc . all other esr bits are cleared. instruction execution resumes at address ivpr[0?47]||ivor2[48?59]||0b0000. 8.2 direct cache flush apu 8.2.1 overview to assist in software flush of the l1 cache, the direct cache flush apu allows the programmer to flush and/or invalidate the cache by specifying the cache set and cache way. without such a feature, the programmer must either: know the virtual addresses of the lines that need to be flushed and issue dcbst or dcbf instructions to those addresses. flush the entire cache by causing all the lines to be replaced. this requires a virtual address range that is mapped as a contiguous physical address range, that the programmer knows and can manipulate the replacement policy of the cache, and the size and organization of the cache. with the direct cache flush apu the program needs only specify the way and set of the cache to flush. the direct cache flush apu available bit, l1cfg0[cfiswa], is set for implementations that contain the direct cache flush apu. 8.2.2 programming model to address a specific physical block of the cache, the l1 flush and invalidate control register 0 (l1finv0) is written with the cache set (l1finv0[cset]) and cache way (l1finv0[cway]) of the line that is to be flushed. l1finv0 is written using a mtspr instruction specifying the l1finv0 register. no tag match in the cache is required. an additional field, l1finv0[ccmd], is used to s pecify the type of flush to be performed on the line addressed by l1finv0[cway] and l1finv0[cset]. storage-related apus RM0004 851/1176 the available l1finv0[ccmd] encodings are described in table 33 on page 96 . only the l1 data cache (or unified cache) is manipulated by the direct cache flush apu. the l1 instruction cache or any other caches in the cache hierarchy are not explicitly targeted by this apu. register model the direct cache flush apu defined one register, the l1 flush and invalidate control register 0, described in chapter 2.11.5 on page 96 .? l1finv0 contains fields to provide the way and set selection of a cache line to flush and or invalidate. 8.3 cache way partitioning apu the cache way partitioning apu allows ways in a unified l1 cache to be configured to accept either data or instruct ion miss line-fill replacements. 8.3.1 programming model the cache way partitioning apu is comprised of bits in l1csr0 and l1cfg0, as follows: way instruction disable field (l1csr0[wid]) is a 4-bit field that that determines which of ways 0?3 are available for replacement by instruction miss line refills. the additional ways instruction disable bit (l1csr0[awid]) determines whether ways 4 and above are available for replacem ent by instruction miss line refills. way data disable field (l1csr0[wdd]) is a 4-bit field that that determines which of ways 0?3 are available for replacem ent by data miss line refills. the additional ways data disable bit (l1csr 0[awdd]) determines whether ways 4 and above are available for replacement by instruction miss line refills. see chapter 2.11.1: l1 cache control and status register 0 (l1csr0) on page 90 .? way access mode bit, l1csr0[wam], determ ines whether all ways are available for access or only ways partitioned for the specific type of access are used for a fetch or read operation. see chapter 2.11.1 on page 90 .? cache way partitioning apu available bi t, l1cfg0[cwpa], indicates whether the cache way partitioning apu is available. see chapter 2.11.3 on page 94 .? these fields are described in detail in chapter 2.11.3 on page 94 ,? and in chapter 2.11.1: l1 cache control and status register 0 (l1csr0) on page 90 .? 8.3.2 interaction with the cache locking apu note that the cache wa y partitioning apu can affect the cache line locking apu?s ability to control replacement of lines. if any cache line locking instruction ( icbtls , dcbtls , dcbtstls ) is allowed to execute and finds a matching line in the cache, the line?s lock bit is set regardless of the l1csr0[wid,awid,wdd,awdd] settings. in this case, no replacement has been made. however, for cache misses that occur while ex ecuting a cache line lock set instruction, the only candidate lines available for locking are those that correspond to ways of the cache that have not been disabled for the particular type of line locking instruction (controlled by wdd and awdd for dcbtls and dcbtstls , controlled by wid and awid for icbtls ). thus, an overlocking condition may result even though fewer than eight lines with the same index are locked.y RM0004 vle introduction 852/1176 9 vle introduction this body of this document describes the vle (variable length encoding) extension to the book e architecture. the vle extension offers more efficient binary representations of applications for the embedded processor spaces where code density plays a major role in affecting overall system cost, and to a somewhat lesser extent, performance. the intent of the vle extension is not to define an entirely different isa nor to supplant the powerpc isa; instead the vle extension can be viewed as a supplement that is can be applied to an application or to part of an application to improve code density. chapter 11: vle compatibilit y with the eis on page 856 ,? describes additional vle extensions to the eis. the major objectives of the vle extension are as follows: coexistence and consistency with the book e isa and general architecture maintain a common programming model and instruction operation model in the vle extension reduce overall code size by ~30% over existing powerpc text segments limit the increase in execution path length to under 10% for most important applications limit the increase in hardware complexity for implementations containing the vle extension 9.1 compatibility with powerpc book e vle provides an extension to book e. there are additional operations defined using an alternate instruction encoding to enable reduced code footprint. this alternate encoding set is selected on an instruction page basis. a single page attribute bit selects between standard book e instruction encodings and vle instructions for that page of memory. this attribute is an extension to the book e page attributes. pages can be freely intermixed, allowing for a mixture of both types of encodings. instruction encodings in pages marked as using the vle extension are either 16 or 32 bits long, and are aligned on 16-bit boundaries. because of this, all instruction pages marked as vle are required to use big-endian byte ordering. the programmer?s model uses the same register set with both instruction encodings, although certain registers are not accessible by vle instructions using the 16-bit formats and not all condition register (cr) fields are used by condition setting or conditional branch instructions executing from a vle instruction page. in addition, immediate fields and displacements differ in size and use, due to the more restrictive encodings imposed by vle instructions. the vle extension defines additional fields in registers defined by book e and the eis. these are described in chapter 11.2: vle extension processor and storage control extensions on page 856 .? other than the requirement of big-endian byte ordering for instruction pages and the additional page attribute to identify whether the instruction page corresponds to a vle section of code, vle complies with the memory model defined in book e and the book e implementation specifications (eis). likewise, the vle extension co mplies with the book e vle introduction RM0004 853/1176 and eis definitions of the exc eption and interrupt model, th e timer facilities, the debug facilities and the special-purpose registers (sprs). 9.2 instruction mnem onics and operands the description of each instruction includes the mnemonic and a formatted list of operands. vle instruction semantics are either identical or similar to book e instruction semantics. where the semantics, side-effects, and binary encodings are identical, book e mnemonics and formats are used. where the semantics are similar but the binary encodings differ, the book e mnemonic is typically preceded with an e_ . to distinguish similar instructions available in both 16- and 32-bit forms under vle and standard book e instructions, vle instructions encoded with 16 bits have an se_ prefix. those vle instructions encoded with 32 bits that have different binary encodings or semantics than the equivalent book e instruction have an e_ prefix. the following are examples: stw r s , d (r a ) // standard book e instruction e_stw r s , d (r a ) // 32-bit vle instruction se_stw r z , sd4 (r x ) // 16-bit vle instruction RM0004 vle storage addressing 854/1176 10 vle storage addressing a program references memory using the effective address (ea) computed by the processor when it executes a branch, storage access, storage control, or tlb management instruction, or when it fetches the next sequential instruction. 10.1 data memory addressing modes table 218 lists data memory addressing modes supported by the vle extension. 10.2 instruction memory addressing modes table 219 lists instruction memory addressing modes supported by the vle extension. table 218. data storage addressing modes mode name description base+16-bit displacement (32-bit instruction format) d-mode the 16-bit d field is sign-extended and added to the contents of the gpr designated by r a or to zero if r a = 0 to produce the ea. base+8-bit displacement (32-bit instruction format) d8-mode the 8-bit d8 field is sign-extended and added to the contents of the gpr designated by r a or to zero if r a = 0 to produce the ea. base+scaled 4-bit displacement (16-bit instruction format) sd4- mode the 4-bit sd4 field zero-extended, scaled (shifted left) according to the size of the operand, and added to the contents of the gpr designated by r x to produce the ea. (note that r x = 0 is not a special case). base+index (32-bit instruction format) x-mode the gpr contents designated by r b are added to the gpr contents designated by r a or to zero if r a = 0 to produce the ea. table 219. instruction storage addressing modes mode description i-form branch instructions (32- bit instruction format) the 24-bit bd24 field is concatenat ed on the right with 0b0, sign- extended, and then added to the ad dress of the branch instruction. taken b15-form branch instructions (32-bit instruction format) the 15-bit bd15 field is concatenat ed on the right with 0b0, sign- extended, and then added to the address of the branch instruction to form the ea of the next instruction. all branch instructions (16-bit instruction format) the 8-bit bd8 field is concatenat ed on the right with 0b0, sign- extended, and then added to the address of the branch instruction to form the ea of the next instruction. sequential instruction fetching (or non-taken branch instructions) the value 4 [2] is added to the addr ess of the current 32-bit [16-bit] instruction to form the ea of the next instruction. if the address of the current instruction is 0xffff_fff c [0xffff_fffe], the address of the next sequential instruction is undefined. vle storage addressing RM0004 855/1176 any branch instruction with lk = 1 (32-bit instruction format) the value 4 is added to the address of the current branch instruction and the result is placed into the lr. if the address of the current instruction is 0xffff_fffc, the result placed into the lr is undefined. branch se_bl. se_blrl. se_bctrl instructions (16-bit instruction format) the value 2 is added to the address of the current branch instruction and the result is placed into the lr. if the address of the current instruction is 0xffff_fffe, the result placed into the lr is undefined. table 219. instruction storage addressing modes (continued) mode description RM0004 vle compatibility with the eis 856/1176 11 vle compatibility with the eis the body of this document addresses the relationship between vle and book e. it does not explicitly address eis-defined features, such as the apus or the use of mas registers. however, the information in the previous chapters provides a model for how the vle extension is integrated with features defined by the layer of architecture defined by the eis. 11.1 overview the vle extension uses the same semantics as the book e architecture. due to the limited instruction encoding formats, vle instructions typically support reduced immediate fields and displacements, and not all book e operations are encoded in the vle extension. the basic philosophy is to capture all useful operations, with most frequent operations given priority. immediate fields and displacements are provided to cover the majority of ranges encountered in embedded control code. instructions are encoded in either a 16- or 32-bit format, and these may be freely intermixed. book e floating-point registers (fprs) are not accessible by vle instructions. vle instructions use book e gpr and spr re gisters with the fo llowing limitations: vle instructions using the 16-bit formats are limited to addressing gpr0?gpr7, and gpr24?gpr31 in most instructions. move instructions are provided to transfer register contents between these registers and gpr8?gpr23. vle instructions using the 16-bit fo rmats are limited to addressing cr0 vle instructions using the 32-bit form ats are limited to addressing cr0?cr3 vle instruction encodings are generally different than book e instructions, except that most book e instructions falling within book e major op code 31 are encoded id entically in 32-bit vle instructions and have identical semantics unless they affect or access a resource not supported by the vle extension. also, major opcode 4 is available to support additional apus using identical encodings for both book e and the vle extension. this allows an implementation of the vle extension to include additional apus, such as the cache-line locking, single-precision floating-point, and spe apus, and to use the exact encodings. because future compatib ility is desired, and to avoid conf usion with book e, register bit numbering remains the same as in book e. 11.2 vle extension processor and storage control extensions this section describes additional functionality and extensions to the eis to support the vle extension. 11.2.1 eis instruction extensions this section describes extensions to eis instructions to support vle operations. because instructions may reside on a half-word boundary, bit 62 is not masked by instructions that cause fetching from a register, such as the lr, ctr, or a save/restore register 0, that holds an instruction address: return from interrupt instructions, such as rfdi (defined as part of the debug apu) and rfmci (defined as part of the machine check apu) no longer mask bit 62 of the respective save/restore register 0. the destination address is x srr0[32?62] || 1?b0. vle compatibility with the eis RM0004 857/1176 11.2.2 book e instruction extensions this section describes the various extensions to book e instructions to support the vle extension: rfci , rfdi , and rfi no longer mask bit 62 of csrr0, dsrr0, or srr0. the destination address is x srr0[32?62] || 1?b0. bclr , bclrl , bcctr , and bcctrl no longer mask bit 62 of the lr or ctr. the destination address is [lr,ctr][32?62] || 1?b0. 11.2.3 eis mmu extensions the vle assumes that the mmu implementation complies with the more general mmu definition provided by book e and the more specific definition provided by the eis. this section describes the differences and extensions to the mmu necessary to support the vle extension. tlb entries each tlb entry is augmented with an additional page attribute bit, the vle bit. if set, vle indicates the corresponding page of memory is a vle page. tlb load on reset during reset, all tlb entries except entry 0 are invalidated. tlb entry 0 is loaded with the additional value shown in ta bl e 2 2 0 . note that implementations may provide a p_rst_vlemode input to supply the value of the vle field on reset. if not available, the default value should be 0, indicating a book e page vle attribute bit if set, the vle attribute bit indicates the corresponding page of memory is a vle page. the vle attribute is used only for instruction access and is ignored for data accesses. the vle bit may be set only for big-endian pages, otherwise a byte-ordering exception occurs on instruction fetches. mmu assist registers (mas n ) to support the vle extension, additional bits are defined in mas2 and mas4. these are described in the following sections. mas2 the mas2 register is shown below. the vle page attribute has been added as mas2[58]. if the vle extension is not present, this bit is always read as zero and writes are ignored. table 220. tlb entry 0 reset value field reset value comments vle p_rst_vlemode value book e mode, not vle if no p_rst_vlemode signal is available RM0004 vle compatibility with the eis 858/1176 mas2[vle] is defined in ta bl e 2 2 1 . mmu assist register 4 (mas4) when the vle extension is implemented, mas4[58] is defined as the vled field, which contains the default mas2[vle] value. if the vle extension is not present, this bit is always read as zero and writes are ignored. mas4 is shown below. mas4[vled]is described in ta b l e 2 2 2 . spr 626 access: user read/write 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 r epn ?vle wimge w reset00000000000000000000000000 0 00000 table 221. mas2 field descriptions bits name comments, or function when set 58 vle vle 0this page is a standard book e page 1this page is a vle page spr 628 access: user read/write 32 33 34 35 36 45 46 47 48 51 52 55 56 57 58 59 60 61 62 63 r ? tlbseld ? tidseld ? tsized ? vled wd id md gd ed w reset all zeros table 222. mas4 field descriptions bits name comments, or function when set 58 vled default vle value. defined by the eis. 0 this page is a standard book e page 1 this page is a vle page vle compatibility with the eis RM0004 859/1176 11.2.4 eis debug apu extensions the se_rfdi instruction is provided to supp ort the eis debug interrupt apu. rfdi rfdi return from debug interrupt se_rfdi msr dsrr1 nia dsrr0 32:62 || 0b0 the se_rfdi instruction is used to return from a debug class interrupt, or as a means of establishing a new context and synchroniz ing on that new context simultaneously. the contents of dsrr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address dsrr0[32?62]||0b0. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0 or csrr0 by the interrupt processing mechanism (see book e) is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in dsrr0 at the time of the execution of se_rfdi ). execution of this instruction is privileged and restricted to supervisor mode only. execution of this instructio n is context synchronizing. when the debug apu is disabled, this instru ction is treated as an illegal instruction. special registers altered: msr 0 15 0000000000001010 RM0004 vle instruction classes 860/1176 12 vle instruction classes this chapter lists instructions defined or supported by the vle extension. unless otherwise noted, instructions that are not prefixed with e_ or se_ have identical encodings and semantics as in book e or in the book e implementation standards (eis). full descriptions of these instructions are provided in the eref: programmers reference manual for st's book e processors. a complete list of supported in structions is provided in chapter 12.6 .? 12.1 processor control instructions this section lists processor control instructions that can be executed when a processor is in vle mode. these instructions are grouped as follows: chapter 12.1.1: system linkage instructions on page 860 ? chapter 12.1.2: processor control register manipulation instructions on page 860 ? chapter 12.1.3: instruction synchronization instruction on page 861 ? 12.1.1 system linkage instructions se_sc , se_rfi , se_rfci , and se_rfdi are system linkage instructions that enable the program to call upon the system to perform a service (that is, invoke a system call interrupt), and by which the system can return from performing a service or from processing an interrupt. table 223 lists system linkage instructions. 12.1.2 processor control register manipulation instructions in addition to the book e processor control register manipulation instructions, the vle extension provides 16-bit forms of instructions to move to/from the lr and ctr. table 224 lists the processor control register manipulation instructions. table 223. system linkage instruction set index mnemonic instruction reference se_sc system call page -954 se_rfci` return from critical interrupt page -949 se_rfdi return from debug interrupt page -859 se_rfi return from interrupt page -950 table 224. system register manipulation instruction set index mnemonic instruction reference se_mfctr r x move from count register page -938 mfdcr r d , dcrn move from device control register book e se_mflr r x move from link register page -939 mfmsr r d move from machine state register book e vle instruction classes RM0004 861/1176 12.1.3 instruction synch ronization instruction table 225 lists the vle-defined se_isync instruction. 12.2 branch operation instructions this section lists branch instructions that can be executed when a processor is in vle mode and the registers that support them. 12.2.1 registers for branch operations the registers that support branch operations are grouped as follows: chapter 2.5.1: condition register (cr) on page 61 ? chapter 2.5.2: link register (lr) on page 66 ? chapter 2.5.3: count register (ctr) on page 67 ? condition register (cr) the condition register (cr) is a 32-bit register. cr bits are numbered 32 (most-significant bit) to 63 (least-significant bit). the cr reflects the result of certain operations, and provides a mechanism for testing (and branching). the vle extension implements the entire cr, but some comparison operations and all branch in structions are limited to using cr0?cr3. the full book e condition register field and logical operations are provided however. mfspr r d , sprn move from special purpose register book e se_mtctr r x move to count register page -942 mtdcr dcrn,r s move to device control register book e se_mtlr r x move to link register page -943 mtmsr r s move to machine state register book e mtspr sprn,r s move to special purpose register book e wrtee r a write msr external enable book e wrteei e write msr external enable immediate book e table 224. system register manipulation instruction set index (continued) mnemonic instruction reference table 225. instruction synchronization instruction set index mnemonic instruction reference se_isync instruction synchronize page -929 access: user read/write 313029282726252423222120191817161514131211109876543210 r cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 w reset0 0 0 00 0 00000000000000000000000000 RM0004 vle instruction classes 862/1176 cr bits are grouped into eight 4-bit fields, cr0?cr7, which are set in one of the following ways. specified fields of the condition register can be set by a move to the cr from a gpr ( mtcrf ). a specified cr field can be set by a move to the cr from another cr field ( e_mcrf ). cr field 0 can be set as the implicit result of an integer instruction. a specified condition register field can be set as the result of an integer compare instruction. cr field 0 can be set as the result of an integer bit test instruction. instructions are provided to perform logical operations on individual cr bits and to test individual condition register bits (see book e). condition register settings for integer instructions for all integer word instructions in which the rc bit is defined and set, and for addic. , the first three bits of cr field 0 (cr[32?34]) are se t by signed comparison of bits 32?63 of the result to zero, and the fourth bit of cr field 0 (cr[35]) is copied from the final state of xer[so]. if (target_register) 32:63 < 0 then c 0b100 else if (target_register) 32:63 > 0 then c 0b010 else c 0b001 cr0 c || xer so if any portion of the result is undefined, the value placed into the first three bits of cr field 0 is undefined. the bits of cr field 0 are interpreted as shown in ta bl e 2 2 6 . condition register setting for compare instructions for compare instructions, a cr field specified by the cr d operand in for the e_cmph , e_cmphl , e_cmpi , and e_cmpli instructions, or cr0 for the e_cmp16i , e_cmph16i , e_cmphl16i , e_cmpl16i , se_cmp , se_cmph , se_cmphl , se_cmpi , and se_cmpli instructions, is set to reflect the result of the comparison. the cr field bits are interpreted as shown in ta bl e 2 2 7 . a complete description of how the bits are set is given in the instruction descriptions and chapter 12.4.5: integer compare and bit test instructions on page 872 .? table 226. cr0 encodings cr bit description 32 negative (lt). bit 32 of the result is equal to 1. 33 positive (gt). bit 32 of the result is equal to 0 and at least one of bits 33?63 of the result is non-zero. 34 zero (eq). bits 32?63 of the result are equal to 0. 35 summary overflow (so). this is a copy of the final state xer[so] at the completion of the instruction. vle instruction classes RM0004 863/1176 condition register setting for the bit test instruction the bit test immediate instruction, se_btsti , also sets cr field 0. see the instruction description and also chapter 12.4.5: integer compare and bit test instructions on page 872 .? link register (lr) vle instructions use the lr as defined in book e, although the vle extension defines a subset of all variants of book e conditional branches involving the lr, as shown in table 228 . count register vle instructions use the count register (ctr) as defined in book e, although the vle extension defines a subset of the variants of book e conditional branches involving the ctr, as shown in ta b l e 2 2 9 . table 227. condition register setting for compare instructions cr bit description 4 crd + 32 less than (lt) for signed-integer compare, gpr( r a or r x) < sci8 or si or gpr( r b or r y). for unsigned-integer compare, gpr( r a or r x) < u sci8 or ui or ui5 or gpr( r b or r y). 4 crd + 33 greater than (gt) for signed-integer compare, gpr( r a or r x) > sci8 or si or ui5 or gpr( r b or r y). for unsigned-integer compare, gpr( r a or r x) > u sci8 or ui or ui5 or gpr( r b or r y). 4 crd + 34 equal (eq) for integer compare, gpr( r a or r x) = sci8 or ui5 or si or ui or gpr( r b or r y). 4 crd + 35 summary overflow (so) for integer compare, this is a copy of the final state of xer[so] at the completion of the instruction. table 228. branch to link register instruction comparison book e vle subset instruction syntax instruction syntax branch conditional to link register branch conditional to link register & link bclr bo , bi bclrl bo , bi branch (absolute) to link register branch (absolute) to link register & link se_blr se_blrl branch conditional & link e_bcl bo , bi , bd branch conditional & link e_bcl bo32 , bi32 , bd15 branch (absolute) & link e_bl bd24 se_bl bd8 RM0004 vle instruction classes 864/1176 12.2.2 branch instructions the sequence of instruction execution can be changed by the branch instructions. because vle instructions must be aligned on half-word boundaries, the low-order bit of the generated branch target address is forced to 0 by the processor in performing the branch. the branch instructions compute the ea of the target in one of the following ways, as described in chapter 10.2: instruction memory addressing modes on page 854 .? 1. adding a displacement to the address of the branch instruction. 2. using the address contained in the lr (branch to link register [and link]). 3. using the address contained in the ctr (branch to count register [and link]). branching can be conditional or unconditional, and the return address can optionally be provided. if the return address is to be provided (lk = 1), the ea of the instruction following the branch instruction is placed into the lr after the branch target address has been computed: this is done whether or not the branch is taken. in branch conditional instructions, the bi32 or bi16 instruction field specifies the cr bit to be tested. for 32-bit instructions using bi32, cr[32?47] (corresponding to bits in cr0?cr3) may be specified. for 16-bit instructions using bi16, only cr[32?35] (bits within cr0) may be specified. in branch conditional instructions, the bo32 or bo16 field specifies the conditions under which the branch is taken and how the branch is affected by or affects the cr and ctr. note that vle instructions also have different encodings for the bo32 and bo16 fields than in book e?s bo field. if the bo32 field specifies that the ctr is to be decremented, ctr[32?63] are decremented. if bo[16,32] specifies a condition that must be true or false, that condition is obtained from the contents of cr[bi+32]. (note that cr bits are numbered 32? 63. bi refers to the bi field in the branch instruction encoding. for example, specifying bi = 2 refers to cr[34].) encodings for the bo32 field for the vle extension are shown in table 230 . the encoding for the bo16 field for the vle extension is shown in ta b l e 2 3 1 . table 229. branch to count register instruction comparison book e vle instruction syntax instruction syntax branch conditional to count register branch conditional to count register & link bcctr bo , bi bcctrl bo , bi branch (absolute) to count register branch (absolute) to count register & link se_bctr se_bctrl table 230. vle extension bo32 encodings bo32 description 00 branch if the condition is false. 01 branch if the condition is true. 10 decrement ctr[32?63] , then branch if the decremented ctr[32?63] 0. 11 decrement ctr[32?63], then branch if the decremented ctr[32?63] = 0. vle instruction classes RM0004 865/1176 the various branch instructions supported by the vle extension are shown in table 232 . 12.3 condition register instructions condition register instructions are provided to transfer values to/from various portions of the cr. the vle extension does not introduce any additional functionality beyond that defined in book e for cr operations, but does remap the cr-logical and mcrf instruction functionality into major opcode 31. these instructions operate identically to the book e instructions, but are encoded differently. table 233 lists condition regi ster instructions supported in vle mode. table 231. vle extension bo16 encodings bo16 description 0 branch if the condition is false. 1 branch if the condition is true. table 232. branch instruction set index mnemonic instruction reference e_b bd24 e_bl bd24 branch branch & link page -903 se_b bd8 se_bl bd8 branch branch & link page -903 e_bc bo32 , bi32 , bd15 se_bc bo16 , bi16 , bd8 e_bcl bo32 , bi32 , bd15 branch conditional branch conditional branch conditional & link page -904 se_bctr se_bctrl branch to count register branch to count register & link page -906 se_blr se_blrl branch to link register branch to link register & link page -908 RM0004 vle instruction classes 866/1176 12.4 integer instructions this section lists the integer instruct ions supported by the vle extension. 12.4.1 integer load instructions the integer load instructions compute the ea of the memory to be accessed as described in chapter 10.1: data memory addressing modes on page 854 .? the byte, half word, or word in memory addressed by ea is loaded into gpr( r d) or gpr( r z). the vle extension supports both big- and little-endian byte ordering for data accesses. some integer load instructions have an update form in which gpr( r a) is updated with the ea. for these forms, if r a 0 and r a r d, the ea is placed into gpr( r a) and the memory element (byte, half word, word, or double word) addressed by ea is loaded into gpr( r d). if r a = 0 or r a= r d, the instruction form is invalid. this is the same behavior as specified for load with update instructions in book e. basic integer load instructions are listed in ta bl e 2 3 4 . table 233. condition register instruction set index mnemonic instruction reference e_crand crb d ,crb a ,crb b condition register and page -920 e_crandc crb d ,crb a ,crb b condition register and with complement page -920 e_creqv crb d ,crb a ,crb b condition register equivalent page -920 e_crnand crb d ,crb a ,crb b condition register nand page -921 e_crnor crb d ,crb a ,crb b condition register nor page -922 e_cror crb d ,crb a ,crb b condition register or page -923 e_crorc crb d ,crb a ,crb b condition register or with complement page -923 e_crxor crb d ,crb a ,crb b condition register xor page -925 e_mcrf cr d ,cr s move condition register field page -936 mcrxr cr d move to condition register from integer exception register book e mfcr r d move from condition register book e mtcrf fxm ,r s move to condition register fields book e table 234. basic integer load instruction set index mnemonic instruction reference e_lbz r d , d (r a ) e_lbzu r d , d8 (r a ) se_lbz r z , sd4 (r x ) load byte and zero load byte and zero with update load byte and zero (16-bit form) page -930 lbzx r d ,r a ,r b lbzux r d ,r a ,r b load byte and zero indexed load byte and zero with update indexed book e vle instruction classes RM0004 867/1176 integer load byte-reversed instructions are listed in ta bl e 2 3 5 . the vle-defined integer load mult iple instruction is listed in table 236 . the vle-defined integer load and reserve instruction is listed in ta b l e 2 3 7 . 12.4.2 integer store instructions the integer store instructions compute the ea of the memory to be accessed as described in chapter 10.1: data memory addressing modes on page 854 .? the contents of gpr( r s) or gpr( r z) are stored into the byte, half word, or word in memory addressed by ea. the vle extension supports both big- and little-endian byte ordering for data accesses. e_lha r d , d (r a ) e_lhau r d , d8 (r a ) load halfword algebraic load halfword algebraic with update page -931 lhax r d ,r a ,r b lhaux r d ,r a ,r b load halfword algebraic indexed load halfword algebraic with update indexed book e e_lhz r d , d (r a ) e_lhzu r d , d8 (r a ) se_lhz r z , sd4 (r x ) load halfword and zero load halfword and zero with update load halfword and zero (16-bit form) page -932 lhzx r d ,r a ,r b lhzux r d ,r a ,r b load halfword and zero indexed load halfword and zero with update indexed book e e_lwz r d , d (r a ) e_lwzu r d , d8 (r a ) se_lwz r z , sd4 (r x ) load word and zero load word and zero with update load word and zero (16-bit form) page -935 lwzx r d ,r a ,r b lwzux r d ,r a ,r b load word and zero indexed load word and zero with update indexed book e table 235. integer load byte-reverse instruction set index mnemonic instruction reference lhbrx r d ,r a ,r b load halfword byte-reverse indexed book e lwbrx r d ,r a ,r b load word byte-reverse indexed book e table 236. integer load multiple instruction set index mnemonic instruction reference e_lmw r d , d8 (r a ) load multiple word page -934 table 237. integer load and reserve instruction set index mnemonic instruction reference lwarx r d ,r a ,r b load word and reserve indexed book e table 234. basic integer load instruction set index (continued) mnemonic instruction reference RM0004 vle instruction classes 868/1176 some integer store instructions have an update form, in which gpr( r a) is updated with the ea. for these forms, the following rules (from book e) apply. if r a 0, the ea is placed into gpr( r a). if r s = r a, the contents of gpr( r s) are copied to the target memory element and then ea is placed into gpr( r a). the basic integer store in structions are listed in ta b l e 2 3 8 . the integer store byte-reverse instructions are listed in ta b l e 2 3 9 . the integer store multiple instruction is listed in ta bl e 2 4 0 . the integer store conditional instruction is listed in ta bl e 2 4 1 . table 238. basic integer store instruction set index mnemonic instru ction reference e_stb r s , d (r a ) e_stbu r s , d8 (r a ) se_stb r z , sd4 (r x ) store byte store byte with update store byte (16-bit form) page -958 stbx r s ,r a ,r b stbux r s ,r a ,r b store byte indexed store byte with update indexed book e e_sth r s , d (r a ) e_sthu r s , d8 (r a ) se_sth r z , sd4 (r x ) store halfword store halfword with update store halfword (16-bit form) page -959 sthx r s ,r a ,r b sthux r s ,r a ,r b store halfword indexed store halfword with update indexed book e e_stw r s , d (r a ) e_stwu r s , d8 (r a ) se_stw r z , sd4 (r x ) store word store word with update store word (16-bit form) page -961 stwx r s ,r a ,r b stwux r s ,r a ,r b store word indexed store word with update indexed book e table 239. integer store byte-reverse instruction set index mnemonic instruction reference sthbrx r s ,r a ,r b store halfword byte-reverse indexed book e stwbrx r s ,r a ,r b store word byte-reverse indexed book e table 240. integer store multiple instruction set index mnemonic instruction reference e_stmw r s , d8 (r a ) store multiple word page -960 table 241. integer store conditional instruction set index mnemonic instruction reference stwcx. r s ,r a ,r b store word conditional indexed book e vle instruction classes RM0004 869/1176 12.4.3 integer arithmetic instructions the integer arithmetic instructions use the contents of the gprs as source operands, and place results into gprs, into status bits in the xer and into cr0. the integer arithmetic instructions treat source operands as signed, two?s complement integers unless the instru ction is explicitly identified as performing an unsigned operation. the e_add2i. instruction and the oim5-form instruction, se_subi. , set the first three bits of cr0 to characterize bits 32?63 of the result. these bits are set by signed comparison of bits 32?63 of the result to zero. e_addic [ . ] and e_subfic [ . ] always set ca to reflect the carry out of bit 32. the integer arithmetic in structions are listed in table 242 . table 242. integer arithmetic instruction set index mnemonic instruction reference add r d ,r a ,r b add. r d ,r a ,r b addo r d ,r a ,r b addo. r d ,r a ,r b add book e se_add r x ,r yadd page -897 addc r d ,r a ,r b addc. r d ,r a ,r b addco r d ,r a ,r b addco. r d ,r a ,r b add carrying book e adde r d ,r a ,r b adde. r d ,r a ,r b addeo r d ,r a ,r b addeo. r d ,r a ,r b add extended book e e_addi r d ,r a , sci8 e_addi. r d ,r a , sci8 e_add16i r d ,r a , si e_add2i. r d , si se_addi r x , oimm add immediate page -898 e_addic r d ,r a , sci8 e_addic. r d ,r a , sci8 add immediate carrying page -900 e_add2is r d , si add immediate shifted page -898 divw r d ,r a ,r b divw. r d ,r a ,r b divwo r d ,r a ,r b divwo. r d ,r a ,r b divide word book e divwu r d ,r a ,r b divwu. r d ,r a ,r b divwuo r d ,r a ,r b divwuo. r d ,r a ,r b divide word unsigned book e RM0004 vle instruction classes 870/1176 12.4.4 integer logical and move instructions logical instructions perform bit-parallel operations on 32-bit operands or move register or immediate values into registers. the move instructions move values into a gp from either another gpr, or an immediate value. the x-form logical instructions with rc = 1 and the sci8-form logical instructions with rc = 1 set the first three bits of cr field 0 as described in chapter 12.4.3: integer arithmetic instructions on page 869 .? the logical instructions do not change xer[so,ov,ca]. the integer logical inst ructions are listed in ta bl e 2 4 3 . mulhw r d ,r a ,r b mulhw. r d ,r a ,r b multiply high word book e mulhwu r d ,r a ,r b mulhwu. r d ,r a ,r b multiply high word unsigned book e e_mulli r d ,r a , sci8 e_mull2i r d , si multiply low immediate page -944 mullw r d ,r a ,r b mullw. r d ,r a ,r b mullwo r d ,r a ,r b mullwo. r d ,r a ,r b multiply low word book e se_mullw r x ,r y multiply low word page -945 neg r d ,r a se_neg r x neg. r d ,r a nego r d ,r a nego. r d ,r a negate page -946 se_sub r x ,r y subtract page -962 subf r d ,r a ,r b subf. r d ,r a ,r b subfo r d ,r a ,r b subfo. r d ,r a ,r b subtract from book e se_subf r x ,r y subtract from page -963 subfc r d ,r a ,r b subfc. r d ,r a ,r b subfco r d ,r a ,r b subfco. r d ,r a ,r b subtract from carrying book e e_subfic r d ,r a , sci8 e_subfic. r d ,r a , sci8 subtract from immediate carrying page -964 se_subi r x , oimm se_subi. r x , oimm subtract immediate page -965 table 242. integer arithmetic instruction set index (continued) mnemonic instruction reference vle instruction classes RM0004 871/1176 table 243. integer logical instruction set index mnemonic instruction reference and [ . ] r a ,r s ,r b se_and [ . ] r x ,r y and page -901 andc [ . ] r a ,r s ,r b se_andc r x ,r y and with complement page -901 e_andi [ . ] r a ,r s , sci8 se_andi r x , ui5 e_and2i. r d , ui and immediate page -901 e_and2is. r d , ui and immediate shifted page -901 se_bclri r x , ui5 bit clear page -905 se_bgeni r x , ui5 bit generate page -907 se_bmski r x , ui5 bit mask generate page -909 se_bseti r x , ui5 bit set page -910 cntlzw r a ,r s cntlzw. r a ,r s count leading zeros word book e eqv r a ,r s ,r b eqv. r a ,r s ,r b equivalent book e extsb r a ,r s extsb. r a ,r s se_extsb r x extend sign byte page -926 extsh r a ,r s extsh. r a ,r s se_extsh r x extend sign halfword page -926 se_extzb r x extend with zeros byte page -927 se_extzh r x extend with zeros halfword page -927 e_li r d , li20 se_li r x , ui7 load immediate page -933 e_lis r d , ui load immediate shifted page -933 se_mfar r x ,ar y move from alternate register page -937 se_mr r x ,r y move register page -940 se_mtar ar x ,r y move to alternate register page -941 nand r a ,r s ,r b nand. r a ,r s ,r b nand book e nor r a ,r s ,r b nor. r a ,r s ,r b nor book e or r a ,r s ,r b or. r a ,r s ,r b se_or r x ,r y or page -948 se_not r xnot page -947 RM0004 vle instruction classes 872/1176 12.4.5 integer compare and bit test instructions the integer compare instructions compare the contents of gpr(ra) with one of the following: the value of the sci8 field the zero-extended value of the ui field the zero-extended value of the ui5 field the sign-extended value of the si field the contents of gpr( r b) or gpr( r y). the following comparisons are signed: e_cmph , e_cmpi , e_cmp16i , e_cmph16i , se_cmp , se_cmph , and se_cmpi . the following comparisons are unsigned: e_cmphl , e_cmpli , e_cmphl16i , e_cmpl16i , se_cmpli , se_cmpl , and se_cmphl . when operands are treated as 32-bit signed quantities, gpr n [32] is the sign bit. when operands are treated as 16-bit signed quantities, gpr n [48] is the sign bit. for 32-bit implementations, the l field must be zero. compare instructions set one of the left-most three bits of the designated cr field and clears the other two. xer[so] is copied to bit 3 of the designated cr field. the cr field is set as shown in ta bl e 2 4 4 . the integer bit test instruction tests the bit specified by the ui5 instruction field and sets the cr0 field as shown in ta bl e 2 4 5 . orc r a ,r s ,r b orc. r a ,r s ,r b or with complement book e e_ori [ . ] r a ,r s , sci8 e_or2i r d , ui or immediate page -966 e_or2is r d , ui or immediate shifted page -966 xor r a ,r s ,r b xor. r a ,r s ,r b xor book e e_xori [ . ] r a ,r s , sci8 xor immediate page -966 table 243. integer logical instruction set index (continued) mnemonic instruction reference table 244. cr settings for compare instructions bit name description 0lt ( r a or r x) < sci8, si, ui5, or gpr( r b or r y) (signed comparison) ( r a or r x) < u sci8, ui, ui5 or gpr( r b or r y) (unsigned comparison) 1gt ( r a or r x) > sci8, si, ui5, or gpr( r b or r y) (signed comparison) ( r a or r x) > u sci8, ui, ui5 or gpr( r b or r y) (unsigned comparison) 2eq( r a or r x) = sci8, si, ui, ui5, or gpr( r b or r y) 3 so summary overflow from the xer vle instruction classes RM0004 873/1176 table 246 is an index for integer compare and bit test operations. 12.4.6 integer select instruction the isel instruction provides a means to select one of two registers and place the result in a destination register under the control of a predicate value supplied by a cr bit. the integer select inst ruction is listed in ta b l e 2 4 7 . 12.4.7 integer trap instructions trap instructions test for a specified set of conditions by comparing the contents of one gpr with a second gpr. if any of the conditions tested by a trap instruction are met, a trap table 245. cr settings for integer bit test instructions bit name description 0 lt always cleared 1gt rx ui5 == 1 2eq rx ui5 == 0 3 so summary overflow from the xer table 246. integer compare and bit test instruction set index mnemonic instruction reference se_btsti r x , ui5 bit test immediate page -911 cmp cr d , l ,r a ,r b se_cmp r x ,r y compare page -912 e_cmph cr d ,r a ,r b se_cmph r x ,r y compare halfword page -914 e_cmph16i r a , si16 compare halfword immediate page -914 e_cmphl cr d ,r a ,r b se_cmphl r x ,r y compare halfword logical page -916 e_cmphl16i r a , ui16 compare halfword logical immediate page -916 e_cmpi cr d ,r a , sci8 e_cmp16i r a , si16 se_cmpi r x , ui5 compare immediate page -912 cmpl cr d , l ,r a ,r b se_cmpl r x ,r y compare logical page -918 e_cmpli cr d ,r a , sci8 e_cmpl16i r a , ui16 se_cmpli r x , ui5 compare logical immediate page -918 table 247. integer select instruction set index mnemonic instruction reference isel r d ,r a ,r b ,cr b integer select eis RM0004 vle instruction classes 874/1176 exception type program interrupt is invoked. if none of the tested conditions are met, instruction execution continues normally. the contents of gpr( r a) are compared with the contents of gpr( r b). for twi and tw , only the contents of bits 32?63 of r a (and r b) participate in the comparison. this comparison results in five conditions that are anded with to. if the result is not 0, the trap exception type program interrupt is invoked. these conditions are as shown in table 248 . the integer trap inst ruction is listed in table 249 . 3 12.4.8 integer rotate and shift instructions instructions are provided that perform shifts and rotates on data from a gpr and return the result, or a portion of the result, to a gpr. the rotation operations rotate a 32-bit quantity left by a specified number of bit positions. bits that exit from position 32 enter at position 63. the rotate 32 operation is used to rotate a given 32-bit quantity. some rotate and shift instructions employ a mask generator. the mask is 32 bits long, and consists of 1 bits from a start bit, mstart , through and including a stop bit, mstop , and 0-bits elsewhere. the values of mstart and mstop range from 32 to 63. if mstart > mstop, the 1 bits wrap around from position 63 to position 0. thus the mask is formed as follows: if mstart mstop then mask mstart:mstop = ones mask all other bits = zeros else mask mstart:63 = ones mask 32:mstop = ones mask all other bits = zeros there is no way to specify an all-zero mask. table 248. integer trap conditions to bit anded with condition 0 less than, using signed comparison 1 greater than, using signed comparison 2 equal 3 less than, using unsigned comparison 4 greater than, using unsigned comparison table 249. integer trap instruction set index mnemonic instruction reference tw to ,r a ,r b trap word book e vle instruction classes RM0004 875/1176 for instructions that use the rotate 32 operation, the mask start and stop positions are always in bits 32?63 of the mask. the use of the mask is described in following sections. the rotate word and shift word instructions with rc = 1 set the first three bits of cr field 0 as described in book e. rotate and shift instructions do not change the ov and so bits. rotate and shift instructions, except algebraic right shifts, do not change the ca bit. the instructions in ta bl e 2 5 0 rotate the contents of a register. depending on the instruction type, the amount of the rotation is either specified as an immediate, or contained in a gpr. the instructions in ta bl e 2 5 1 rotate the contents of a register. depending on the instruction type, the result of the rotation is either inserted into the target register under control of a mask (if a mask bit is 1, the associated bit of the rotated data is placed into the target register; if a mask bit is 0, the associated bit in the target register remains unchanged) or anded with a mask before being placed into the target register. the rotate left instructions allow right-rotation of the contents of a register to be performed (in concept) by a left-rotation of 32- n , where n is the number of bits by which to rotate right. they allow right-rotation of the contents of bits 32?63 of a register to be performed (in concept) by a left-rotation of 32- n , where n is the number of bits by which to rotate right. the integer shift instructions ar e listed in RM0004 vle instruction classes 876/1176 12.5 storage control instructions this section lists storage control inst ructions, which include the following: chapter 12.5.1: storage synchronization instructions on page 876? chapter 12.5.2: cache management instructions on page 876? chapter 12.5.3: tlb management instructions on page 877 ? 12.5.1 storage synchronization instructions the memory synchronization instructions implemented by the vle extension are identical to those defined in book e. the storage synchronization instructions are listed in ta bl e 2 5 3 . 12.5.2 cache management instructions cache management instructions implemented by the vle extension are identical to those defined in book e. the cache management instructions are listed in ta b l e 2 5 4 . srw r a ,r s ,r b srw. r a ,r s ,r b se_srw r x ,r y shift right word page -957 e_srwi r a ,r s , sh se_srwi r x , ui5 shift right word immediate page -957 table 252. integer shift instruction set index (continued) mnemonic instruction reference table 253. storage synchronization instruction set index mnemonic instruction reference mbar memory barrier book e msync memory synchronize book e vle instruction classes RM0004 877/1176 12.5.3 tlb management instructions the tlb management instructions implemented by the vle extension are identical to those defined in book e and in the eis. the tlb management instructions are listed in ta b l e 2 5 5 . 12.5.4 instruction alig nment and byte ordering to be recognized by the instruction decoder, an instruction fetched from memory must be placed in the pipeline with its bytes in the proper order. book e allows instructions to be placed into memory marked as either big- or little-endian. this is manageable because book e instructions are always word-size aligned on word boundaries. vle instructions can be either half word or word size, and are aligned on half-word boundaries. because of this, only big-endian instruction memory is supported when executing from a page of vle instructions. attempts to execute vle instructions from a page marked as little-endian generate an instruction storage interrupt byte-ordering exception. 12.6 instruction listings this section lists instructions either defined or supported by the vle extension. table 256 lists instructions by instruction name. table 254. cache management instruction set index mnemonic instruction reference dcba r a ,r b data cache block allocate book e dcbf r a ,r b data cache block flush book e dcbi r a ,r b data cache block invalidate book e dcbst r a ,r b data cache block store book e dcbt ct ,r a ,r b data cache block touch book e dcbtls ct,ra,rb data cache block touch and lock set book e dcbtst ct ,r a ,r b data cache block touch for store book e dcbz r a ,r b data cache block set to zero book e icbi r a ,r b instruction cache block invalidate book e icbt ct ,r a ,r b instruction cache block touch book e table 255. tlb management instruction set index mnemonic instruction reference tlbivax r a ,r b tlb invalidate virtual address indexed book e tlbre tlb read entry book e tlbsx r a ,r b tlb search indexed book e tlbsync tlb synchronize book e tlbwe tlb write entry book e RM0004 vle instruction classes 878/1176 table 256. instructions listed by name instruction mnemonic reference add add r d ,r a ,r b add. r d ,r a ,r b addo r d ,r a ,r b addo. r d ,r a ,r b book e add carrying addc r d ,r a ,r b addc. r d ,r a ,r b addco r d ,r a ,r b addco. r d ,r a ,r b book e add extended adde r d ,r a ,r b adde. r d ,r a ,r b addeo r d ,r a ,r b addeo. r d ,r a ,r b book e and with complement andc [ . ] r a ,r s ,r b se_andc r x ,r y book e page -901 and and [ . ] r a ,r s ,r b se_and [ . ] r x ,r y book e page -901 compare cmp cr d , l ,r a ,r b se_cmp r x ,r y book e page -912 compare logical cmpl cr d , l ,r a ,r b se_cmpl r x ,r y book e page -918 count leading zeros word cntlzw r a ,r s cntlzw. r a ,r s book e data cache block allocate dcba r a ,r b book e data cache block flush dcbf r a ,r b book e data cache block invalidate dcbi r a ,r b book e data cache block store dcbst r a ,r b book e data cache block touch dcbt ct ,r a ,r b book e data cache block touch for store dcbtst ct ,r a ,r b book e data cache block set to zero dcbz r a ,r b book e divide word divw r d ,r a ,r b divw. r d ,r a ,r b divwo r d ,r a ,r b divwo. r d ,r a ,r b book e divide word unsigned divwu r d ,r a ,r b divwu. r d ,r a ,r b divwuo r d ,r a ,r b divwuo. r d ,r a ,r b book e equivalent eqv r a ,r s ,r b eqv. r a ,r s ,r b book e vle instruction classes RM0004 879/1176 extend sign byte extsb r a ,r s extsb. r a ,r s se_extsb r x book e book e page -926 extend sign halfword extsh r a ,r s extsh. r a ,r s se_extsh r x book e book e page -926 add immediate shifted e_add2is r d , si page -897 add immediate e_addi r d ,r a , sci8 e_addi. r d ,r a , sci8 e_add16i r d ,r a , si e_add2i. r d , si se_addi r x , oimm page -897 add immediate carrying e_addic r d ,r a , sci8 e_addic. r d ,r a , sci8 page -900 and immediate shifted e_and2is. r d , ui page -901 and immediate e_andi [ . ] r a ,r s , sci8 se_andi r x , ui5 e_and2i. r d , ui page -901 branch conditional branch conditional branch conditional & link e_bc bo32 , bi32 , bd15 se_bc bo16 , bi16 , bd8 e_bcl bo32 , bi32 , bd15 page -904 branch branch & link e_b bd24 e_bl bd24 page -903 compare halfword e_cmph cr d ,r a ,r b se_cmph r x ,r y page -914 compare halfword immediate e_cmph16i r a , si16 page -914 compare halfword logical e_cmphl cr d ,r a ,r b se_cmphl r x ,r y page -916 compare halfword logical immediate e_cmphl16i r a , ui16 page -916 compare immediate e_cmpi cr d ,r a , sci8 e_cmp16i r a , si16 se_cmpi r x , ui5 page -912 compare logical immediate e_cmpli cr d ,r a , sci8 e_cmpl16i r a , ui16 se_cmpli r x , ui5 page -918 condition register and e_crand crb d ,crb a ,crb b page -920 condition register and with complement e_crandc crb d ,crb a ,crb b page -920 condition register equivalent e_creqv crb d ,crb a ,crb b page -920 condition register nand e_crnand crb d ,crb a ,crb b page -921 condition register nor e_crnor crb d ,crb a ,crb b page -922 table 256. instructions listed by name (continued) instruction mnemonic reference RM0004 vle instruction classes 880/1176 condition register or e_cror crb d ,crb a ,crb b page -923 condition register or with complement e_crorc crb d ,crb a ,crb b page -924 condition register xor e_crxor crb d ,crb a ,crb b page -925 load byte and zero load byte and zero with update load byte and zero (16-bit form) e_lbz r d , d (r a ) e_lbzu r d , d8 (r a ) se_lbz r z , sd4 (r x ) page -930 load halfword algebraic load halfword algebraic with update e_lha r d , d (r a ) e_lhau r d , d8 (r a ) page -931 load halfword and zero load halfword and zero with update load halfword and zero (16-bit form) e_lhz r d , d (r a ) e_lhzu r d , d8 (r a ) se_lhz r z , sd4 (r x ) page -932 load immediate e_li r d , li20 se_li r x , ui7 page -933 load immediate shifted e_lis r d , ui page -933 load multiple word e_lmw r d , d8 (r a ) page -934 load word and zero load word and zero with update load word and zero (16-bit form) e_lwz r d , d (r a ) e_lwzu r d , d8 (r a ) se_lwz r z , sd4 (r x ) page -935 move condition register field e_mcrf cr d ,cr s page -936 multiply low immediate e_mulli r d ,r a , sci8 e_mull2i r d , si page -944 or immediate shifted e_or2is r d , ui page -948 or immediate e_ori [ . ] r a ,r s , sci8 e_or2i r d , ui page -948 rotate left word e_rlw r a ,r s ,r b page -951 rotate left word immediate e_rlwi r a ,r s , sh page -951 rotate left word immediate then mask insert e_rlwimi r a ,r s , sh , mb , me page -952 rotate left word immediate then and with mask e_rlwinm r a ,r s , sh , mb , me page -953 shift left word immediate e_slwi r a ,r s , sh se_slwi r x , ui5 page -955 shift right word immediate e_srwi r a ,r s , sh se_srwi r x , ui5 page -957 store byte store byte with update store byte (16-bit form) e_stb r s , d (r a ) e_stbu r s , d8 (r a ) se_stb r z , sd4 (r x ) page -958 table 256. instructions listed by name (continued) instruction mnemonic reference vle instruction classes RM0004 881/1176 store halfword store halfword with update store halfword (16-bit form) e_sth r s , d (r a ) e_sthu r s , d8 (r a ) se_sth r z , sd4 (r x ) page -959 store multiple word e_stmw r s , d8 (r a ) page -960 store word store word with update store word (16-bit form) e_stw r s , d (r a ) e_stwu r s , d8 (r a ) se_stw r z , sd4 (r x ) page -961 subtract from immediate carrying e_subfic r d ,r a , sci8 e_subfic. r d ,r a , sci8 page -964 xor immediate e_xori [ . ] r a ,r s , sci8 page -966 instruction cache block invalidate icbi r a ,r b book e instruction cache block touch icbt ct ,r a ,r b book e integer select isel r d ,r a ,r b ,cr b eis load byte and zero indexed load byte and zero with update indexed lbzx r d ,r a ,r b lbzux r d ,r a ,r b book e load halfword algebraic indexed load halfword algebraic with update indexed lhax r d ,r a ,r b lhaux r d ,r a ,r b book e load halfword byte-reverse indexed lhbrx r d ,r a ,r b book e load halfword and zero indexed load halfword and zero with update indexed lhzx r d ,r a ,r b lhzux r d ,r a ,r b book e load word and reserve indexed lwarx r d ,r a ,r b book e load word byte-reverse indexed lwbrx r d ,r a ,r b book e load word and zero indexed load word and zero with update indexed lwzx r d ,r a ,r b lwzux r d ,r a ,r b book e memory barrier mbar book e move to condition register from integer exception register mcrxr cr d book e move from condition register mfcr r d book e move from device control register mfdcr r d , dcrn book e move from machine state register mfmsr r d book e move from special purpose register mfspr r d , sprn book e memory synchronize msync book e move to condition register fields mtcrf fxm ,r s book e move to device control register mtdcr dcrn,r s book e move to machine state register mtmsr r s book e move to special purpose register mtspr sprn,r s book e table 256. instructions listed by name (continued) instruction mnemonic reference RM0004 vle instruction classes 882/1176 multiply high word mulhw r d ,r a ,r b mulhw. r d ,r a ,r b book e multiply high word unsigned mulhwu r d ,r a ,r b mulhwu. r d ,r a ,r b book e multiply low word mullw r d ,r a ,r b mullw. r d ,r a ,r b mullwo r d ,r a ,r b mullwo. r d ,r a ,r b book e nand nand r a ,r s ,r b nand. r a ,r s ,r b book e negate neg r d ,r a se_neg r x neg. r d ,r a nego r d ,r a nego. r d ,r a book e page -946 book e book e book e nor nor r a ,r s ,r b nor. r a ,r s ,r b book e or or r a ,r s ,r b or. r a ,r s ,r b se_or r x ,r y book e book e page -948 or with complement orc r a ,r s ,r b orc. r a ,r s ,r b book e add se_add r x ,r y page -897 bit clear se_bclri r x , ui5 page -905 branch to count register branch to count register & link se_bctr se_bctrl page -906 bit generate se_bgeni r x , ui5 page -907 branch to link register branch to link register & link se_blr se_blrl page -908 bit mask generate se_bmski r x , ui5 page -909 bit set se_bseti r x , ui5 page -910 branch branch & link se_b bd8 se_bl bd8 page -903 bit test immediate se_btsti r x , ui5 page -911 extend with zeros byte se_extzb r x page -927 extend with zeros halfword se_extzh r x page -927 instruction synchronize se_isync page -929 move from alternate register se_mfar r x ,ar y page -937 move from count register se_mfctr r x page -938 table 256. instructions listed by name (continued) instruction mnemonic reference vle instruction classes RM0004 883/1176 move from link register se_mflr r x page -939 move register se_mr r x ,r y page -940 move to alternate register se_mtar ar x ,r y page -941 move to count register se_mtctr r x page -942 move to link register se_mtlr r x page -943 multiply low word se_mullw r x ,r y page -945 not se_not r x page -947 subtract se_sub r x ,r y page -962 subtract from se_subf r x ,r y page -963 subtract immediate se_subi r x , oimm se_subi. r x , oimm page -965 shift left word slw r a ,r s ,r b slw. r a ,r s ,r b se_slw r x ,r y book e book e page -955 shift right algebraic word sraw r a ,r s ,r b sraw. r a ,r s ,r b se_sraw r x ,r y book e book e page -956 shift right algebraic word immediate srawi r a ,r s , sh srawi. r a ,r s , sh se_srawi r x , ui5 book e book e page -956 shift right word srw r a ,r s ,r b srw. r a ,r s ,r b se_srw r x ,r y book e book e page -957 store byte indexed store byte with update indexed stbx r s ,r a ,r b stbux r s ,r a ,r b book e store halfword byte-reverse indexed sthbrx r s ,r a ,r b book e store halfword indexed store halfword with update indexed sthx r s ,r a ,r b sthux r s ,r a ,r b book e store word byte-reverse indexed stwbrx r s ,r a ,r b book e store word conditional indexed stwcx. r s ,r a ,r b book e store word indexed store word with update indexed stwx r s ,r a ,r b stwux r s ,r a ,r b book e subtract from subf r d ,r a ,r b subf. r d ,r a ,r b subfo r d ,r a ,r b subfo. r d ,r a ,r b book e table 256. instructions listed by name (continued) instruction mnemonic reference RM0004 vle instruction classes 884/1176 table 257 lists instructions by mnemonic. subtract from carrying subfc r d ,r a ,r b subfc. r d ,r a ,r b subfco r d ,r a ,r b subfco. r d ,r a ,r b book e tlb invalidate virtual address indexed tlbivax r a ,r b book e tlb read entry tlbre book e tlb search indexed tlbsx r a ,r b book e tlb synchronize tlbsync book e tlb write entry tlbwe book e trap word tw to ,r a ,r b book e write msr external enable wrtee r a book e write msr external enable immediate wrteei e book e xor xor r a ,r s ,r b xor. r a ,r s ,r b book e table 257. instructions listed by mnemonic mnemonic instruction reference add r d ,r a ,r b add. r d ,r a ,r b addo r d ,r a ,r b addo. r d ,r a ,r b add book e addc r d ,r a ,r b addc. r d ,r a ,r b addco r d ,r a ,r b addco. r d ,r a ,r b add carrying book e adde r d ,r a ,r b adde. r d ,r a ,r b addeo r d ,r a ,r b addeo. r d ,r a ,r b add extended book e andc [ . ] r a ,r s ,r b and with complement book e and [ . ] r a ,r s ,r band book e cmp cr d , l ,r a ,r b compare book e cmpl cr d , l ,r a ,r b compare logical book e cntlzw r a ,r s cntlzw. r a ,r s count leading zeros word book e dcba r a ,r b data cache block allocate book e dcbf r a ,r b data cache block flush book e table 256. instructions listed by name (continued) instruction mnemonic reference vle instruction classes RM0004 885/1176 dcbi r a ,r b data cache block invalidate book e dcbst r a ,r b data cache block store book e dcbt ct ,r a ,r b data cache block touch book e dcbtst ct ,r a ,r b data cache block touch for store book e dcbz r a ,r b data cache block set to zero book e divw r d ,r a ,r b divw. r d ,r a ,r b divwo r d ,r a ,r b divwo. r d ,r a ,r b divide word book e divwu r d ,r a ,r b divwu. r d ,r a ,r b divwuo r d ,r a ,r b divwuo. r d ,r a ,r b divide word unsigned book e eqv r a ,r s ,r b eqv. r a ,r s ,r b equivalent book e extsb r a ,r s extsb. r a ,r s extend sign byte book e extsh r a ,r s extsh. r a ,r s extend sign halfword book e e_add2is r d , si add immediate shifted page -897 e_addi r d ,r a , sci8 e_addi. r d ,r a , sci8 e_add16i r d ,r a , si e_add2i. r d , si add immediate page -897 e_addic r d ,r a , sci8 e_addic. r d ,r a , sci8 add immediate carrying page -900 e_and2is. r d , ui and immediate shifted page -901 e_andi [ . ] r a ,r s , sci8 e_and2i. r d , ui and immediate page -901 e_bc bo32 , bi32 , bd15 e_bcl bo32 , bi32 , bd15 branch conditional branch conditional & link page -904 e_b bd24 e_bl bd24 branch branch & link page -903 e_cmph cr d ,r a ,r b compare halfword page -914 e_cmph16i r a , si16 compare halfword immediate page -914 e_cmphl cr d ,r a ,r b compare halfword logical page -916 e_cmphl16i r a , ui16 compare halfword logical immediate page -916 e_cmpi cr d ,r a , sci8 e_cmp16i r a , si16 compare immediate page -912 table 257. instructions listed by mnemonic (continued) mnemonic instruction reference RM0004 vle instruction classes 886/1176 e_cmpli cr d ,r a , sci8 e_cmpl16i r a , ui16 compare logical immediate page -918 e_crand crb d ,crb a ,crb b condition register and page -920 e_crandc crb d ,crb a ,crb b condition register and with complement page -920 e_creqv crb d ,crb a ,crb b condition register equivalent page -920 e_crnand crb d ,crb a ,crb b condition register nand page -921 e_crnor crb d ,crb a ,crb b condition register nor page -922 e_cror crb d ,crb a ,crb b condition register or page -923 e_crorc crb d ,crb a ,crb b condition register or with complement page -924 e_crxor crb d ,crb a ,crb b condition register xor page -925 e_lbz r d , d (r a ) e_lbzu r d , d8 (r a ) load byte and zero load byte and zero with update page -930 e_lha r d , d (r a ) e_lhau r d , d8 (r a ) load halfword algebraic load halfword algebraic with update page -931 e_lhz r d , d (r a ) e_lhzu r d , d8 (r a ) load halfword and zero load halfword and zero with update page -932 e_li r d , li20 load immediate page -933 e_lis r d , ui load immediate shifted page -933 e_lmw r d , d8 (r a ) load multiple word page -935 e_lwz r d , d (r a ) e_lwzu r d , d8 (r a ) load word and zero load word and zero with update page -936 e_mcrf cr d ,cr s move condition register field page -944 e_mulli r d ,r a , sci8 e_mull2i r d , si multiply low immediate page -948 e_or2is r d , ui or immediate shifted page -948 e_ori [ . ] r a ,r s , sci8 e_or2i r d , ui or immediate page -951 e_rlw r a ,r s ,r b rotate left word page -951 e_rlwi r a ,r s , sh rotate left word immediate page -952 e_rlwimi r a ,r s , sh , mb , me rotate left word immediate then mask insert page -953 e_rlwinm r a ,r s , sh , mb , me rotate left word immediate then and with mask page -955 e_slwi r a ,r s , sh shift left word immediate page -935 e_srwi r a ,r s , sh shift right word immediate book e e_stb r s , d (r a ) e_stbu r s , d8 (r a ) store byte store byte with update page -958 table 257. instructions listed by mnemonic (continued) mnemonic instruction reference vle instruction classes RM0004 887/1176 e_sth r s , d (r a ) e_sthu r s , d8 (r a ) store halfword store halfword with update page -959 e_stmw r s , d8 (r a ) store multiple word page -960 e_stw r s , d (r a ) e_stwu r s , d8 (r a ) store word store word with update page -961 e_subfic r d ,r a , sci8 e_subfic. r d ,r a , sci8 subtract from immediate carrying page -964 e_xori [ . ] r a ,r s , sci8 xor immediate page -966 icbi r a ,r b instruction cache block invalidate book e icbt ct ,r a ,r b instruction cache block touch book e isel r d ,r a ,r b ,cr b integer select eis lbzx r d ,r a ,r b lbzux r d ,r a ,r b load byte and zero indexed load byte and zero with update indexed book e lhax r d ,r a ,r b lhaux r d ,r a ,r b load halfword algebraic indexed load halfword algebraic with update indexed book e lhbrx r d ,r a ,r b load halfword byte-reverse indexed book e lhzx r d ,r a ,r b lhzux r d ,r a ,r b load halfword and zero indexed load halfword and zero with update indexed book e lwarx r d ,r a ,r b load word and reserve indexed book e lwbrx r d ,r a ,r b load word byte-reverse indexed book e lwzx r d ,r a ,r b lwzux r d ,r a ,r b load word and zero indexed load word and zero with update indexed book e mbar memory barrier book e mcrxr cr d move to condition register from integer exception register book e mfcr r d move from condition register book e mfdcr r d , dcrn move from device control register book e mfmsr r d move from machine state register book e mfspr r d , sprn move from special purpose register book e msync memory synchronize book e mtcrf fxm ,r s move to condition register fields book e mtdcr dcrn,r s move to device control register book e mtmsr r s move to machine state register book e mtspr sprn,r s move to special purpose register book e mulhw r d ,r a ,r b mulhw. r d ,r a ,r b multiply high word book e table 257. instructions listed by mnemonic (continued) mnemonic instruction reference RM0004 vle instruction classes 888/1176 mulhwu r d ,r a ,r b mulhwu. r d ,r a ,r b multiply high word unsigned book e mullw r d ,r a ,r b mullw. r d ,r a ,r b mullwo r d ,r a ,r b mullwo. r d ,r a ,r b multiply low word book e nand r a ,r s ,r b nand. r a ,r s ,r b nand book e neg r d ,r a neg. r d ,r a nego r d ,r a nego. r d ,r a negate book e nor r a ,r s ,r b nor. r a ,r s ,r b nor book e or r a ,r s ,r b or. r a ,r s ,r b or book e orc r a ,r s ,r b orc. r a ,r s ,r b or with complement book e se_add r x ,r yadd page -897 se_addi r x , oimm add immediate page -897 se_andc r x ,r y and with complement page -901 se_andi r x , ui5 and immediate page -901 se_and [ . ] r x ,r yand page -901 se_bc bo16 , bi16 , bd8 branch conditional page -904 se_bclri r x , ui5 bit clear page -905 se_bctr se_bctrl branch to count register branch to count register & link page -905 se_bgeni r x , ui5 bit generate page -906 se_blr se_blrl branch to link register branch to link register & link page -907 se_bmski r x , ui5 bit mask generate page -908 se_bseti r x , ui5 bit set page -909 se_b bd8 se_bl bd8 branch branch & link page -910 se_btsti r x , ui5 bit test immediate page -903 se_cmp r x ,r y compare page -912 se_cmph r x ,r y compare halfword page -914 se_cmphl r x ,r y compare halfword logical page -916 table 257. instructions listed by mnemonic (continued) mnemonic instruction reference vle instruction classes RM0004 889/1176 se_cmpi r x , ui5 compare immediate page -912 se_cmpl r x ,r y compare logical page -918 se_cmpli r x , ui5 compare logical immediate page -918 se_extsb r x extend sign byte page -926 se_extsh r x extend sign halfword page -926 se_extzb r x extend with zeros byte page -927 se_extzh r x extend with zeros halfword page -927 se_isync instruction synchronize page -929 se_lbz r z , sd4 (r x ) load byte and zero (16-bit form) page -930 se_lhz r z , sd4 (r x ) load halfword and zero (16-bit form) page -932 se_li r x , ui7 load immediate page -933 se_lwz r z , sd4 (r x ) load word and zero (16-bit form) page -935 se_mfar r x ,ar y move from alternate register page -937 se_mfctr r x move from count register page -938 se_mflr r x move from link register page -939 se_mr r x ,r y move register page -940 se_mtar ar x ,r y move to alternate register page -941 se_mtctr r x move to count register page -942 se_mtlr r x move to link register page -943 se_mullw r x ,r y multiply low word page -945 se_neg r x negate page -946 se_not r xnot page -947 se_or r x ,r yor page -948 se_slw r x ,r y shift left word page -955 se_slwi r x , ui5 shift left word immediate page -955 se_sraw r x ,r y shift right algebraic word page -956 se_srawi r x , ui5 shift right algebraic word immediate page -956 se_srw r x ,r y shift right word page -957 se_srwi r x , ui5 shift right word immediate page -957 se_stb r z , sd4 (r x ) store byte (16-bit form) page -958 se_sth r z , sd4 (r x ) store halfword (16-bit form) page -959 se_stw r z , sd4 (r x ) store word (16-bit form) page -961 se_sub r x ,r y subtract page -962 se_subf r x ,r y subtract from page -963 table 257. instructions listed by mnemonic (continued) mnemonic instruction reference RM0004 vle instruction classes 890/1176 se_subi r x , oimm se_subi. r x , oimm subtract immediate page -965 slw r a ,r s ,r b slw. r a ,r s ,r b shift left word book e sraw r a ,r s ,r b sraw. r a ,r s ,r b shift right algebraic word book e srawi r a ,r s , sh srawi. r a ,r s , sh shift right algebraic word immediate book e srw r a ,r s ,r b srw. r a ,r s ,r b shift right word book e stbx r s ,r a ,r b stbux r s ,r a ,r b store byte indexed store byte with update indexed book e sthbrx r s ,r a ,r b store halfword byte-reverse indexed book e sthx r s ,r a ,r b sthux r s ,r a ,r b store halfword indexed store halfword with update indexed book e stwbrx r s ,r a ,r b store word byte-reverse indexed book e stwcx. r s ,r a ,r b store word conditional indexed book e stwx r s ,r a ,r b stwux r s ,r a ,r b store word indexed store word with update indexed book e subf r d ,r a ,r b subf. r d ,r a ,r b subfo r d ,r a ,r b subfo. r d ,r a ,r b subtract from book e subfc r d ,r a ,r b subfc. r d ,r a ,r b subfco r d ,r a ,r b subfco. r d ,r a ,r b subtract from carrying book e tlbivax r a ,r b tlb invalidate virtual address indexed book e tlbre tlb read entry book e tlbsx r a ,r b tlb search indexed book e tlbsync tlb synchronize book e tlbwe tlb write entry book e tw to ,r a ,r btrap word book e wrtee r a write msr external enable book e wrteei e write msr external enable immediate book e xor r a ,r s ,r b xor. r a ,r s ,r b xor book e table 257. instructions listed by mnemonic (continued) mnemonic instruction reference vle instruction set RM0004 891/1176 13 vle instruction set the vle extension isa is defined in the instruction pages in this chapter. because of the various immediate field and displacement field calculations used in the vle extension, a description of the less obvious ones precedes the actual instruction pages, and the instruction descriptions generally assume the appropriate calculation has been performed. note: the instructions in this se ction are listed in order of the root instruction. for example, e_cmpi and se_cmpi are both listed under cmpi . 13.1 book e? and eis-defined instructions table 258 lists instructions that are used by the vle extension that are defined by book e or the eis. full descriptions of those instructions can be found in the eref. descriptions in this chapter indi cate any limitations on the behavior of vle instructions as compared to their book e and eis equivalents. table 258. book e? and eis-defined instructions listed by mnemonic mnemonic instruction defining architecture add r d ,r a ,r b add. r d ,r a ,r b addo r d ,r a ,r b addo. r d ,r a ,r b add book e addc r d ,r a ,r b addc. r d ,r a ,r b addco r d ,r a ,r b addco. r d ,r a ,r b add carrying book e adde r d ,r a ,r b adde. r d ,r a ,r b addeo r d ,r a ,r b addeo. r d ,r a ,r b add extended book e andc [ . ] r a ,r s ,r b and with complement book e and [ . ] r a ,r s ,r b and book e cmp cr d , l ,r a ,r b compare book e cmpl cr d , l ,r a ,r b compare logical book e cntlzw r a ,r s cntlzw. r a ,r s count leading zeros word book e dcba r a ,r b data cache block allocate book e dcbf r a ,r b data cache block flush book e dcbi r a ,r b data cache block invalidate book e dcbst r a ,r b data cache block store book e dcbt ct ,r a ,r b data cache block touch book e RM0004 vle instruction set 892/1176 dcbtls ct,ra,rb data cache block touch and lock set book e dcbtst ct ,r a ,r b data cache block touch for store book e dcbz r a ,r b data cache block set to zero book e divw r d ,r a ,r b divw. r d ,r a ,r b divwo r d ,r a ,r b divwo. r d ,r a ,r b divide word book e divwu r d ,r a ,r b divwu. r d ,r a ,r b divwuo r d ,r a ,r b divwuo. r d ,r a ,r b divide word unsigned book e eqv r a ,r s ,r b eqv. r a ,r s ,r b equivalent book e extsb r a ,r s extsb. r a ,r s extend sign byte book e extsh r a ,r s extsh. r a ,r s extend sign halfword book e e_srwi r a ,r s , sh shift right word immediate book e icbi r a ,r b instruction cache block invalidate book e icbt ct ,r a ,r b instruction cache block touch book e lbzx r d ,r a ,r b lbzux r d ,r a ,r b load byte and zero indexed load byte and zero with update indexed book e lhax r d ,r a ,r b lhaux r d ,r a ,r b load halfword algebraic indexed load halfword algebraic with update indexed book e lhbrx r d ,r a ,r b load halfword byte-reverse indexed book e lhzx r d ,r a ,r b lhzux r d ,r a ,r b load halfword and zero indexed load halfword and zero with update indexed book e lwarx r d ,r a ,r b load word and reserve indexed book e lwbrx r d ,r a ,r b load word byte-reverse indexed book e lwzx r d ,r a ,r b lwzux r d ,r a ,r b load word and zero indexed load word and zero with update indexed book e mbar memory barrier book e mcrxr cr d move to condition register from integer exception register book e mfcr r d move from condition register book e mfdcr r d , dcrn move from device control register book e mfmsr r d move from machine state register book e mfspr r d , sprn move from special purpose register book e table 258. book e? and eis-defined instructions listed by mnemonic (continued) mnemonic instruction defining architecture vle instruction set RM0004 893/1176 msync memory synchronize book e mtcrf fxm ,r s move to condition register fields book e mtdcr dcrn,r s move to device control register book e mtmsr r s move to machine state register book e mtspr sprn,r s move to special purpose register book e mulhw r d ,r a ,r b mulhw. r d ,r a ,r b multiply high word book e mulhwu r d ,r a ,r b mulhwu. r d ,r a ,r b multiply high word unsigned book e mullw r d ,r a ,r b mullw. r d ,r a ,r b mullwo r d ,r a ,r b mullwo. r d ,r a ,r b multiply low word book e nand r a ,r s ,r b nand. r a ,r s ,r b nand book e neg r d ,r a neg. r d ,r a nego r d ,r a nego. r d ,r a negate book e nor r a ,r s ,r b nor. r a ,r s ,r b nor book e or r a ,r s ,r b or. r a ,r s ,r b or book e orc r a ,r s ,r b orc. r a ,r s ,r b or with complement book e slw r a ,r s ,r b slw. r a ,r s ,r b shift left word book e sraw r a ,r s ,r b sraw. r a ,r s ,r b shift right algebraic word book e srawi r a ,r s , sh srawi. r a ,r s , sh shift right algebraic word immediate book e srw r a ,r s ,r b srw. r a ,r s ,r b shift right word book e stbx r s ,r a ,r b stbux r s ,r a ,r b store byte indexed store byte with update indexed book e sthbrx r s ,r a ,r b store halfword byte-reverse indexed book e sthx r s ,r a ,r b sthux r s ,r a ,r b store halfword indexed store halfword with update indexed book e table 258. book e? and eis-defined instructions listed by mnemonic (continued) mnemonic instruction defining architecture RM0004 vle instruction set 894/1176 stwbrx r s ,r a ,r b store word byte-reverse indexed book e stwcx. r s ,r a ,r b store word conditional indexed book e stwx r s ,r a ,r b stwux r s ,r a ,r b store word indexed store word with update indexed book e subf r d ,r a ,r b subf. r d ,r a ,r b subfo r d ,r a ,r b subfo. r d ,r a ,r b subtract from book e subfc r d ,r a ,r b subfc. r d ,r a ,r b subfco r d ,r a ,r b subfco. r d ,r a ,r b subtract from carrying book e tlbivax r a ,r b tlb invalidate virtual address indexed book e tlbre tlb read entry book e tlbsx r a ,r b tlb search indexed book e tlbsync tlb synchronize book e tlbwe tlb write entry book e tw to ,r a ,r b trap word book e wrtee r a write msr external enable book e wrteei e write msr external enable immediate book e xor r a ,r s ,r b xor. r a ,r s ,r b xor book e isel r d ,r a ,r b ,cr b integer select eis table 258. book e? and eis-defined instructions listed by mnemonic (continued) mnemonic instruction defining architecture vle instruction set RM0004 895/1176 13.2 immediate field and displacement field encodings table 259 shows encodings for immediate and displacement fields. table 259. immediate field and displacement field encodings encoding description bd15 format used by 32-bit branch conditional class in structions. the bd15 field is an 15-bit signed displacement which is sign-extended and shift ed left one bit (concatenat ed with 0b0) and then added to the current instruction address to form the branch target address. bd24 format used by 32-bit branch class instructions. th e bd24 field is an 24-bit signed displacement which is sign-extended and shifted left one bit (c oncatenated with 0b0) and then added to the current instruction address to form the branch target address. bd8 format used by 16-bit branch and branch conditional class instructions. the bd8 field is an 8-bit signed displacement which is sign-extended and shif ted left one bit (concatenated with 0b0) and then added to the current instruction addre ss to form the branch target address. d format used by some 32-bit load and store cla ss instructions. the d field is a 16-bit signed displacement which is sign-extended to 32 bits, and t hen added to the base register to form a 32-bit ea. d8 format used by some 32-bit load and store class instructions. the d8 field is a 8-bit signed displacement which is sign-extended to 32 bits, and t hen added to the base register to form a 32-bit ea. f, s c l , u i 8 (sci8 format) format used by some 32-bit arithmetic, compare, and logical instructions. the ui8 field is an 8-bit immediate value shifted left 0, 1, 2, or 3 byte po sitions according to the value of the scl field. the remaining bits in the 32-bit word are filled with the value of the f field, and the resulting 32-bit value is used as one operand of the instruction. more formally, if scl=0 then imm_value 24 f || ui8 else if scl=1 then imm_value 16 f || ui8 || 8 f else if scl=2 then imm_value 8 f || ui8 || 16 f else imm_value ui8 || 24 f li20 format used by 32-bit e_li instruction. the li20 field is a 20-bit signed displacement which is sign- extended to 32 bits for the e_li instruction. oim5 format used by the 16-bit se_addi , se_cmpli , and se_subi [ . ] instructions. the oim5 instruction field is a 5-bit value in the range 0?31 and is used to represent immediate values in the range 1?32, thus the binary encoding of 0b00000 represents an immediate val ue of 1, 0b00001 represents an immediate value of 2, and so on. in the instru ction descriptions, oimm represents the immediate value, not the oim5 instruction field binary encoding. sci8 format refer to f, scl,ui8 (sci8 format) sd4 format used by 16-bit load and store class instruct ions. the sd4 field is a 4-bit unsigned immediate value zero-extended to 32 bits, shifted left accordi ng to the size of the operation, and then added to the base register to form a 32-bit ea. for byte operations, no shift is performed. for half-word operations, the immediate is shifted left one bi t (concatenated with 0b0). for word operations, the immediate is shifted left two bits (concatenated with 0b00). for future double-word operations, the immediate is shifted left thr ee bits (concatenated with 0b000). si (d format, i16a format) format used by certain 32-bit arit hmetic type instructions. the si fi eld is a 16-bit signed immediate value sign-extended to 32 bits and used as one ope rand of the instruction. the instruction encoding differs between the d and i16a instruction formats RM0004 vle instruction set 896/1176 ui (i16a, i16l formats) format used by certain 32-bit logical and arithmetic type instructions. the ui field is a 16-bit unsigned immediate value zero-extended to 32 bits or padd ed with 16 zeros and used as one operand of the instruction. the instruction encoding differs between the i16a and i16l instruction formats. ui5 this format is used by some 16-bit reg+imm cl ass instructions. the ui5 field is a 5-bit unsigned immediate value zero-extended to 32 bits and used as the second operand of the instruction. for other 16-bit reg+imm class instructions, the ui5 fi eld is a 5-bit unsigned immediate value used to select a register bit in the range 0?31. ui7 this format is used by the 16-bit se_li instructions. the ui7 field is a 7-bit unsigned immediate value zero-extended to 32 bits and used as the operand of the instruction. table 259. immediate field and displacement field encodings (continued) encoding description vle instruction set RM0004 897/1176 _add x _add x add se_add r x ,r y sum 32:63 gpr(rx) + gpr(ry) gpr(rx) sum 32:63 the sum of the contents of gpr( r x) and the contents of gpr( r y) is placed into gpr( r x). special registers altered: none 056101115 000001 0 0 ry rx vle user RM0004 vle instruction set 898/1176 _addi x _addi x add [2 operand] immediate [shifted] [and record] e_add16i r d ,r a , si a gpr(ra) b exts(si) gpr(rd) a + b the sum of the contents of gpr( r a) and the sign-extended value of field si is placed into gpr( r d). special registers altered: none e_add2i. r a , si si si 0:4 || si 5:15 sum 32:63 gpr(ra) + exts(si) lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(ra) sum 32:63 the sum of the contents of gpr( r a) and the sign-extended value of si is placed into gpr( r a). special registers altered: cr0 e_add2is r a , si si si 0:4 || si 5:15 sum 32:63 gpr(rd) + (si || 16 0) gpr(ra) sum 32:63 the sum of the contents of gpr( r a) and the value of si concatenated with 16 zeros is placed into gpr( r a). special registers altered: none e_addi r d ,r a , sci8 (rc = 0) e_addi. r d ,r a , sci8 (rc = 1) vle user 05610111516 31 000111 rd ra si 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0001 si 5:15 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0010 si 5:15 0 5 6 1011 1516 2021222324 31 000110 rd ra 1000rcfscl ui8 vle instruction set RM0004 899/1176 imm sci8(f,scl,ui8) sum 32:63 gpr(ra) + imm if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rd) sum 32:63 the sum of the contents of gpr( r a) and the value of sci8 is placed into gpr( r d). special registers altered: cr0 (if rc = 1) se_addi r x , oimm gpr(rx) gpr(rx) + ( 27 0 || offset(oim5)) the sum of the contents of gpr( r x) and the zero-extended offset value of oim5 (a final value in the range 1?32), is placed into gpr( r x). special registers altered: none 0 5 6 7 11 12 15 0010000 oim5 (1) 1. oimm = oim5 +1 rx RM0004 vle instruction set 900/1176 _ addic x _addic x add immediate carrying [and record] e_addic r d ,r a , sci8 (rc = 0) e_addic. r d ,r a , sci8 (rc = 1) imm sci8(f,scl,ui8) carry 32:63 carry(gpr(ra) + imm) sum 32:63 gpr(ra) + imm if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rd) sum 32:63 ca carry 32 the sum of the contents of gpr( r a) and the value of sci8 is placed into gpr( r d). special registers altered: ca, cr0 (if rc=1) vle user 0 5 6 1011 1516 192021222324 31 000110 rd ra 1001rcfscl ui8 vle instruction set RM0004 901/1176 _ and x _and x and [2 operand] [immediate | with complement] [and record] se_and r x ,r y(rc=0) se_and. r x ,r y(rc=1) e_and2i. r d , ui e_and2is. r d , ui e_andi r a ,r s , sci8 (rc = 0) e_andi. r a ,r s , sci8 (rc = 1) se_andi r x , ui5 se_andc r x ,r y if ?e_andi[ . ]? then b sci8(f,scl,ui8) if ?se_andi? then b ui5 if ?se_and[ . ]? then b gpr(ry) if ?se_andc? then b ? gpr(ry) if ?e_and2i.? then b 16 0 || ui 0:4 || ui 5:15 if ?e_and2is.? then b ui 0:4 || ui 5:15 || 16 0 result 32:63 gpr(rs or rd or rx) & b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so if ?se_and[ci]? then gpr(rx) result 32:63 else gpr(ra or rd) result 32:63 for e_andi [ . ], the contents of gpr( r s) are anded with the value of sci8. for e_and2i. , the contents of gpr( r d) are anded with 16 0 || ui. for e_and2is. , the contents of gpr( r d) are anded with ui || 16 0. for se_andi , the contents of gpr( r x) are anded with the value of ui5. for se_and [ . ], the contents of gpr( r x) are anded with the contents of gpr( r y). 0 5678 1112 15 0100011rc ry rx vle user 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11001 ui 5:15 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11101 ui 5:15 0 5 6 1011 1516 2021222324 31 000110 rs ra 1100rcfscl ui8 0 5 6 7 11 12 15 0010111 ui5 rx 0 5678 1112 15 01000101 ry rx RM0004 vle instruction set 902/1176 for se_andc , the contents of gpr( r x) are anded with the one?s complement of the contents of gpr( r y). the result is placed into gpr( r a) or gpr( r x) ( se_and [ ic ][ . ]) special registers altered: cr0 (if rc = 1) vle instruction set RM0004 903/1176 _ b x _b x branch [and link] e_b bd24 (lk = 0) e_bl bd24 (lk = 1) a cia nia (a + exts(bd24||0b0)) 32:63 if lk=1 then lr cia + 4 let the btea be calculated as follows: for e_b [ l ], let btea be the sum of the cia and the sign-extended value of the bd24 instruction field concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia+4 is placed into the lr. special registers altered: lr (if lk = 1) se_b bd8 (lk = 0) se_bl bd8 (lk = 1) a cia nia (a + exts(bd8||0b0)) 32:63 if lk=1 then lr cia + 2 let the btea be calculated as follows: for se_b [ l ], let btea be the sum of the cia and the sign-extended value of the bd8 instruction field concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia+2 is placed into the lr. special registers altered: lr (if lk = 1) vle user 0 567 30 31 0111100 bd24 lk 0 5678 15 1110100lk bd8 RM0004 vle instruction set 904/1176 _ bc x _bc x branch conditional [and link] e_bc bo32 , bi32 , bd15 (lk = 0) e_bcl bo32 , bi32 , bd15 (lk = 1) if bo32 0 then ctr 32:63 ctr 32:63 ? 1 ctr_ok ? bo32 0 | ((ctr 32:63 0) bo32 1 ) cond_ok bo32 0 | (cr bi32+32 bo32 1 ) if ctr_ok & cond_ok then nia (cia + exts(bd15 || 0b0)) 32:63 else nia cia + 4 if lk=1 then lr cia + 4 let the btea be calculated as follows: for e_bc [ l ], let btea be the sum of the cia and the sign-extended value of the bd15 instruction field concatenated with 0b0. bo32 specifies any conditions that must be met for the branch to be taken, as defined in chapter 12.2.2: branch instructions on page 864 .? the sum bi32+32 specifies the cr bit. only cr[32?47] may be specified. if the branch conditions are met, the btea is the address of the next instruction to be executed. if lk = 1, the sum cia + 4 is placed into the lr. special registers altered: ctr (if bo32 0 =1) lr (if lk = 1) se_bc bo16,bi16,bd8 cond_ok (cr bi16+32 bo16) if cond_ok then nia (cia + exts(bd8 || 0b0)) 32:63 else nia cia + 2 let the btea be calculated as follows: for se_bc , btea is the sum of the cia and the sign-extended value of the bd8 instruction field concatenated with 0b0. bo16 specifies any conditions that must be met for the branch to be taken, as defined in chapter 12.2.2: branch instructions on page 864 .? the sum bi16+32 specifies cr bit; only cr[32?35] may be specified. if the branch conditions are met, the btea is the address of the next instruction to be executed. special registers altered: none vle user 0 5 6 9 10 11 12 15 16 30 31 011110 1 0 0 0 bo32 bi32 bd15 lk 0 4 5 678 15 11100bo16bi16 bd8 vle instruction set RM0004 905/1176 _ bclri _bclri bit clear immediate se_bclri r x,ui5 a ui5 b a 1 || 0 || 31- a 1 result 32:63 gpr(rx) & b gpr(rx) result 32:63 for se_bclri , the bit of gpr( r x) specified by the value of ui5 is cleared and all other bits in gpr( r x) remain unaffected. special registers altered: none 0 5 6 7 11 12 15 0110000 ui5 rx vle user RM0004 vle instruction set 906/1176 _ bctr x _bctr x branch to count register [and link] se_bctr (lk = 0) se_bctrl (lk = 1) nia ctr 32:62 || 0b0 if lk=1 then lr cia + 2 let the btea be calculated as follows: for se_bctr [ l ], let btea be bits 32?62 of the contents of the ctr concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia + 2 is placed into the lr. special registers altered: lr (if lk = 1) 01415 000000000000011lk vle user vle instruction set RM0004 907/1176 _ bgeni _bgeni bit generate immediate se_bgeni r x,ui5 a ui5 b a 0 || 1 || 31- a 0 gpr(rx) b for se_bgeni , a constant value consisting of a single ?1? bit surrounded by ?0?s is generated and the value is placed into gpr( r x). the position of the ?1? bit is specified by the ui5 field. special registers altered: none 0 5 6 7 11 12 15 0110001 ui5 rx vle user RM0004 vle instruction set 908/1176 _ blr x _blr x branch to link register [and link] se_blr (lk = 0) se_blrl (lk = 1) nia lr 32:62 || 0b0 if lk=1 then lr cia + 2 let the btea be calculated as follows: for se_blr [ l ], let btea be bits 32?62 of the contents of the lr concatenated with 0b0. the btea is the address of the next instruction to be executed. if lk = 1, the sum cia + 2 is placed into the lr. special registers altered: lr (if lk = 1) 01415 000000000000010lk vle user vle instruction set RM0004 909/1176 _ bmaski _bmaski bit mask generate immediate se_bmaski r x , ui5 a ui5 if a = 0 then b 32 1 else b 32-a 0 || a 1 gpr(rx) b for se_bmaski , a constant value consisting of a mask of low-order ?1? bits that is zero- extended to 32 bits is generated, and the value is placed into gpr( r x). the number of low- order ?1? bits is specified by the ui5 field. if ui5 is 0b00000, a value of all ?1?s is generated special registers altered: none 0 5 6 7 11 12 15 0010110 ui5 rx vle user RM0004 vle instruction set 910/1176 _ bseti _bseti bit set immediate se_bseti r x,ui5 a ui5 b a 0 || 1 || 31- a 0 result 32:63 gpr(rx) | b gpr(rx) result 32:63 for se_bseti , the bit of gpr( r x) specified by the value of ui5 is set, and all other bits in gpr( r x) remain unaffected. special registers altered: none 0 5 6 7 11 12 15 0110010 ui5 rx vle user vle instruction set RM0004 911/1176 _ btsti _btsti bit test immediate se_btsti r x , ui5 a ui5 b a 0 || 1 || 31- a 0 c gpr(rx) & b if c = 32 0 then d 0b001 else d 0b010 cr 0:3 d || xer so for se_btsti , the bit of gpr( r x) specified by the value of ui5 is tested for equality to ?1?. the result of the test is recorded in the cr. eq is set if the tested bit is clear, lt is cleared, and gt is set to the inverse value of eq. special registers altered: cr[0?3] 0 5 6 7 11 12 15 0110011 ui5 rx vle user RM0004 vle instruction set 912/1176 _ cmp _cmp compare [immediate] e_cmp16i r a , si e_cmpi cr d32 ,r a , sci8 a gpr(ra) 32:63 if ?e_cmpi? then b sci8(f,scl,ui8) if ?e_cmp16i? then b exts(si 0:4 || si 5:15 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 if ?e_cmpi? then cr 4 crd32+32:4 crd32+35 c || xer so // only cr0-cr3 if ?e_cmp16i? then cr 32:35 c || xer so // only cr0 if e_cmpi , gpr( r a) contents are compared with the value of sci8, treating operands as signed integers. if e_cmp16i , gpr( r a) contents are compared with the sign-extended value of the si field, treating operands as signed integers. the result of the comparison is placed into cr field cr d ( cr d32). for e_cmpi , only cr0? cr3 may be specified. for e_cmp16i , only cr0 may be specified. special registers altered: cr field cr d ( cr d32) (cr0 for e_cmp16i ) se_cmp r x ,r y se_cmpi r x , ui5 a gpr(rx) 32:63 if ?se_cmpi? then b 27 0 || ui5 if ?se_cmp? then b gpr(ry) 32:63 if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 0:3 c || xer so vle user 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0011 si 5:15 0 5 6 8 9 1011 1516 2021222324 31 0001100 00 crd32 ra 10101fscl ui8 0 5678 1112 15 00001100 ry rx 0 5 6 7 11 12 15 0010101 ui5 rx vle instruction set RM0004 913/1176 if se_cmp , the contents of gpr( r x) are compared with the contents of gpr( r y), treating the operands as signed integers. the result of the comparison is placed into cr field 0. if se_cmpi , the contents of gpr( r x) are compared with the value of the zero-extended ui5 field, treating the operands as signed integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] RM0004 vle instruction set 914/1176 _ cmph _cmph compare halfword [immediate] e_cmph cr d ,r a ,r b a exts(gpr(ra) 48:63 ) b exts(gpr(rb) 48:63 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 4 crd+32:4 crd+35 c || xer so for e_cmph , the contents of the low-order 16 bits of gpr( r a) and gpr( r b) are compared, treating the operands as signed integers. the result of the comparison is placed into cr field crd. special registers altered: cr field crd se_cmph r x ,r y a exts(gpr(rx) 48:63 ) b exts(gpr(ry) 48:63 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 0:3 c || xer so for se_cmph , the contents of the low-order 16 bits of gpr( r x) and gpr( r y) are compared, treating the operands as signed integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] e_cmph16i r a , si a exts(gpr(ra) 48:63 ) b exts(si 0:4 || si 5:15 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 32:35 c || xer so // only cr0 vle user 0 5 6 1011 1516 2021 3031 011111 crd / ra rb 0000001110 / 0 5678 1112 15 00001110 ry rx 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0110 si 5:15 vle instruction set RM0004 915/1176 the contents of the lower 16-bits of gpr( r a) are sign-extended and compared with the sign-extended value of the si field, treating the operands as signed integers. the result of the comparis on is placed into cr0. special registers altered: cr0 RM0004 vle instruction set 916/1176 _ cmphl __cmphl _ compare halfword logical [immediate] e_cmphl cr d ,r a ,r b a extz(gpr(ra) 48:63 ) b extz(gpr(rb) 48:63 ) if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 4 crd+32:4 crd+35 c || xer so for e_cmphl , the contents of the low-order 16 bits of gpr( r a) and gpr( r b) are compared, treating the operands as unsigned integers. the result of the comparison is placed into cr field crd. special registers altered: cr field crd se_cmphl r x ,r y a gpr(rx) 48:63 b gpr(ry) 48:63 if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 0:3 c || xer so for se_cmphl , the contents of the low-order 16 bits of gpr( r x) and gpr( r y) are compared, treating the operands as unsigned integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] e_cmphl16i r a , ui a 16 0 || gpr(ra) 48:63) b 16 0 || ui 0:4 || ui 5:15 if a < b then c 0b100 if a > b then c 0b010 if a = b then c 0b001 cr 32:35 c || xer so // only cr0 vle user 0 5 6 1011 1516 2021 3031 011111 crd / ra rb 0000101110 / 0 5678 1112 15 00001111 ry rx 0 5 6 1011 1516 2021 31 011100 ui 0:4 ra 1 0111 ui 5:15 vle instruction set RM0004 917/1176 the contents of the lower 16-bits of gpr( r a) are zero-extended and compared with the zero-extended value of the ui field, treating the operands as unsigned integers. the result of the comparis on is placed into cr0. special registers altered: cr0 RM0004 vle instruction set 918/1176 _ cmpl __cmpl _ compare logical [immediate] e_cmpl16i r a , ui e_cmpli cr d32 ,r a , sci8 a gpr(ra) 32:63 if ?e_cmpli? then b sci8(f,scl,ui8) if ?e_cmpl16i? then b 16 0 || ui 0:4 || ui 5:15 if a < u b then c 0b100 if a > u b then c 0b010 if a = b then c 0b001 if ?e_cmpli? then cr 4 crd32+32:4 crd32+35 c || xer so // only cr0-cr3 if ?e_cmp16i? then cr 32:35 c || xer so // only cr0 if e_cmpi , the contents of bits 32?63 of gpr( r a) are compared with the value of sci8, treating the operands as unsigned integers. l must be 0 for 32-bit implementations if e_cmpl16i , the contents of gpr( r a) are compared with the zero-extended value of the ui field, treating the operands as unsigned integers. the result of the comparison is placed into cr field crd (crd32). for e_cmpli , only cr0? cr3 may be specified. for e_cmpl16i , only cr0 may be specified. special registers altered: cr field crd (crd32) (cr0 for e_cmpl16i ) se_cmpl r x ,r y se_cmpli r x , oimm a gpr(rx) 32:63 if ?se_cmpli? then b 27 0 || offset(oim5) if ?se_cmpl? then b gpr(ry) 32:63 if a < u b then c 0b100 if a > u b then c 0b010 if a = b then c 0b001 vle user 0 5 6 1011 1516 2021 31 011100 ui 0:4 ra 1 0101 ui 5:15 0 5 6 8 9 1011 1516 2021222324 31 0001100 01 crd32 ra 10101fscl ui8 0 5678 1112 15 00001101 ry rx 0 5 6 7 11 12 15 0010001 oim5 (1) 1. oimm = oim5 +1 rx vle instruction set RM0004 919/1176 cr 0:3 c || xer so if se_cmpl , the contents of gpr( r x) are compared with the contents of gpr( r y), treating the operands as unsigned integers. the result of the comparison is placed into cr field 0. if se_cmpli , the contents of gpr( r x) are compared with the value of the zero-extended offset value of the oim5 field (a final value in the range 1?32), treating the operands as unsigned integers. the result of the comparison is placed into cr field 0. special registers altered: cr[0?3] RM0004 vle instruction set 920/1176 _ crand __crand _ condition register and e_crand crb d ,crb a ,crb b cr bt+32 cr ba+32 & cr bb+32 the content of bit crba+32 of the cr is anded with the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr condition register and with complement e_crandc crb d ,crb a ,crb b cr bt+32 cr ba+32 & ? cr bb+32 the content of bit crba+32 of the cr is anded with the one?s complement of the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr cr equivalent e_creqv crb d ,crb a ,crb b cr bt+32 cr ba+32 cr bb+32 the content of bit crba+32 of the cr is xored with the content of bit crbb+32 of the cr, and the one?s complement of result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0100000001 / 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0010000001 / 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0100100001 / vle instruction set RM0004 921/1176 _ crnand __crnand _ condition re gister nand e_crnand crb d ,crb a ,crb b cr bt+32 ? (cr ba+32 & cr bb+32 ) the content of bit crba+32 of the cr is anded with the content of bit crbb+32 of the cr, and the one?s complement of the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0011100001 / RM0004 vle instruction set 922/1176 _ crnor _ crnor condition re gister nor e_crnor crb d ,crb a ,crb b cr bt+32 ? (cr ba+32 | cr bb+32 ) the content of bit crba+32 of the cr is ored with the content of bit crbb+32 of the cr, and the one?s complement of the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0000100001 / vle instruction set RM0004 923/1176 _ cror _cror condition register or e_cror crb d ,crb a ,crb b cr bt+32 cr ba+32 | cr bb+32 the content of bit crba+32 of the cr is ored with the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0111000001 / RM0004 vle instruction set 924/1176 _ cror __cror _ condition register or with complement e_crorc crb d ,crb a ,crb b cr bt+32 cr ba+32 | ? cr bb+32 the content of bit crba+32 of the cr is ored with the one?s complement of the content of bit crbb+32 of the cr, and the result is placed into bit crbd +32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0110100001 / vle instruction set RM0004 925/1176 _ crxor __crxor _ condition re gister xor e_crxor crb d ,crb a ,crb b cr crbd+32 cr ba+32 cr bb+32 the content of bit crba+32 of the cr is xored with the content of bit crbb+32 of the cr, and the result is placed into bit crbd+32 of the cr. special registers altered: cr vle user 0 5 6 1011 1516 2021 3031 011111 crbd crba crbb 0011000001 / RM0004 vle instruction set 926/1176 _ extsb x _extsb x extend sign (byte | halfword) se_extsb r x se_extsh0. r x if se_extsb then n 56 if se_extsh then n 48 if ?extsw? then n 32 if rc=1 then do lt gpr(rs) n:63 < 0 gt gpr(rs) n:63 > 0 eq gpr(rs) n:63 = 0 cr0 lt || gt || eq || so s gpr(rs or rx) n gpr(ra or rx) n-32 s || gpr(rs or rx) n:63 for se_extsb , the contents of bits 56?63 of gpr( r x) are placed into bits 56?63 of gpr( r x). bit 56 of the contents of gpr( r x) is copied into bits 32?55 of gpr( r x). for se_extsh , the contents of bits 48?63 of gpr( r x) are placed into bits 48?63 of gpr( r x). bit 48 of the contents of gpr( r x) is copied into bits 32?47 of gpr( r x). special registers altered: cr0 (if rc=1) 056111215 000000001101 rx 056111215 000000001111 rx vle user vle instruction set RM0004 927/1176 _ extz x extz x extend zero (byte | halfword) se_extzb r x se_extzh r x if ?se_extzb? then n 56 if ?se_extzh? then n 48 gpr(rx) n-32 0 || gpr(rx) n:63 for se_extzb , the contents of bits 56?63 of gpr( r x) are placed into bits 56?63 of gpr( r x). bits 32?55 of gpr( r x) are cleared. for se_extzh , the contents of bits 48?63 of gpr( r x) are placed into bits 48?63 of gpr( r x). bits 32?47 of gpr( r x) are cleared. special registers altered: none 056111215 000000001100 rx 056111215 000000001110 rx vle user RM0004 vle instruction set 928/1176 _ illegal _illegal illegal se_illegal srr1 msr srr0 cia nia ivpr 32:47 || ivor6 48:59 || 0b0000 msr we,ee,pr,is,ds,fp,fe0,fe1 0b0000_0000 se_illegal is used to request an illegal instruct ion exception. a program interrupt is generated. the contents of the msr are copied into srr1 and the address of the se_illegal instruction is placed into srr0. msr[we,ee,pr,is,ds,fp,fe0,fe1] are cleared. the interrupt causes the next instruction to be fetched from address ivpr[32? 47]||ivor6[48?59]||0b0000 this instruction is context synchronizing. special registers altered: srr0 sr r1 msr[we,ee,pr,is,ds,fp,fe0,fe1] 015 0000000000000000 vle user vle instruction set RM0004 929/1176 _ isync _isync instruction synchronize se_isync the se_isync instruction provides an ordering function for the effects of all instructions executed by the processor executing the se_isync instruction. executing an se_isync instruction ensures that all instructions preceding the se_isync instruction have completed before the se_isync instruction completes, and that no subsequent instructions are initiated until after the se_isync instruction completes. it also causes any prefetched instructions to be discarded, with the effect that subsequent instructions are fetched and executed in the context established by the instructions preceding the se_isync instruction. the se_isync instruction may complete before memory accesses associated with instructions preceding the se_isync instruction have been performed. this instruction is context synchronizing (see book e). it has identical semantics to book e isync , just a different encoding. special registers altered: none 015 0000000000000001 vle user RM0004 vle instruction set 930/1176 _ lbz x _lbz x load byte and zero [with update] [indexed] e_lbz r d , d (r a ) (d-mode) se_lbz r z , sd4 (r x ) (sd4-mode) e_lbzu r d , d8 (r a ) (d8-mode) if (ra=0 & !se_lbz) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 28 0 || sd4)) 32:63 gpr(rd or rz) 24 0 || mem(ea,1) if e_lbzu then gpr(ra) ea let the ea be calculated as follows: for e_lbz and e_lbzu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_lbz , let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field. the byte in memory addressed by ea is loaded into bits 56?63 of gpr( r d or r z). bits 32?55 of gpr( r d or r z) are cleared. if e_lbzu , ea is placed into gpr( r a). if e_lbzu and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 05610111516 31 001100 rd ra d 03478111215 1 0 0 0 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rd ra 00000000 d8 vle instruction set RM0004 931/1176 _ lha x _lha x load halfword algebraic [with update] [indexed] e_lha r d , d (r a ) (d-mode) e_lhau r d , d8 (r a ) (d8-mode) if ra=0 then a 32 0 else a gpr(ra) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 gpr(rd) exts(mem(ea,2)) 32:63 if e_lhau then gpr(ra) ea let the ea be calculated as follows: for e_lha and e_lhau , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. the half word in memory addressed by ea is loaded into bits 48?63 of gpr( r d). bits 32?47 of gpr( r d) are filled with a copy of bi t 0 of the loaded half word. if e_lhau , ea is placed into gpr( r a). if e_lhau and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 05610111516 31 001110 rd ra d 0 5 6 1011 1516 2324 31 000110 rd ra 00000011 d8 RM0004 vle instruction set 932/1176 _ lhz x _lhz x load halfword and zero [with update] [indexed] e_lhz r d , d (r a ) (d-mode) se_lhz r z , sd4 (r x ) (sd4-mode) e_lhzu r d , d8 (r a ) (d8-mode) if (ra=0 & !se_lhz) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 27 0 || sd4 || 0)) 32:63 gpr(rd or rz) 16 0 || mem(ea,2) if e_lhzu then gpr(ra) ea let the ea be calculated as follows: for e_lhz and e_lhzu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_lhz let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 1 bit. the half word in memory addressed by ea is loaded into bits 48?63 of gpr( r d). bits 32?47 of gpr( r d) are cleared. if e_lhzu , ea is placed into gpr( r a). if e_lhzu and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 05610111516 31 010110 rd ra d 03478111215 1 0 1 0 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rd ra 00000001 d8 vle instruction set RM0004 933/1176 _ li x _li x load immediate [shifted] e_li r d , li20 (li20-mode) li20 li20 0:3 || li20 4:8 || li20 9:19 gpr(rd) exts(li20) for e_li , the sign-extended li20 field is placed into gpr( r d). special registers altered: none e_lis r d , ui ui ui 0:4 || ui 5:15 gpr(rd) ui || 16 0 for e_lis , the ui field is concatenated on the right with 16 0?s and placed into gpr( r d). special registers altered: none se_li r x , ui7 gpr(rx) 25 0 || ui7 for se_li , the zero-extended ui7 field is placed into gpr( r x). special registers altered: none vle user 0 5 6 1011 151617 2021 31 011100 rd li20 4:8 0li20 0:3 li20 9:19 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11100 ui 5:15 045 111215 01001 ui7 rx RM0004 vle instruction set 934/1176 _ lmw _lmw load multiple word e_lmw r d , d8 (r a ) if ra=0 then ea exts(d8) 32:63 else ea (gpr(ra)+exts(d8)) 32:63 r rd do while r 31 gpr(r) mem(ea,4) r r + 1 ea (ea+4) 32:63 let the ea be the sum of the contents of gpr( r a), or 32 0s if r a = 0, and the sign-extended value of the d8 instruction field. let n = (32-rd). n consecutive words starting at ea are loaded into bits 32?63 of registers gpr( r d) through gpr(31). ea must be a multiple of 4. if it is not, either an alignment interrupt is invoked or the results are boundedly undefined. if r a is in the range of registers to be loaded, including the case in which r a = 0, the instruction form is invalid. special registers altered: none vle user 0 5 6 1011 1516 2324 31 000110 rd ra 0 0 0 0 1 0 0 0 d8 vle instruction set RM0004 935/1176 _ lwz _lwz load word and zero [with update] [indexed] e_lwz r d , d (r a ) (d-mode) se_lwz r z , sd4 (r x ) (sd4-mode) e_lwzu r d , d8 (r a ) (d8-mode) if (ra=0 & !se_lwz) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 26 0 || sd4 || 2 0)) 32:63 gpr(rd or rz) mem(ea,4) if e_lwzu then gpr(ra) ea let the ea be calculated as follows: for e_lwz and e_lwzu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_lwz let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 2 bits. the word in memory addressed by the ea is loaded into bits 32?63 of gpr( r d). if e_lwzu , ea is placed into gpr( r a). if e_lwzu and r a = 0 or r a= r d, the instruction form is invalid. special registers altered: none vle user 05610111516 31 010100 rd ra d 03478111215 1 1 0 0 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rd ra 00000010 d8 RM0004 vle instruction set 936/1176 _ mcrf _mcrf move cr field e_mcrf cr d , cr s cr 4xcrd+32:4xcrd+35 cr 4xcrs+32:4xcrs+35 the contents of field cr s (bits 4 crs+32 through 4 crs+35) of the cr are copied to field cr d (bits 4 crd+32 through 4 crd+35) of the cr. special registers altered: cr vle user 0 5 6 8 9 1011 1314 2021 3031 011111 crd // crs /// 0000010000 / vle instruction set RM0004 937/1176 _ mfar _mfar move from alternate register se_mfar r x ,ar y gpr(rx) gpr(ary) for se_mfar , the contents of gpr( ar y) are placed into gpr( r x). ar y specifies a gpr in the range r8?r23. the encoding 0000 specifies r8, 0001 specifies r9,?, 1111 specifies r23. special registers altered: none 0 5678 1112 15 00000011 ary rx vle user RM0004 vle instruction set 938/1176 _ mfctr _mfctr move from count register se_mfctr r x gpr(rx) ctr the ctr contents are placed into bits 32?63 of gpr( r x). special registers altered: none 056111215 000000 0 0 1 0 1 0 rx vle user vle instruction set RM0004 939/1176 _ mflr _mflr move from link register se_mflr r x gpr(rx) lr the lr contents are placed into bits 32?63 of gpr( r x). special registers altered: none 056111215 000000 0 0 1 0 0 0 rx vle user RM0004 vle instruction set 940/1176 _ mr _mr move register se_mr r x ,r y gpr(rx) gpr(ry) for se_mr , the contents of gpr( r y) are placed into gpr( r x). special registers altered: none 0 5678 1112 15 00000001 ry rx vle user vle instruction set RM0004 941/1176 _ mtar _mtar move to alternate register se_mtar ar x ,r y gpr(arx) gpr(ry) for se_mtar , the contents of gpr( r y) are placed into gpr( ar x). ar x specifies a gpr in the range r8?r23. the encoding 0000 specifies r8, 0001 specifies r9,?, 1111 specifies r23. special registers altered: none 0 5678 1112 15 00000010 ry arx vle user RM0004 vle instruction set 942/1176 _ mtctr _mtctr move to count register se_mtctr r x ctr gpr(rx) the contents of bits 32?63 of gpr( r x) are placed into the ctr. special registers altered: ctr 056111215 000000 0 0 1 0 1 1 rx vle user vle instruction set RM0004 943/1176 _ mtlr _mtlr move to link register se_mtlr r x lr gpr(rx) the contents of bits 32?63 of gpr( r x) are placed into the lr. special registers altered: lr 056111215 000000 0 0 1 0 0 1 rx vle user RM0004 vle instruction set 944/1176 _ mulli x _mulli x multiply low [2 operand] immediate e_mulli r d ,r a , sci8 imm sci8(f,scl,ui8) prod 0:63 gpr(ra) imm gpr(rd) prod 32:63 bits 32?63 of the 64-bit product of the contents of gpr( r a) and the value of sci8 are placed into gpr( r d). both operands and the product are interpreted as signed integers. special registers altered: none e_mull2i r a , si prod 0:63 gpr(ra) exts(si 0:4 || si 5:15 ) gpr(ra) prod 32:63 bits 32?63 of the 64-bit product of the contents of gpr( r a) and the sign-extended value of the si field are placed into gpr( r a). both operands and the product are interpreted as signed integers. special registers altered: none vle user 0 5 6 1011 1516 2021222324 31 000110 rd ra 10100fscl ui8 0 5 6 1011 1516 2021 31 011100 si 0:4 ra 1 0100 si 5:15 vle instruction set RM0004 945/1176 _ mullw x _mullw x multiply low word se_mullw r x ,r y prod 0:63 gpr(rx) 32:63 gpr(ry) 32:63 gpr(rx) prod 32:63 bits 32?63 of the 64-bit product of the contents of bits 32?63 of gpr( r x) and the contents of bits 32?63 of gpr( r y) is placed into gpr( r x). special registers altered: none 0 5678 1112 15 00000101 ry rx vle user RM0004 vle instruction set 946/1176 _ neg x _neg x negate se_neg r x result 32:63 ? gpr(rx)+ 1 gpr(rx) result 32:63 the sum of the one?s complement of the contents of gpr( r x) and 1 is placed into gpr( r x). if bits 32?63 of gpr( r x) contain the most negative 32-bit number (0x8000_0000), bits 32? 63 of the result contain the most negative 32-bit number special registers altered: none 056111215 000000000011 rx vle user vle instruction set RM0004 947/1176 _ not x _not x not se_not r x result 32:63 ? gpr(rx) gpr(rx) result 32:63 the contents of gpr( r x) are inverted. special registers altered: none 056112115 000000000010 rx vle user RM0004 vle instruction set 948/1176 _ or x _or x or [2 operand] [immediate | with complement] [shifted][and record] se_or r x ,r y e_or2i r d , ui e_or2is r d , ui e_ori r a ,r s , sci8 (rc = 0) e_ori. r a ,r s , sci8 (rc = 1) if ?e_ori[ . ]? then b sci8(f,scl,ui8) if ?e_or2i? then b 16 0 || ui 0:4 || ui 5:15 if ?e_or2is? then b ui 0:4 || ui 5:15 || 16 0 if ?se_or? then b gpr(rb) result 0:63 gpr(rs or rd or rx) | b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rd or rx) result for e_ori [ . ], the contents of gpr( r s) are ored with the value of sci8. for e_or2i, the contents of gpr( r d) are ored with 16 0 || ui. for e_or2is , the contents of gpr( r d) are ored with ui || 16 0. for se_or , the contents of gpr( r x) are ored with the contents of gpr( r y). the result is placed into gpr( r a or r x). the preferred ?no-op? (an instruction that does nothing) is: e_ori 0,0,0 special registers altered: cr0 (if rc = 1) 0 5678 1112 15 01000100 ry rx vle user 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11000 ui 5:15 0 5 6 1011 1516 2021 31 011100 rd ui 0:4 11010 ui 5:15 0 5 6 1011 1516 192021222324 31 000110 rs ra 1101rcfscl ui8 vle instruction set RM0004 949/1176 _ rfci _rfci return from critical interrupt se_rfci msr csrr1 nia csrr0 0:62 || 0b0 the se_rfci instruction is used to return from a critical class interrupt, or as a means of establishing a new context and synchroniz ing on that new context simultaneously. the contents of csrr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched, under control of the new msr value, from the address csrr0[32?62]||0b0. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0 or csrr0 by the interrupt processing mechanism (see book e) is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in csrr0 at the time of the execution of the se_rfci ). execution of this instruction is privile ged and restricted to supervisor mode. execution of this instructio n is context synchronizing. special registers altered: msr 015 0000000000001001 vle supervisor RM0004 vle instruction set 950/1176 _ rfi _rfi return from interrupt se_rfi msr srr1 nia srr0 0:62 || 0b0 the se_rfi instruction is used to return from a non-critical class interrupt, or as a means of simultaneously establishing a new context and synchronizing on that new context. the contents of srr1 are placed into the msr. if the new msr value does not enable any pending exceptions, then the next instruction is fetched under control of the new msr value from the address srr0[32?62]||0b0. if the new msr value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into srr0 or csrr0 by the interrupt processing mechanism (see book e) is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in srr0 at the time of the execution of the se_rfi ). execution of this instruction is privile ged and restricted to supervisor mode. execution of this instructio n is context synchronizing. special registers altered: msr 015 0000000000001000 vle supervisor vle instruction set RM0004 951/1176 _ rlw _rlw rotate left word [immediate] e_rlw r a ,r s ,r b(rc=0) e_rlw. r a ,r s ,r b(rc=1) e_rlwi r a ,r s , sh (rc = 0) e_rlwi. r a ,r s , sh (rc = 1) if ? e_rlw [ . ]? then n gpr(rb) 59:63 else n sh result 32:63 rotl 32 (gpr(rs) 32:63 ,n) if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra) result 32:63 if e_rlw [ . ], let the shift count n be the contents of bits 59?63 of gpr( r b). if e_rlwi [ . ], let the shift count n be sh. the contents of gpr( r s) are rotated 32 left n bits. the rotated data is placed into gpr( r a). special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 2021 3031 011111 rs ra rb 0100011000rc 0 5 6 1011 1516 2021 3031 011111 rs ra sh 0100111000rc RM0004 vle instruction set 952/1176 _ rlwimi _rlwimi rotate left word immediate then mask insert e_rlwimi r a ,r s , sh , mb , me n sh b mb+32 e me+32 r rotl 32 (gpr(rs) 32:63 ,n) m mask(b,e) result 32:63 r&m | gpr(ra)& ? m gpr(ra) result 32:63 let the shift count n be the value sh. the contents of gpr( r s) are rotated 32 left n bits. a mask is generated having 1 bits from bit mb+32 through bit me+32 and 0 bits elsewhere. the rotated data are inserted into gpr( r a) under control of the generated mask (if a mask bit is 1 the associated bit of the rotated data is placed into the target register, and if the mask bit is 0 the associated bit in the target register remains unchanged). special registers altered: none vle user 0 5 6 1011 1516 2021 2526 3031 011101 rs ra sh mb me 0 vle instruction set RM0004 953/1176 _ rlwinm _rlwinm rotate left word immediate then and with mask e_rlwinm r a ,r s , sh , mb , me n sh b mb+32 e me+32 r rotl 32 (gpr(rs) 32:63 ,n) m mask(b,e) result 32:63 r & m gpr(ra) result 32:63 let the shift count n be sh. the contents of gpr( r s) are rotated 32 left n bits. a mask is generated having 1 bits from bit mb+32 through bit me+32 and 0 bits elsewhere. the rotated data are anded with the generated mask and the result is placed into gpr( r a). special registers altered: none vle user 0 5 6 1011 1516 2021 2526 3031 011101 rs ra sh mb me 1 RM0004 vle instruction set 954/1176 _ sc _sc system call se_sc srr1 msr srr0 cia+2 nia ivpr 32:47 || ivor8 48:59 || 0b0000 msr we,ee,pr,is,ds,fp,fe0,fe1 0b0000_0000 se_sc is used to request a system service. a system call interrupt is generated. the contents of the msr are copied into srr1 and the address of the instruction after the se_sc instruction is placed into srr0. msr[we,ee,pr,is,ds,fp,fe0,fe1] are cleared. the interrupt causes the next instruction to be fetched from the address ivpr[32?47]||ivor8[48?59]||0b0000 this instruction is context synchronizing. special registers altered: srr0 sr r1 msr[we,ee,pr,is,ds,fp,fe0,fe1] 015 0000000000000010 vle user vle instruction set RM0004 955/1176 _ slw x _slw x shift left word [immediate] [and record] e_slwi r a ,r s , sh (rc = 0) e_slwi. r a ,r s , sh (rc = 1) se_slw r x ,r y se_slwi r x , ui5 if ?e_slwi[ . ]? then n sh if se_slw then n gpr(ry) 58:63 if se_slwi then n ui5 r rotl 32 (gpr(rs or rx) 32:63 ,n) if n<32 then m mask(32,63-n) else m 32 0 result 32:63 r & m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rx) result 32:63 let the shift count n be the value specified by the contents of bits 58?63 of gpr( r b or r y), or by the value of the sh or ui5 field. the contents of bits 32?63 of gpr( r s or r x) are shifted left n bits. bits shifted out of position 32 are lost. zeros are supplied to the vacated positions on the right. the 32-bit result is placed into bits 32?63 of gpr( r a or r x). shift amounts from 32 to 63 give a zero result. special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 2021 3031 011111 rs ra sh 0000111000rc 0 5678 1112 15 01000010 ry rx 0 5 6 7 11 12 15 0110110 ui5 rx RM0004 vle instruction set 956/1176 _ sraw x _sraw x shift right algebraic word [immediate] [and record] se_sraw r x ,r y se_srawi r x , ui5 if ?se_sraw? then n gpr(ry) 59:63 if ?se_srawi? then n ui5 r rotl 32 (gpr(rs or rx) 32:63 ,32-n) if ((se_sraw & gpr(ry) 58 =1) then m 32 0 else m mask(n+32,63) s gpr(rs or rx) 32 result 0:63 r&m | ( 32 s)& ? m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rx) result 32:63 ca s & ((r& ? m) 32:63 0) if se_sraw , let the shift count n be the contents of bits 58?63 of gpr( r y). if se_srawi , let the shift count n be the value of the ui5 field. the contents of bits 32?63 of gpr( r s or r x) are shifted right n bits. bits shifted out of position 63 are lost. bit 32 of r s or r x is replicated to fill vacate d positions on the left. the 32-bit result is placed into bits 32?63 of gpr( r a or r x). ca is set if bits 32?63 of gpr( r s or r x) contain a negative value and any 1 bits are shifted out of bit position 63; otherwise ca is cleared. a shift amount of zero causes gpr( r a or r x) to receive exts(gpr( r s or r x) 32:63 ), and ca to be cleared. for se_sraw, shift amounts from 32 to 63 give a result of 64 sign bits, and cause ca to receive bit 32 of the contents of gpr( r s or r x) (that is, sign bit of gpr( r s or r x) 32:63 ). special registers altered: ca cr0 (if rc = 1) 0 5678 1112 15 01000001 ry rx 0 5 6 7 11 12 15 0110101 ui5 rx vle user vle instruction set RM0004 957/1176 _ srw x _srw x shift right word [immediate] [and record] e_srwi r a ,r s , sh (rc = 0) e_srwi. r a ,r s , sh (rc = 1) se_srw r x ,r y se_srwi r x , ui5 n gpr(rb) 59:63 if ?e_srwi[ . ]? then n sh if ?se_srw? then n gpr(ry) 59:63 if ?se_srwi? then n ui5 r rotl 32 (gpr(rs or rx) 32:63 ,32-n) if ((se_srw & gpr(ry) 58 =1) then m 32 0 else m mask(n+32,63) result 32:63 r & m if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra or rx) result 32:63 if e_srwi , let the shift count n be the value of the sh field. if se_srw , let the shift count n be the contents of bits 58?63 of gpr( r y). if se_srwi , let the shift count n be the value of the ui5 field. the contents of bits 32?63 of gpr( r s or r x) are shifted right n bits. bits shifted out of position 63 are lost. zeros are supplied to the vacated positions on the left. the 32-bit result is placed into bits 32?63 of gpr( r a or r x). shift amounts from 32 to 63 give a zero result. special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 2021 3031 011111 rs ra sh 1000111000rc 0 5678 1112 15 01000000 ry rx 0 5 6 7 11 12 15 0110100 ui5 rx RM0004 vle instruction set 958/1176 _ stb x _stb x store byte [with update] [indexed] e_stb r s , d (r a ) (d-mode) se_stb r z , sd4 (r x ) (sd4-mode) e_stbu r s , d8 (r a ) (d8-mode) if (ra=0 & !se_stb) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 28 0 || sd4)) 32:63 mem(ea,1) gpr(rs or rz) 56:63 if e_stbu then gpr(ra) ea let the ea be calculated as follows: for e_stb and e_stbu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_stb , let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field. the contents of bits 56?63 of gpr( r s) are stored into the byte in memory addressed by ea. if e_stbu , ea is placed into gpr( r a). if e_stbu and r a = 0, the instruction form is invalid. none vle user 05610111516 31 001101 rs ra d 03478111215 1 0 0 1 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rs ra 00000100 d8 vle instruction set RM0004 959/1176 _ sth x _sth x store halfword [with update] [indexed] e_sth r s , d (r a ) (d-mode) se_sth r z , sd4 (r x ) (sd4-mode) e_sthu r s , d8 (r a ) (d8-mode) if (ra=0 & !se_sth) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 27 0 || sd4 || 0)) 32:63 mem(ea,2) gpr(rs or rz) 48:63 if e_sthu then gpr(ra) ea let the ea be calculated as follows: for e_sth and e_sthu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a=0, and the sign-extended value of the d or d8 instruction field. for se_sth let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 1 bit. the contents of bits 48?63 of gpr( r s) are stored into the half word in memory addressed by ea. if e_sthu , ea is placed into gpr( r a). if e_sthu and r a = 0, the instruction form is invalid. special registers altered: none vle user 05610111516 31 010111 rs ra d 03478111215 1 0 1 1 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rs ra 0 0 0 0 0 1 0 1 d8 RM0004 vle instruction set 960/1176 _ stmw _stmw store multiple word e_stmw r s , d8 (r a ) (d8-mode) if ra=0 then ea exts(d8) 32:63 else ea (gpr(ra)+exts(d8)) 32:63 r rs do while r 31 mem(ea,4) gpr(r) 32:63 r r + 1 ea (ea+4) 32:63 let the ea be the sum of the contents of gpr( r a), or 32 0s if r a = 0, and the sign-extended value of the d8 instruction field. let n = (32 - r s). bits 32?63 of registers gpr( r s) through gpr(31) are stored in n consecutive words in memory starting at address ea. ea must be a multiple of 4. if it is not, either an alignment interrupt is invoked or the results are boundedly undefined. special registers altered: none vle user 0 5 6 1011 1516 2324 31 000110 rs ra 00001001 d8 vle instruction set RM0004 961/1176 _ stw x _stw x store word [with update] [indexed] e_stw r s , d (r a ) (d-mode) se_stw r z , sd4 (r x ) (sd4-mode) e_stwu r s , d8 (r a ) (d8-mode) if (ra=0 & !se_stw) then a 32 0 else a gpr(ra or rx) if d-mode then ea (a + exts(d)) 32:63 if d8-mode then ea (a + exts(d8)) 32:63 if sd4-mode then ea (a + ( 26 0 || sd4 || 2 0)) 32:63 mem(ea,4) gpr(rs or rz) 32:63 let the ea be calculated as follows: for e_stw and e_stwu , let ea be the sum of the contents of gpr( r a), or 32 0s if r a = 0, and the sign-extended value of the d or d8 instruction field. for se_stw , let ea be the sum of the contents of gpr( r x) and the zero-extended value of the sd4 instruction field shifted left by 2 bits. the contents of bits 32?63 of gpr( r s) are stored into the word in memory addressed by ea. if e_stwu , ea is placed into gpr( r a). if e_stwu and r a = 0, the instruction form is invalid. special registers altered: none vle user 05610111516 31 010101 rs ra d 03478111215 1 1 0 1 sd4 rz rx 0 5 6 1011 1516 2324 31 000110 rs ra 00000110 d8 RM0004 vle instruction set 962/1176 _ sub _sub subtract se_sub r x ,r y sum 32:63 gpr(rx) + ? gpr(ry) + 1 gpr(rx) sum 32:63 the sum of the contents of gpr( r x), the one?s complement of contents of gpr( r y), and 1 is placed into gpr( r x). special registers altered: none 0 5678 1112 15 00000110 ry rx vle user vle instruction set RM0004 963/1176 _ subf x _subf x subtract from se_subf r x ,r y sum 32:63 ? gpr(rx) + gpr(ry) + 1 gpr(rx) sum 32:63 the sum of the one?s complement of the contents of gpr( r x), the contents of gpr( r y), and 1 is placed into gpr( r x). special registers altered: none 056101115 vle user RM0004 vle instruction set 964/1176 _ subfic x _subfic x subtract from immediate carrying [and record] e_subfic r d ,r a , sci8 (rc = 0) e_subfic. r d ,r a , sci8 (rc = 1) imm sci8(f,scl,ui8) carry 32:63 carry( ? gpr(ra) + imm + 1) sum 32:63 ? gpr(ra) + imm + 1 if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rd) sum 32:63 ca carry 32 the sum of the one?s complement of the contents of gpr( r a), the value of sci8, and 1 is placed into gpr( r d). special registers altered: ca cr0 (if rc=1) vle user 0 5 6 1011 1516 2021222324 31 000110 rd ra 1011rcfscl ui8 vle instruction set RM0004 965/1176 _ subi x _subi x subtract immediate [and record] se_subi r x , oimm (rc = 0) se_subi. r x , oimm (rc = 1) sum 32:63 gpr(rx) + ?( 27 0 || offset(oim5)) + 1 if rc=1 then do lt sum 32:63 < 0 gt sum 32:63 > 0 eq sum 32:63 = 0 cr0 lt || gt || eq || so gpr(rx) sum 32:63 the sum of the contents of gpr( r x), the one?s complement of the zero-extended value of the offseted oim5 field (a final value in the range 1?32), and 1 is placed into gpr( r x). special registers altered: cr0 (if rc = 1) 0 5 6 7 11 12 15 001001rc oim5 (1) 1. oimm = oim5 +1 rx vle user RM0004 vle instruction set 966/1176 _ xor x _xor x xor [immediate] [and record] e_xori r a ,r s , sci8 (rc = 0) e_xori. r a ,r s , sci8 (rc = 1) if ?e_xori[ . ]? then b sci8(f,scl,ui8) result 32:63 gpr(rs) b if rc=1 then do lt result 32:63 < 0 gt result 32:63 > 0 eq result 32:63 = 0 cr0 lt || gt || eq || so gpr(ra) result for e_xori [ . ], the contents of gpr( r s) are xored with sci8. the result is placed into gpr( r a). special registers altered: cr0 (if rc = 1) vle user 0 5 6 1011 1516 192021222324 31 000110 rs ra 1110rcfscl ui8 vle instruction index RM0004 967/1176 14 vle instruction index the tables in this appendix use the following conventions: 14.1 instruction index sorted by opcode table 261 lists the 16-bit vle instructions, sorted by opcode. table 260. notation conventions notation meaning - don?t care, usually part of an operand field / reserved bit, invalid instruction form if encoded as 1 ? allocated for implementatio n-dependent use. see the im plementation documentation. table 261. instruction index sorted by opcode format 16-bit opcodes mnemonic instruction page (inst 0:15 ) c 0000 0000 0000 0000 se_illegal illegal -928 c 0000 0000 0000 0001 se_isync instruction synchronize -929 c 0000 0000 0000 0010 se_sc system call -954 c 0000 0000 0000 0100 se_blr branch to link register -908 c 0000 0000 0000 0101 se_blrl branch to link register & link -908 c 0000 0000 0000 0110 se_bctr branch to count register -906 c 0000 0000 0000 0111 se_bctrl branch to count register & link -906 c 0000 0000 0000 1000 se_rfi return from interrupt -950 c 0000 0000 0000 1001 se_rfci return from critical interrupt -949 c 0000 0000 0000 1010 se_rfdi return from debug interrupt -949 c 0000 0000 0000 1011 c 0000 0000 0001 - - - - r 0000 0000 0010 xxxx se_not not -947 r 0000 0000 0011 xxxx se_neg negate -946 r 0000 0000 01 - - xxxx r 0000 0000 1000 xxxx se_mflr move from link register -939 r 0000 0000 1001 xxxx se_mtlr move to link register -943 r 0000 0000 1010 xxxx se_mfctr move from count register -938 r 0000 0000 1011 xxxx se_mtctr move to count register -942 r 0000 0000 1100 xxxx se_extzb extend with zeros byte -927 RM0004 vle instruction index 968/1176 r 0000 0000 1101 xxxx se_extsb extend sign byte -926 r 0000 0000 1110 xxxx se_extzh extend with zeros halfword -927 r 0000 0000 1111 xxxx se_extsh extend sign halfword -926 r 0000 0001 yyyy xxxx se_mr move register -940 rr 0000 0010 yyyy xxxx se_mtar move to alternate register -941 rr 0000 0011 yyyy xxxx se_mfar move from alternate register -937 rr 0000 0100 yyyy xxxx se_add add -897 rr 0000 0101 yyyy xxxx se_mullw multiply low word -945 rr 0000 0110 yyyy xxxx se_sub subtract -962 rr 0000 0111 yyyy xxxx se_subf subtract from -963 rr 0000 10- - yyyy xxxx rr 0000 1100 yyyy xxxx se_cmp compare -912 rr 0000 1101 yyyy xxxx se_cmpl compare logical -918 rr 0000 1110 yyyy xxxx se_cmph compare halfword -914 rr 0000 1111 yyyy xxxx se_cmphl compare halfword logical -916 im5 0010 000i iiii xxxx se_addi add immediate -897 im5 0010 001i iiii xxxx se_cmpli compare logical immediate -918 im5 0010 010i iiii xxxx se_subi subtract immediate -965 im5 0010 011i iiii xxxx se_subi. subtract immediate and record -965 im5 0010 100i iiii xxxx im5 0010 101i iiii xxxx se_cmpi compare immediate -912 im5 0010 110i iiii xxxx se_bmask i bit mask generate immediate -909 im5 0010 111i iiii xxxx se_andi and immediate -901 rr 0100 0000 yyyy xxxx se_srw shift right word -957 rr 0100 0001 yyyy xxxx se_sraw shift right algebraic word -956 rr 0100 0010 yyyy xxxx se_slw shift left word -955 rr 0100 0011 yyyy xxxx rr 0100 0100 yyyy xxxx se_or or -948 rr 0100 0101 yyyy xxxx se_andc and with complement -901 rr 0100 0110 yyyy xxxx se_and and -901 rr 0100 0111 yyyy xxxx se_and. and and record -901 im7 0100 1iii iiii xxxx se_li load immediate -933 table 261. instruction index sorted by opcode (continued) format 16-bit opcodes mnemonic instruction page (inst 0:15 ) vle instruction index RM0004 969/1176 table 262 shows 32-bit instruction encodings. im5 0110 000i iiii xxxx se_bclri bit clear immediate -905 im5 0110 001i iiii xxxx se_bgeni bit generate immediate -906 im5 0110 010i iiii xxxx se_bseti bit set immediate -910 im5 0110 011i iiii xxxx se_btsti bit test immediate -911 im5 0110 100i iiii xxxx se_srwi shift right word immediate -957 im5 0110 101i iiii xxxx se_srawi shift right algebraic word immediate -957 im5 0110 110i iiii xxxx se_slwi shift left word immediate -955 im5 0110 111i iiii xxxx sd4 1000 iiii zzzz xxxx se_lbz load byte and zero -930 sd4 1001 iiii zzzz xxxx se_stb store byte -958 sd4 1010 iiii zzzz xxxx se_lhz load halfword and zero -932 sd4 1011 iiii zzzz xxxx se_sth store halfword -959 sd4 1100 iiii zzzz xxxx se_lwz load word and zero -935 sd4 1101 iiii zzzz xxxx se_stw store word -961 b8 1110 0o i i dddd dddd se_bc branch conditional -904 b8 1110 1000 dddd dddd se_b branch -910 b8 1110 1001 dddd dddd se_bl branch and link -910 1110 101- ---- ---- 1110 11-- ---- ---- table 261. instruction index sorted by opcode (continued) format 16-bit opcodes mnemonic instruction page (inst 0:15 ) table 262. 32-bit instruction encodings format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) apu 00010 ------ ----- ---------- ----- - apu reserved for apus d8 000110t t t t t aaaaa 00000000dd ddddd d e_lbzu load byte & zero with update -930 d8 000110t t t t t aaaaa 00000001dd ddddd d e_lhzu load halfword & zero with update -932 d8 000110t t t t t aaaaa 00000010dd ddddd d e_lwzu load word & zero with update -935 RM0004 vle instruction index 970/1176 d8 000110t t t t t aaaaa 00000011dd ddddd d e_lhau load halfword algebraic with update -931 d8 000110t t t t t aaaaa 00000100dd ddddd d e_stbu store byte with update -958 d8 000110t t t t t aaaaa 00000101dd ddddd d e_sthu store halfword with update -959 d8 000110t t t t t aaaaa 00000110dd ddddd d e_stwu store word with update -961 d8 000110t t t t t aaaaa 00000111dd ddddd d d8 000110t t t t t aaaaa 00001000dd ddddd d e_lmw load multiple word -934 d8 000110t t t t t aaaaa 00001001dd ddddd d e_stmw store multiple word -960 d8 000110t t t t t aaaaa 00001010dd ddddd d d8 000110t t t t t aaaaa 00001011dd ddddd d 000110t t t t t aaaaa 000011- - dd ddddd d 000110t t t t t aaaaa 0001- - - - - - - - - - - - 000110t t t t t aaaaa 001- - - - - - - - - - - - - 000110t t t t t aaaaa 01- - - - - - - - - - - - - - sci8 000110t t t t t aaaaa 10000fssi i i i i i i i e_addi add immediate -897 sci8 000110t t t t t aaaaa 10001fssi i i i i i i i e_addi. add immediate and record -897 sci8 000110t t t t t aaaaa 10010fssi i i i i i i i e_addic add immediate carrying -900 sci8 000110t t t t t aaaaa 10011fssi i i i i i i i e_addic. add immediate carrying and record -900 sci8 000110t t t t t aaaaa 10100fssi i i i i i i i e_mulli multiply low immediate -944 sci8 000110000bf aaaaa 10101fssi i i i i i i i e_cmpi compare immediate -912 sci8 000110001bf aaaaa 10101fssi i i i i i i i e_cmpli compare logical immediate -918 sci8 000110t t t t t aaaaa 10110fssi i i i i i i i e_subfic subtract from immediate carrying -964 table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 971/1176 sci8 000110t t t t t aaaaa 10111fssi i i i i i i i e_subfic. subtract from immediate and record -964 sci8 000110sssss aaaaa 11000fssi i i i i i i i e_andi and immediate -901 sci8 000110sssss aaaaa 11001fssi i i i i i i i e_andi. and immediate and record -901 sci8 000110sssss aaaaa 11010fssi i i i i i i i e_ori or immediate -951 sci8 000110sssss aaaaa 11011fssi i i i i i i i e_ori. or immediate and record -951 sci8 000110sssss aaaaa 11100fssi i i i i i i i e_xori xor immediate -966 sci8 000110sssss aaaaa 11101fssi i i i i i i i e_xori. xor immediate and record -966 sci8 000110sssss aaaaa 11110fssi i i i i i i i sci8 000110sssss aaaaa 11111fssi i i i i i i i d 000111t t t t t aaaaa i i i i i i i i i i i i i i i i e_add16i add immediate -897 d 001100t t t t t aaaaa dddddddddd ddddd d e_lbz load byte & zero -930 d 001101t t t t t aaaaa dddddddddd ddddd d e_stb store byte -958 d 001110t t t t t aaaaa dddddddddd ddddd d e_lha load halfword algebraic -931 001111- - - - - - - - - - - - - - - - - - - - - - - - - - d 010100t t t t t aaaaa dddddddddd ddddd d e_lwz load word & zero -935 d 010101t t t t t aaaaa dddddddddd ddddd d e_stw store word -961 d 010110t t t t t aaaaa dddddddddd ddddd d e_lhz load halfword & zero -932 d 010111t t t t t aaaaa dddddddddd ddddd d e_sth store halfword -959 li20 011100t t t t t i i i i i 0i i i i i i i i i i i i i i i e_li load immediate -933 i16a 011100i i i i i aaaaa 10000i i i i i i i i i i i i16a 011100i i i i i aaaaa 10001i i i i i i i i i i i e_add2i. add (2 operand) immediate and record cr -898 i16a 011100i i i i i aaaaa 10010i i i i i i i i i i i e_add2is add (2 operand) immediate shifted -898 i16a 011100i i i i i aaaaa 10011i i i i i i i i i i i e_cmp16i compare immediate -912 table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 972/1176 i16a 011100i i i i i aaaaa 10100i i i i i i i i i i i e_mull2i multiply low word (2 operand) immediate -944 i16a 011100i i i i i aaaaa 10101i i i i i i i i i i i e_cmpl16i compare logical immediate -918 i16a 011100i i i i i aaaaa 10110i i i i i i i i i i i e_cmph16 i compare halfword immediate -914 i16a 011100i i i i i aaaaa 10111i i i i i i i i i i i e_cmphl1 6i compare halfword logical immediate -916 i16l 011100t t t t t i i i i i 11000i i i i i i i i i i i e_or2i or (2 operand) immediate -948 i16l 011100t t t t t i i i i i 11001i i i i i i i i i i i e_and2i. and (2 operand) immediate & record cr -901 i16l 011100t t t t t i i i i i 11010i i i i i i i i i i i e_or2is or (2 operand) immediate shifted -966 i16l 011100t t t t t i i i i i 11011i i i i i i i i i i i i16l 011100t t t t t i i i i i 11100i i i i i i i i i i i e_lis load immediate shifted -933 i16l 011100t t t t t i i i i i 11101i i i i i i i i i i i e_and2is. and (2 operand) immediate shifted & record cr -901 i16l 011100t t t t t i i i i i 11110i i i i i i i i i i i i16l 011100t t t t t i i i i i 11111i i i i i i i i i i i rlwi 011101sssss aaaaa hhhhhbbbbb eeeee 0 e_rlwimi rotate left word immed then mask insert -952 rlwi 011101sssss aaaaa hhhhhbbbbb eeeee 1 e_rlwinm rotate left word immed then and with mask -953 bd24 0111100dddd ddddd dddddddddd ddddd 0 e_b branch -903 bd24 0111100dddd ddddd dddddddddd ddddd 1 e_bl branch & link -903 bd15 0111101000o oi i i i dddddddddd ddddd 0 e_bc branch conditional -904 table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 973/1176 bd15 0111101000o oi i i i dddddddddd ddddd 1 e_bcl branch conditional & link -904 x 011111 - - - - - 01111 / isel integer select book e x 011111 / 0000 01011 0 mulhwu multiply high word unsigned book e x 011111 / 0000 01011 1 mulhwu. multiply high word unsigned & record book e x 011111 / 0010 01011 0 mulhw multiply high word book e x 011111 / 0010 01011 1 mulhw. multiply high word & record cr book e x 011111 00000 00000 / cmp compare book e x 011111 00000 00100 / tw trap word book e x 011111 00000 01000 0 subfc subtract from carrying book e x 011111 00000 01000 1 subfc. subtract from carrying & record cr book e x 011111 00000 01010 0 addc add carrying book e x 011111 00000 01010 1 addc. add carrying & record cr book e x 011111 00000 01110 / e_cmph compare halfword -914 xl 011111 00000 10000 / e_mcrf move condition register field -944 x 011111 00000 10011 / mfcr move from condition register book e x 011111 00000 10100 / lwarx load word & reserve indexed book e x 011111 00000 10110 / icbt instruction cache block touch indexed book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 974/1176 x 011111 00000 10111 / lwzx load word & zero indexed book e x 011111 00000 11000 0 slw shift left word book e x 011111 00000 11000 1 slw. shift left word & record cr book e x 011111 00000 11010 0 cntlzw count leading zeros word book e x 011111 00000 11010 1 cntlzw. count leading zeros word & record cr book e x 011111 00000 11100 0 and and book e x 011111 00000 11100 1 and. and & record cr book e x 011111 00001 00000 / cmpl compare logical book e xl 011111 00001 00001 / e_crnor condition register nor -922 x 011111 00001 01000 0 subf subtract from book e x 011111 00001 01000 1 subf. subtract from & record cr book e x 011111 00001 01110 / e_cmphl compare halfword logical -916 x 011111 00001 10110 / dcbst data cache block store indexed book e x 011111 00001 10111 / lwzux load word & zero with update indexed book e x 011111 00001 11000 0 e_slwi shift left word immediate -955 x 011111 00001 11000 1 e_slwi. shift left word immediate & record cr -955 x 011111 00001 11100 0 andc and with complement book e x 011111 00001 11100 1 andc. and with complement & record cr book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 975/1176 x 011111 00010 10011 / mfmsr move from machine state register book e x 011111 00010 10110 / dcbf data cache block flush indexed book e x 011111 00010 10111 / lbzx load byte & zero indexed book e x 011111 00011 01000 0 neg negate book e x 011111 00011 01000 1 neg. negate & record cr book e x 011111 00011 10111 / lbzux load byte & zero with update indexed book e x 011111 00011 11100 0 nor nor book e x 011111 00011 11100 1 nor. nor & record cr book e xl 011111 00100 00001 / e_crandc condition register and with complement -920 x 011111 00100 00011 / wrtee write external enable book e x 011111 00100 01000 0 subfe subtract from extended with ca book e x 011111 00100 01000 1 subfe. subtract from extended with ca & record cr book e x 011111 00100 01010 0 adde add extended with ca book e x 011111 00100 01010 1 adde. add extended with ca & record cr book e xfx 011111 00100 10000 / mtcrf move to condition register fields book e x 011111 00100 10010 / mtmsr move to machine state register book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 976/1176 x 011111 00100 10110 1 stwcx. store word conditional indexed & record cr book e x 011111 00100 10111 / stwx store word indexed book e x 011111 00101 00011 / wrteei write external enable immediate book e x 011111 00101 10111 / stwux store word with update indexed book e xl 011111 00110 00001 / e_crxor condition register xor -925 x 011111 00110 01000 0 subfze subtract from zero extended with ca book e x 011111 00110 01000 1 subfze. subtract from zero extended with ca & record cr book e x 011111 00110 01010 0 addze add to zero extended with ca book e x 011111 00110 01010 1 addze. add to zero extended with ca & record cr book e x 011111 00110 10111 / stbx store byte indexed book e xl 011111 00111 00001 / e_crnand condition register nand book e x 011111 00111 01000 0 subfme subtract from minus one extended with ca book e x 011111 00111 01000 1 subfme. subtract from minus one extended with ca & record cr book e x 011111 00111 01010 0 addme add to minus one extended with ca book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 977/1176 x 011111 00111 01010 1 addme. add to minus one extended with ca & record cr book e x 011111 00111 01011 0 mullw multiply low word book e x 011111 00111 01011 1 mullw. multiply low word & record cr book e x 011111 00111 10110 / dcbtst data cache block touch for store indexed book e x 011111 00111 10111 / stbux store byte with update indexed book e xl 011111 01000 00001 / e_crand condition register and -920 x 011111 01000 01010 0 add add book e x 011111 01000 01010 1 add. add & record cr book e x 011111 01000 10011 / mfapidi move from apid indirect book e x 011111 01000 10110 / dcbt data cache block touch indexed book e x 011111 01000 10111 / lhzx load halfword & zero indexed book e x 011111 01000 11000 0 e_rlw rotate left word -951 x 011111 01000 11000 1 e_rlw. rotate left word & record cr -951 x 011111 01000 11100 0 eqv equivalent book e x 011111 01000 11100 1 eqv. equivalent & record cr book e xl 011111 01001 00001 / e_creqv condition register equivalent -920 x 011111 01001 10111 / lhzux load halfword & zero with update indexed book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 978/1176 x 011111 01001 11000 0 e_rlwi rotate left word immediate -952 x 011111 01001 11000 1 e_rlwi. rotate left word immediate & record cr -952 x 011111 01001 11100 0 xor xor book e x 011111 01001 11100 1 xor. xor & record cr book e xfx 011111 01010 00011 / mfdcr move from device control register book e xfx 011111 01010 10011 / mfspr move from special purpose register book e x 011111 01010 10111 / lhax load halfword algebraic indexed book e x 011111 01011 10111 / lhaux load halfword algebraic with update indexed book e x 011111 01100 10111 / sthx store halfword indexed book e x 011111 01100 11100 0 orc or with complement book e x 011111 01100 11100 1 orc. or with complement & record cr book e xl 011111 01101 00001 / e_crorc condition register or with complement -923 x 011111 01101 10111 / sthux store halfword with update indexed book e x 011111 01101 11100 0 or or book e x 011111 01101 11100 1 or. or & record cr book e xl 011111 01110 00001 / e_cror condition register or -923 table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 979/1176 xfx 011111 01110 00011 / mtdcr move to device control register book e x 011111 01110 01011 0 divwu divide word unsigned book e x 011111 01110 01011 1 divwu. divide word unsigned & record cr book e xfx 011111 01110 10011 / mtspr move to special purpose register book e x 011111 01110 10110 / dcbi data cache block invalidate indexed book e x 011111 01110 11100 0 nand nand book e x 011111 01110 11100 1 nand. nand & record cr book e x 011111 01111 01011 0 divw divide word book e x 011111 01111 01011 1 divw. divide word & record cr book e x 011111 10000 00000 / mcrxr move to condition register from xer book e x 011111 10000 01000 0 subfco subtract from carrying & record ov book e x 011111 10000 01000 1 subfco. subtract from carrying & record ov & cr book e x 011111 10000 01010 0 addco add carrying & record ov book e x 011111 10000 01010 1 addco. add carrying & record ov & cr book e x 011111 10000 10110 / lwbrx load word byte- reverse indexed book e x 011111 10000 11000 0 srw shift right word book e x 011111 10000 11000 1 srw. shift right word & record cr book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 980/1176 x 011111 10001 01000 0 subfo subtract from & record ov book e x 011111 10001 01000 1 subfo. subtract from & record ov & cr book e x 011111 10001 10110 / tlbsync tlb synchronize book e x 011111 10001 11000 0 e_srwi shift right word immediate -957 x 011111 10001 11000 1 e_srwi. shift right word immediate & record cr -957 x 011111 10010 10110 / msync memory synchronize book e x 011111 10011 01000 0 nego negate & record ov book e x 011111 10011 01000 1 nego. negate & record ov & record cr book e x 011111 10100 01000 0 subfeo subtract from extended with ca & record ov book e x 011111 10100 01000 1 subfeo. subtract from extended with ca & record ov & cr book e x 011111 10100 01010 0 addeo add extended with ca & record ov book e x 011111 10100 01010 1 addeo. add extended with ca & record ov & cr book e x 011111 10100 10101 / stswx store string word indexed book e x 011111 10100 10110 / stwbrx store word byte- reverse indexed book e x 011111 10110 01000 0 subfzeo subtract from zero extended with ca & record ov book e x 011111 10110 01000 1 subfzeo. subtract from zero extended with ca & record ov & cr book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 981/1176 x 011111 10110 01010 0 addzeo add to zero extended with ca & record ov book e x 011111 10110 01010 1 addzeo. add to zero extended with ca & record ov & cr book e x 011111 10110 10101 / stswi store string word immediate book e x 011111 10111 01000 0 subfmeo subtract from minus one extended with ca & record ov book e x 011111 10111 01000 1 subfmeo. subtract from minus one extended with ca & record ov & cr book e x 011111 10111 01010 0 addmeo add to minus one extended with ca & record ov book e x 011111 10111 01010 1 addmeo. add to minus one extended with ca & record ov & cr book e x 011111 10111 01011 0 mullwo multiply low word & record ov book e x 011111 10111 01011 1 mullwo. multiply low word & record ov & cr book e x 011111 10111 10110 / dcba data cache block allocate indexed book e x 011111 11000 01010 0 addo add & record ov book e x 011111 11000 01010 1 addo. add & record ov & cr book e x 011111 11000 10010 / tlbivax tlb invalidate virtual address indexed book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 982/1176 x 011111 11000 10110 / lhbrx load halfword byte-reverse indexed book e x 011111 11000 11000 0 sraw shift right algebraic word book e x 011111 11000 11000 1 sraw. shift right algebraic word & record cr book e x 011111 11001 11000 0 srawi shift right algebraic word immediate book e x 011111 11001 11000 1 srawi. shift right algebraic word immediate & record cr book e x 011111 11010 10110 / mbar memory barrier book e x 011111 11100 10010 ? tlbsx tlb search indexed book e x 011111 11100 10110 / sthbrx store halfword byte-reverse indexed book e x 011111 11100 11010 0 extsh extend sign halfword book e x 011111 11100 11010 1 extsh. extend sign halfword & record cr book e x 011111 11101 10010 / tlbre tlb read entry book e x 011111 11101 11010 0 extsb extend sign byte book e x 011111 11101 11010 1 extsb. extend sign byte & record cr book e x 011111 11110 01011 0 divwuo divide word unsigned & record ov book e x 011111 11110 01011 1 divwuo. divide word unsigned & record ov & cr book e x 011111 11110 10010 / tlbwe tlb write entry book e table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 983/1176 x 011111 11110 10110 / icbi instruction cache block invalidate indexed book e x 011111 11111 01011 0 divwo divide word & record ov book e x 011111 11111 01011 1 divwo. divide word & record ov & cr book e x 011111 11111 10110 / dcbz data cache block set to zero indexed book e x 1111- - reserved table 262. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 984/1176 14.2 instruction index sorted by mnemonic table 263 lists all of the 16-bit vle in structions, sorted by mnemonic. table 263. 16-bit vle instructions sorted by mnemonic format 16-bit opcodes (inst 0:15 ) mnemonic instruction page rr 0000 0100 yyyy xxxx se_add add -897 im5 0010 000 i i i i i xxxx se_addi add immediate -897 rr 0100 0110 yyyy xxxx se_and and -901 rr 0100 0111 yyyy xxxx se_and. and and record -901 rr 0100 0101 yyyy xxxx se_andc and with complement -901 im5 0010 111 i i i i i xxxx se_andi and immediate -901 b8 1 110 0o i i dddd dddd se_bc branch conditional -904 im5 0110 000 i i i i i xxxx se_bclri bit clear immediate -905 c 0 000 0000 0000 0110 se_bctr branch to count register -905 c 0 000 0000 0000 0111 se_bctrl branch to count register & link -905 im5 0110 001 i i i i i xxxx se_bgeni bit generate immediate -906 b8 1 110 1001 dddd dddd se_bl branch and link -910 c 0 000 0000 0000 0100 se_blr branch to link register -908 c 0 000 0000 0000 0101 se_blrl branch to link register & link -908 im5 0010 110 i i i i i xxxx se_bmaski bit mask generate immediate -909 b8 1 110 1000 dddd dddd se_b branch -903 im5 0110 010 i i i i i xxxx se_bseti bit set immediate -910 im5 0110 011 i i i i i xxxx se_btsti bit test immediate -911 rr 0000 1100 yyyy xxxx se_cmp compare -912 rr 0000 1110 yyyy xxxx se_cmph compare halfword -914 rr 0000 1111 yyyy xxxx se_cmphl compare halfword logical -916 im5 0010 101 i i i i i xxxx se_cmpi compare immediate -912 rr 0000 1101 yyyy xxxx se_cmpl compare logical -918 im5 0010 001 i i i i i xxxx se_cmpli compare logical immediate -918 r 0000 0000 1101 xxxx se_extsb extend sign byte -926 r 0000 0000 1111 xxxx se_extsh extend sign halfword -926 r 0000 0000 1100 xxxx se_extzb extend with zeros byte -927 vle instruction index RM0004 985/1176 r 0000 0000 1110 xxxx se_extzh extend with zeros halfword -927 c 0 000 0000 0000 0000 se_illegal illegal -928 c 0 000 0000 0000 0001 se_isync instruction synchronize -929 sd4 1000 i i i i zzzz xxxx se_lbz load byte and zero -930 sd4 1010 i i i i zzzz xxxx se_lhz load halfword and zero -932 im7 0100 1 i i i i i i i xxxx se_li load immediate -933 sd4 1100 i i i i zzzz xxxx se_lwz load word and zero -935 rr 0000 0011 yyyy xxxx se_mfar move from alternate register -937 r 0000 0000 1010 xxxx se_mfctr move from count register -938 r 0000 0000 1000 xxxx se_mflr move from link register -939 rr 0000 0001 yyyy xxxx se_mr move register -940 rr 0000 0010 yyyy xxxx se_mtar move to alternate register -941 r 0000 0000 1011 xxxx se_mtctr move to count register -942 r 0000 0000 1001 xxxx se_mtlr move to link register -943 rr 0000 0101 yyyy xxxx se_mullw multiply low word -945 r 0000 0000 0011 xxxx se_neg negate -946 r 0000 0000 0010 xxxx se_not not -947 rr 0100 0100 yyyy xxxx se_or or -948 c 0 000 0000 0000 1001 se_rfci return from critical interrupt -949 c 0 000 0000 0000 1010 se_rfdi return from debug interrupt -859 c 0 000 0000 0000 1000 se_rfi return from interrupt -950 c 0 000 0000 0000 0010 se_sc system call -954 rr 0100 0010 yyyy xxxx se_slw shift left word -955 im5 0110 110 i i i i i xxxx se_slwi shift left word immediate -955 rr 0100 0001 yyyy xxxx se_sraw shift right algebraic word -956 im5 0110 101 i i i i i xxxx se_srawi shift right algebraic word immediate -956 rr 0100 0000 yyyy xxxx se_srw shift right word -957 im5 0110 100 i i i i i xxxx se_srwi shift right word immediate -957 table 263. 16-bit vle instructions sorted by mnemonic (continued) format 16-bit opcodes (inst 0:15 ) mnemonic instruction page RM0004 vle instruction index 986/1176 table 264 outlines the 32-bit instruction encodings. sd4 1001 i i i i zzzz xxxx se_stb store byte -958 sd4 1011 i i i i zzzz xxxx se_sth store halfword -959 sd4 1101 i i i i zzzz xxxx se_stw store word -961 rr 0000 0110 yyyy xxxx se_sub subtract -962 rr 0000 0111 yyyy xxxx se_subf subtract from -963 im5 0010 010 i i i i i xxxx se_subi subtract immediate -965 im5 0010 011 i i i i i xxxx se_subi. subtract immediate and record -962 table 263. 16-bit vle instructions sorted by mnemonic (continued) format 16-bit opcodes (inst 0:15 ) mnemonic instruction page table 264. 32-bit instruction encodings (by mnemonic) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) x 011111 0 1 0 0 0 01010 0 add add book e x 011111 0 1 0 0 0 01010 1 add. add & record cr book e d 000111t t t t t aaaaa iiiii iiiii iiiii i e_add16i add immediate -897 i16a 011100i i i i i aaaaa 10001 i i i i i iiiii i e_add2i. add (2 operand) immediate and record cr -897 i16a 011100i i i i i aaaaa 10010 i i i i i iiiii i e_add2is add (2 operand) immediate shifted -897 x 011111 0 0 0 0 0 01010 0 addc add carrying book e x 011111 0 0 0 0 0 01010 1 addc. add carrying & record cr book e x 011111 1 0 0 0 0 01010 0 addco add carrying & record ov book e x 011111 1 0 0 0 0 01010 1 addco. add carrying & record ov & cr book e x 011111 0 0 1 0 0 01010 0 adde add extended with ca book e x 011111 0 0 1 0 0 01010 1 adde. add extended with ca & record cr book e vle instruction index RM0004 987/1176 x 011111 1 0 1 0 0 01010 0 addeo add extended with ca & record ov book e x 011111 1 0 1 0 0 01010 1 addeo. add extended with ca & record ov & cr book e sci8 000110t t t t t aaaaa 10000 fssi i iiiii i e_addi add immediate -897 sci8 000110t t t t t aaaaa 10001 fssi i iiiii i e_addi. add immediate and record -897 sci8 000110t t t t t aaaaa 10010 fssi i iiiii i e_addic add immediate carrying -900 sci8 000110t t t t t aaaaa 10011 fssi i iiiii i e_addic. add immediate carrying and record -900 x 011111 0 0 1 1 1 01010 0 addme add to minus one extended with ca book e x 011111 0 0 1 1 1 01010 1 addme. add to minus one extended with ca & record cr book e x 011111 1 0 1 1 1 01010 0 addmeo add to minus one extended with ca & record ov book e x 011111 1 0 1 1 1 01010 1 addmeo. add to minus one extended with ca & record ov & cr book e x 011111 1 1 0 0 0 01010 0 addo add & record ov book e x 011111 1 1 0 0 0 01010 1 addo. add & record ov & cr book e x 011111 0 0 1 1 0 01010 0 addze add to zero extended with ca book e x 011111 0 0 1 1 0 01010 1 addze. add to zero extended with ca & record cr book e x 011111 1 0 1 1 0 01010 0 addzeo add to zero extended with ca & record ov book e table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 988/1176 x 011111 1 0 1 1 0 01010 1 addzeo. add to zero extended with ca & record ov & cr book e x 011111 0 0 0 0 0 11100 0 and and book e x 011111 0 0 0 0 0 11100 1 and. and & record cr book e i16l 011100t t t t t i i i i i 11001 i i i i i iiiii i e_and2i. and (2 operand) immediate & record cr -901 i16l 011100t t t t t i i i i i 11101 i i i i i iiiii i e_and2is. and (2 operand) immediate shifted & record cr -901 x 011111 0 0 0 0 1 11100 0 andc and with complement book e x 011111 0 0 0 0 1 11100 1 andc. and with complement & record cr book e sci8 000110sssss aaaaa 11000 fssi i iiiii i e_andi and immediate -901 sci8 000110sssss aaaaa 11001 fssi i iiiii i e_andi. and immediate and record -901 apu 00010- - - - - - - - - - - ----- ----- ----- - apu reserved for apus bd24 0111100dddd ddddd ddddd ddddd ddddd 0 e_b branch -903 bd15 0111101000o oi i i i ddddd ddddd ddddd 0 e_bc branch conditional -904 bd15 0111101000o oi i i i ddddd ddddd ddddd 1 e_bcl branch conditional & link -904 bd24 0111100dddd ddddd ddddd ddddd ddddd 1 e_bl branch & link -903 x 011111 0 0 0 0 0 00000 / cmp compare book e i16a 011100i i i i i aaaaa 10011 i i i i i iiiii i e_cmp16i compare immediate -912 x 011111 0 0 0 0 0 01110 / e_cmph compare halfword -914 table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 989/1176 i16a 011100i i i i i aaaaa 10110 i i i i i iiiii i e_cmph16i compare halfword immediate -914 x 011111 0 0 0 0 1 01110 / e_cmphl compare halfword logical -916 i16a 011100i i i i i aaaaa 10111 i i i i i iiiii i e_cmphl16 i compare halfword logical immediate -916 sci8 000110000bf aaaaa 10101 fssi i iiiii i e_cmpi compare immediate -912 x 011111 0 0 0 0 1 00000 / cmpl compare logical book e i16a 011100i i i i i aaaaa 10101 i i i i i iiiii i e_cmpl16i compare logical immediate -918 sci8 000110001bf aaaaa 10101 fssi i iiiii i e_cmpli compare logical immediate -918 x 011111 0 0 0 0 0 11010 0 cntlzw count leading zeros word book e x 011111 0 0 0 0 0 11010 1 cntlzw. count leading zeros word & record cr book e xl 011111 0 1 0 0 0 00001 / e_crand condition register and -920 xl 011111 0 0 1 0 0 00001 / e_crandc condition register and with complement -920 xl 011111 0 1 0 0 1 00001 / e_creqv condition register equivalent -920 xl 011111 0 0 1 1 1 00001 / e_crnand condition register nand book e xl 011111 0 0 0 0 1 00001 / e_crnor condition register nor -922 xl 011111 0 1 1 1 0 00001 / e_cror condition register or -923 xl 011111 0 1 1 0 1 00001 / e_crorc condition register or with complement -924 table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 990/1176 xl 011111 0 0 1 1 0 00001 / e_crxor condition register xor -925 x 011111 1 0 1 1 1 10110 / dcba data cache block allocate indexed book e x 011111 0 0 0 1 0 10110 / dcbf data cache block flush indexed book e x 011111 0 1 1 1 0 10110 / dcbi data cache block invalidate indexed book e x 011111 0 0 0 0 1 10110 / dcbst data cache block store indexed book e x 011111 0 1 0 0 0 10110 / dcbt data cache block touch indexed book e x 011111 0 0 1 1 1 10110 / dcbtst data cache block touch for store indexed book e x 011111 1 1 1 1 1 10110 / dcbz data cache block set to zero indexed book e x 011111 0 1 1 1 1 01011 0 divw divide word book e x 011111 0 1 1 1 1 01011 1 divw. divide word & record cr book e x 011111 1 1 1 1 1 01011 0 divwo divide word & record ov book e x 011111 1 1 1 1 1 01011 1 divwo. divide word & record ov & cr book e x 011111 0 1 1 1 0 01011 0 divwu divide word unsigned book e x 011111 0 1 1 1 0 01011 1 divwu. divide word unsigned & record cr book e x 011111 1 1 1 1 0 01011 0 divwuo divide word unsigned & record ov book e table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 991/1176 x 011111 1 1 1 1 0 01011 1 divwuo. divide word unsigned & record ov & cr book e x 011111 0 1 0 0 0 11100 0 eqv equivalent book e x 011111 0 1 0 0 0 11100 1 eqv. equivalent & record cr book e x 011111 1 1 1 0 1 11010 0 extsb extend sign byte book e x 011111 1 1 1 0 1 11010 1 extsb. extend sign byte & record cr book e x 011111 1 1 1 0 0 11010 0 extsh extend sign halfword book e x 011111 1 1 1 0 0 11010 1 extsh. extend sign halfword & record cr book e x 011111 1 1 1 1 0 10110 / icbi instruction cache block invalidate indexed book e x 011111 0 0 0 0 0 10110 / icbt instruction cache block touch indexed book e x 011111 - - - - - 01111 / isel integer select book e d 001100t t t t t aaaaa ddddd ddddd ddddd d e_lbz load byte & zero -930 d8 000110t t t t t aaaaa 00000 000dd ddddd d e_lbzu load byte & zero with update -930 x 011111 0 0 0 1 1 10111 / lbzux load byte & zero with update indexed book e x 011111 0 0 0 1 0 10111 / lbzx load byte & zero indexed book e d 001110t t t t t aaaaa ddddd ddddd ddddd d e_lha load halfword algebraic -931 d8 000110t t t t t aaaaa 00000 011dd ddddd d e_lhau load halfword algebraic with update -931 table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 992/1176 x 011111 0 1 0 1 1 10111 / lhaux load halfword algebraic with update indexed book e x 011111 0 1 0 1 0 10111 / lhax load halfword algebraic indexed book e x 011111 1 1 0 0 0 10110 / lhbrx load halfword byte-reverse indexed book e d 010110t t t t t aaaaa ddddd ddddd ddddd d e_lhz load halfword & zero -932 d8 000110t t t t t aaaaa 00000 001dd ddddd d e_lhzu load halfword & zero with update -932 x 011111 0 1 0 0 1 10111 / lhzux load halfword & zero with update indexed book e x 011111 0 1 0 0 0 10111 / lhzx load halfword & zero indexed book e li20 011100t t t t t i i i i i 0i i i i i i i i i iiiii i e_li load immediate -933 i16l 011100t t t t t i i i i i 11100 i i i i i iiiii i e_lis load immediate shifted -933 d8 000110t t t t t aaaaa 00001 000dd ddddd d e_lmw load multiple word -935 x 011111 0 0 0 0 0 10100 / lwarx load word & reserve indexed book e x 011111 1 0 0 0 0 10110 / lwbrx load word byte- reverse indexed book e d 010100t t t t t aaaaa ddddd ddddd ddddd d e_lwz load word & zero -935 d8 000110t t t t t aaaaa 00000 010dd ddddd d e_lwzu load word & zero with update -935 x 011111 0 0 0 0 1 10111 / lwzux load word & zero with update indexed book e x 011111 0 0 0 0 0 10111 / lwzx load word & zero indexed book e x 011111 1 1 0 1 0 10110 / mbar memory barrier book e table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 993/1176 xl 011111 0 0 0 0 0 10000 / e_mcrf move condition register field -936 x 011111 1 0 0 0 0 00000 / mcrxr move to condition register from xer book e x 011111 0 1 0 0 0 10011 / mfapidi move from apid indirect book e x 011111 0 0 0 0 0 10011 / mfcr move from condition register book e xfx 011111 0 1 0 1 0 00011 / mfdcr move from device control register book e x 011111 0 0 0 1 0 10011 / mfmsr move from machine state register book e xfx 011111 0 1 0 1 0 10011 / mfspr move from special purpose register book e x 011111 1 0 0 1 0 10110 / msync memory synchronize book e xfx 011111 0 0 1 0 0 10000 / mtcrf move to condition register fields book e xfx 011111 0 1 1 1 0 00011 / mtdcr move to device control register book e x 011111 0 0 1 0 0 10010 / mtmsr move to machine state register book e xfx 011111 0 1 1 1 0 10011 / mtspr move to special purpose register book e x 011111 / 0 0 1 0 01011 0 mulhw multiply high word book e x 011111 / 0 0 1 0 01011 1 mulhw. multiply high word & record cr book e x 011111 / 0 0 0 0 01011 0 mulhwu multiply high word unsigned book e table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 994/1176 x 011111 / 0 0 0 0 01011 1 mulhwu. multiply high word unsigned & record book e i16a 011100i i i i i aaaaa 10100 i i i i i iiiii i e_mull2i multiply low word (2 operand) immediate -944 sci8 000110t t t t t aaaaa 10100 fssi i iiiii i e_mulli multiply low immediate -944 x 011111 0 0 1 1 1 01011 0 mullw multiply low word book e x 011111 0 0 1 1 1 01011 1 mullw. multiply low word & record cr book e x 011111 1 0 1 1 1 01011 0 mullwo multiply low word & record ov book e x 011111 1 0 1 1 1 01011 1 mullwo. multiply low word & record ov & cr book e x 011111 0 1 1 1 0 11100 0 nand nand book e x 011111 0 1 1 1 0 11100 1 nand. nand & record cr book e x 011111 0 0 0 1 1 01000 0 neg negate book e x 011111 0 0 0 1 1 01000 1 neg. negate & record cr book e x 011111 1 0 0 1 1 01000 0 nego negate & record ov book e x 011111 1 0 0 1 1 01000 1 nego. negate & record ov & record cr book e x 011111 0 0 0 1 1 11100 0 nor nor book e x 011111 0 0 0 1 1 11100 1 nor. nor & record cr book e x 011111 0 1 1 0 1 11100 0 or or book e x 011111 0 1 1 0 1 11100 1 or. or & record cr book e table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 995/1176 i16l 011100t t t t t i i i i i 11000 i i i i i iiiii i e_or2i or (2 operand) immediate -948 i16l 011100t t t t t i i i i i 11010 i i i i i iiiii i e_or2is or (2 operand) immediate shifted -948 x 011111 0 1 1 0 0 11100 0 orc or with complement book e x 011111 0 1 1 0 0 11100 1 orc. or with complement & record cr book e sci8 000110sssss aaaaa 11010 fssi i iiiii i e_ori or immediate -951 sci8 000110sssss aaaaa 11011 fssi i iiiii i e_ori. or immediate and record -951 x 1111- - reserved x 011111 0 1 0 0 0 11000 0 e_rlw rotate left word -951 x 011111 0 1 0 0 0 11000 1 e_rlw. rotate left word & record cr -951 x 011111 0 1 0 0 1 11000 0 e_rlwi rotate left word immediate -952 x 011111 0 1 0 0 1 11000 1 e_rlwi. rotate left word immediate & record cr -952 rlwi 011101sssss aaaaa hhhhh bbbbb eeeee 0 e_rlwimi rotate left word immed then mask insert -953 rlwi 011101sssss aaaaa hhhhh bbbbb eeeee 1 e_rlwinm rotate left word immed then and with mask -955 x 011111 0 0 0 0 0 11000 0 slw shift left word book e x 011111 0 0 0 0 0 11000 1 slw. shift left word & record cr book e x 011111 0 0 0 0 1 11000 0 e_slwi shift left word immediate -935 x 011111 0 0 0 0 1 11000 1 e_slwi. shift left word immediate & record cr -935 table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 996/1176 x 011111 1 1 0 0 0 11000 0 sraw shift right algebraic word book e x 011111 1 1 0 0 0 11000 1 sraw. shift right algebraic word & record cr book e x 011111 1 1 0 0 1 11000 0 srawi shift right algebraic word immediate book e x 011111 1 1 0 0 1 11000 1 srawi. shift right algebraic word immediate & record cr book e x 011111 1 0 0 0 0 11000 0 srw shift right word book e x 011111 1 0 0 0 0 11000 1 srw. shift right word & record cr book e x 011111 1 0 0 0 1 11000 0 e_srwi shift right word immediate -957 x 011111 1 0 0 0 1 11000 1 e_srwi. shift right word immediate & record cr -957 d 001101t t t t t aaaaa ddddd ddddd ddddd d e_stb store byte -958 d8 000110t t t t t aaaaa 00000 100dd ddddd d e_stbu store byte with update -958 x 011111 0 0 1 1 1 10111 / stbux store byte with update indexed book e x 011111 0 0 1 1 0 10111 / stbx store byte indexed book e d 010111t t t t t aaaaa ddddd ddddd ddddd d e_sth store halfword -959 x 011111 1 1 1 0 0 10110 / sthbrx store halfword byte-reverse indexed book e d8 000110t t t t t aaaaa 00000 101dd ddddd d e_sthu store halfword with update -959 x 011111 0 1 1 0 1 10111 / sthux store halfword with update indexed book e x 011111 0 1 1 0 0 10111 / sthx store halfword indexed book e d8 000110t t t t t aaaaa 00001 001dd ddddd d e_stmw store multiple word -960 table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 997/1176 x 011111 1 0 1 1 0 10101 / stswi store string word immediate book e x 011111 1 0 1 0 0 10101 / stswx store string word indexed book e d 010101t t t t t aaaaa ddddd ddddd ddddd d e_stw store word -961 x 011111 1 0 1 0 0 10110 / stwbrx store word byte-reverse indexed book e x 011111 0 0 1 0 0 10110 1 stwcx. store word conditional indexed & record cr book e d8 000110t t t t t aaaaa 00000 110dd ddddd d e_stwu store word with update -961 x 011111 0 0 1 0 1 10111 / stwux store word with update indexed book e x 011111 0 0 1 0 0 10111 / stwx store word indexed book e x 011111 0 0 0 0 1 01000 0 subf subtract from book e x 011111 0 0 0 0 1 01000 1 subf. subtract from & record cr book e x 011111 0 0 0 0 0 01000 0 subfc subtract from carrying book e x 011111 0 0 0 0 0 01000 1 subfc. subtract from carrying & record cr book e x 011111 1 0 0 0 0 01000 0 subfco subtract from carrying & record ov book e x 011111 1 0 0 0 0 01000 1 subfco. subtract from carrying & record ov & cr book e x 011111 0 0 1 0 0 01000 0 subfe subtract from extended with ca book e x 011111 0 0 1 0 0 01000 1 subfe. subtract from extended with ca & record cr book e table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 998/1176 x 011111 1 0 1 0 0 01000 0 subfeo subtract from extended with ca & record ov book e x 011111 1 0 1 0 0 01000 1 subfeo. subtract from extended with ca & record ov & cr book e sci8 000110t t t t t aaaaa 10110 fssi i iiiii i e_subfic subtract from immediate carrying -964 sci8 000110t t t t t aaaaa 10111 fssi i iiiii i e_subfic. subtract from immediate and record -964 x 011111 0 0 1 1 1 01000 0 subfme subtract from minus one extended with ca book e x 011111 0 0 1 1 1 01000 1 subfme. subtract from minus one extended with ca & record cr book e x 011111 1 0 1 1 1 01000 0 subfmeo subtract from minus one extended with ca & record ov book e x 011111 1 0 1 1 1 01000 1 subfmeo. subtract from minus one extended with ca & record ov & cr book e x 011111 1 0 0 0 1 01000 0 subfo subtract from & record ov book e x 011111 1 0 0 0 1 01000 1 subfo. subtract from & record ov & cr book e x 011111 0 0 1 1 0 01000 0 subfze subtract from zero extended with ca book e x 011111 0 0 1 1 0 01000 1 subfze. subtract from zero extended with ca & record cr book e table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 999/1176 x 011111 1 0 1 1 0 01000 0 subfzeo subtract from zero extended with ca & record ov book e x 011111 1 0 1 1 0 01000 1 subfzeo. subtract from zero extended with ca & record ov & cr book e x 011111 1 1 0 0 0 10010 / tlbivax tlb invalidate virtual address indexed book e x 011111 1 1 1 0 1 10010 / tlbre tlb read entry book e x 011111 1 1 1 0 0 10010 ? tlbsx tlb search indexed book e x 011111 1 0 0 0 1 10110 / tlbsync tlb synchronize book e x 011111 1 1 1 1 0 10010 / tlbwe tlb write entry book e x 011111 0 0 0 0 0 00100 / tw tr a p wo r d book e x 011111 0 0 1 0 0 00011 / wrtee write external enable book e x 011111 0 0 1 0 1 00011 / wrteei write external enable immediate book e x 011111 0 1 0 0 1 11100 0 xor xor book e x 011111 0 1 0 0 1 11100 1 xor. xor & record cr book e sci8 000110sssss aaaaa 11100 fssi i iiiii i e_xori xor immediate -966 sci8 000110sssss aaaaa 11101 fssi i iiiii i e_xori. xor immediate and record -966 table 264. 32-bit instruction encodings (by mnemonic) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1000/1176 14.3 instruction index sorted by opcode table 265 lists all the 16-bit power*embedded instructions, sorted by opcode. table 265. instruction index sorted by opcode format 16-bit opcodes (inst 0:15 ) mnemonic instruction page c 0000 0000 0000 0001 se_isync instruction synchronize -929 c 0000 0000 0000 0010 se_sc system call -954 c 0000 0000 0000 0100 se_blr branch to link register -908 c 0000 0000 0000 0101 se_blrl branch to link register & link -908 c 0000 0000 0000 0110 se_bctr branch to count register -906 c 0000 0000 0000 0111 se_bctrl branch to count register & link -906 c 0000 0000 0000 1000 se_rfi return from interrupt -950 c 0000 0000 0000 1001 se_rfci return from critical interrupt -949 c 0000 0000 0000 1010 se_rfdi return from debug interrupt -859 c 0000 0000 0000 1011 unimp c 0000 0000 0000 11 - - unimp c 0000 0000 0001 ---- unimp r 0000 0000 0010 xxxx se_not not -947 r 0000 0000 0011 xxxx unimp r 0000 0000 0100 xxxx se_lmw load multiple word -934 r 0000 0000 0101 xxxx se_stmw store multiple word -960 r 0000 0000 011 - xxxx unimp r 0000 0000 1000 xxxx se_mflr move from link register -939 r 0000 0000 1001 xxxx se_mtlr move to link register -943 r 0000 0000 1010 xxxx se_mfctr move from count register -938 r 0000 0000 1011 xxxx se_mtctr move to count register -942 r 0000 0000 1100 xxxx se_extzb extend with zeros byte -927 r 0000 0000 1101 xxxx se_extsb extend sign byte -926 r 0000 0000 1110 xxxx se_extzh extend with zeros halfword -927 r 0000 0000 1111 xxxx se_extsh extend sign halfword -926 r 0000 0001 ---- xxxx unimp vle instruction index RM0004 1001/1176 rr 0000 0010 yyyy xxxx se_mtar move to alternate register -941 rr 0000 0011 yyyy xxxx se_mfar move from alternate register -937 rr 0000 0100 yyyy xxxx se_add add -897 rr 0000 0101 yyyy xxxx unimp rr 0000 0110 yyyy xxxx se_sub subtract -962 rr 0000 0111 yyyy xxxx se_sub. subtract and record -962 rr 0000 1000 yyyy xxxx unimp rr 0000 1001 yyyy xxxx unimp rr 0000 1010 yyyy xxxx se_mullw multiply low word -945 rr 0000 1011 yyyy xxxx se_mr move register -940 rr 0000 1100 yyyy xxxx se_cmp compare -912 rr 0000 1101 yyyy xxxx se_cmpl compare logical -918 rr 0000 1110 yyyy xxxx se_xor xor -966 rr 0000 1111 yyyy xxxx se_or or -948 im5 0010 000 i i i i i xxxx se_addi add immediate -897 im5 0010 001 i i i i i xxxx se_cmpli compare logical immediate -918 im5 0010 010 i i i i i xxxx se_subi subtract immediate -965 im5 0010 011 i i i i i xxxx se_subi. subtract immediate and record -965 im5 0010 100 i i i i i xxxx se_subfic subtract from immediate carrying -964 im5 0010 101 i i i i i xxxx se_cmpi compare immediate -912 im5 0010 110 i i i i i xxxx se_bmask i bit mask generate immediate -909 im5 0010 111 i i i i i xxxx se_andi and immediate -901 rr 0100 0000 yyyy xxxx se_sraw shift right algebraic word -956 rr 0100 0001 yyyy xxxx se_rlw rotate left word -951 rr 0100 0010 yyyy xxxx se_srw shift right word -957 rr 0100 0011 yyyy xxxx se_slw shift left word -955 rr 0100 0100 yyyy xxxx se_subf subtract from -963 rr 0100 0101 yyyy xxxx se_andc and with complement -901 rr 0100 0110 yyyy xxxx se_and and -901 rr 0100 0111 yyyy xxxx se_and. and and record -901 table 265. instruction index sorted by opcode (continued) format 16-bit opcodes (inst 0:15 ) mnemonic instruction page RM0004 vle instruction index 1002/1176 im7 0100 1 i i i i i i i xxxx se_li load immediate -933 im5 0110 000 i i i i i xxxx se_bclri bit clear immediate -905 im5 0110 001 i i i i i xxxx se_bgeni bit generate immediate -907 im5 0110 010 i i i i i xxxx se_bseti bit set immediate -910 im5 0110 011 i i i i i xxxx se_btsti bit test immediate -911 im5 0110 100 i i i i i xxxx se_rlwi rotate left word immediate -951 im5 0110 101 i i i i i xxxx se_srawi shift right algebraic word immediate -956 im5 0110 110 i i i i i xxxx se_slwi shift left word immediate -955 im5 0110 111 i i i i i xxxx se_srwi shift right word immediate -957 sd4 1000 i i i i zzzz xxxx se_lbz load byte and zero -930 sd4 1001 i i i i zzzz xxxx se_stb store byte -958 sd4 1010 i i i i zzzz xxxx se_lhz load halfword and zero -932 sd4 1011 i i i i zzzz xxxx se_sth store halfword -959 sd4 1100 i i i i zzzz xxxx se_lwz load word and zero -935 sd4 1101 i i i i zzzz xxxx se_stw store word -961 unimp1110 ---- ---- ---- unimp b8 1111 0o i i dddd dddd se_bc branch conditional -904 b8 1111 1000 dddd dddd se_b branch -903 b8 1111 1001 dddd dddd se_bl branch and link -903 unimp1111 101 - ---- ---- unimp unimp1111 11 - - ---- ---- unimp table 265. instruction index sorted by opcode (continued) format 16-bit opcodes (inst 0:15 ) mnemonic instruction page vle instruction index RM0004 1003/1176 table 266 outlines the 32-bit instruction encodings. table 266. 32-bit instruction encodings format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) a p u 0 - 0 1 - - ????? ????? ?????- - - - - - - - - - - apu reserved for apus d14 001100ttttt aaaaa 00dddddddd ddddd d e_lbz load byte & zero -930 d14 001100ttttt aaaaa 01dddddddd ddddd d e_lhz load halfword & zero -932 d14 001100ttttt aaaaa 10dddddddd ddddd d e_lwz load word & zero -936 d14 001100ttttt aaaaa 11dddddddd ddddd d e_ld load doubleword & zero (reserved for 64b gpr) d14 001101ttttt aaaaa 00dddddddd ddddd d e_stb store byte -958 d14 001101ttttt aaaaa 01dddddddd ddddd d e_sth store halfword -959 d14 001101ttttt aaaaa 10dddddddd ddddd d e_stw store word -961 d14 001101ttttt aaaaa 11dddddddd ddddd d e_std store doubleword (reserved for 64b gpr) d8 001110ttttt aaaaa 00000000dd ddddd d e_lbzu load byte & zero with update -930 d8 001110ttttt aaaaa 00000001dd ddddd d e_lhzu load halfword & zero with update -932 d8 001110ttttt aaaaa 00000010dd ddddd d e_lwzu load word & zero with update -935 d8 001110ttttt aaaaa 00000011dd ddddd d e_ldu load doubleword with update (reserved for 64b gpr) d8 001110ttttt aaaaa 00000100dd ddddd d e_stbu store byte with update -958 d8 001110ttttt aaaaa 00000101dd ddddd d e_sthu store halfword with update -959 d8 001110ttttt aaaaa 00000110dd ddddd d e_stwu store word with update -961 d8 001110ttttt aaaaa 00000111dd ddddd d e_stdu store doubleword with update (reserved for 64b gpr) d8 001110ttttt aaaaa 00001000dd ddddd d e_lmw load multiple word -934 d8 001110ttttt aaaaa 00001001dd ddddd d e_stmw store multiple word -960 d8 001110ttttt aaaaa 00001010dd ddddd d e_lha load halfword algebraic -931 d8 001110ttttt aaaaa 00001011dd ddddd d e_lhau load halfword algebraic with update -931 RM0004 vle instruction index 1004/1176 unimp 001110ttttt aaaaa 000011- - dd ddddd d unimp unimp 001110ttttt aaaaa 0001?- - - - - - - - - - - unimp unimp 001110ttttt aaaaa 001??- - - - - - - - - - - unimp sci8 00111000000 aaaaa 010bffssi i i i i i i i e_cmpi compare immediate -912 sci8 00111000000 aaaaa 011bffssi i i i i i i i e_cmpli compare logical immediate -918 sci8 001110ttttt aaaaa 10000fssi i i i i i i i e_addi add immediate -897 sci8 001110ttttt aaaaa 10001fssi i i i i i i i e_addic add immediate carrying -900 sci8 001110ttttt aaaaa 10010fssi i i i i i i i e_andi and immediate -901 sci8 001110ttttt aaaaa 10011fssi i i i i i i i e_ori or immediate -951 sci8 001110ttttt aaaaa 10100fssi i i i i i i i e_subfic subtract from immediate carrying -964 sci8 001110ttttt aaaaa 10101fssi i i i i i i i unimp sci8 001110ttttt aaaaa 10110fssi i i i i i i i e_mulli multiply low immediate -944 sci8 001110ttttt aaaaa 10111fssi i i i i i i i e_xori xor immediate -966 sci8 001110ttttt aaaaa 11000fssi i i i i i i i e_addi. add immediate and record -897 sci8 001110ttttt aaaaa 11001fssi i i i i i i i e_addic. add immediate carrying and record -900 sci8 001110ttttt aaaaa 11010fssi i i i i i i i e_andi. and immediate and record -901 sci8 001110ttttt aaaaa 11011fssi i i i i i i i e_ori. or immediate and record -951 sci8 001110ttttt aaaaa 11100fssi i i i i i i i e_subfic. subtract from immediate and record -964 sci8 001110ttttt aaaaa 10101fssi i i i i i i i unimp sci8 001110ttttt aaaaa 11110fssi i i i i i i i e_mulli. multiply low immediate and record -944 sci8 001110ttttt aaaaa 11111fssi i i i i i i i e_xori. xor immediate and record -966 d 001111ttttt aaaaa iiiiiiiiii iiiii i e_add16i add immediate -898 li20 011100ttttt 0 iiii iiiiiiiiii iiiii i e_li load immediate -933 li20 011100ttttt 1 iiii iiiiiiiiii iiiii i e_lis load immediate shifted -933 table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1005/1176 rlwi 011101sssss aaaaa hhhhhbbbbb eeeee 0 e_rlwimi. rotate left word immed then mask insert & record cr -952 rlwi 011101sssss aaaaa hhhhhbbbbb eeeee 1 e_rlwinm. rotate left word immed then and with mask & record cr -953 bd24 0111100dddd ddddd dddddddddd ddddd 0 e_b branch -903 bd24 0111100dddd ddddd dddddddddd ddddd 1 e_bl branch & link -903 bd15 0111101000o o iiii dddddddddd ddddd 0 e_bc branch conditional -904 bd15 0111101000o o iiii dddddddddd ddddd 1 e_bcl branch conditional & link -904 x 011111 ----- ----- ---------- 01111 / isel integer select book e x 011111 ----- ----- ----- / 0000 01011 0 mulhwu multiply high word unsigned book e x 011111 ----- ----- ----- / 0000 01011 1 mulhwu. multiply high word unsigned & record book e x 011111 ----- ----- ----- / 0010 01011 0 mulhw multiply high word book e x 011111 ----- ----- ----- / 0010 01011 1 mulhw. multiply high word & record cr book e x 011111 ----- ----- ----- 00000 00000 / cmp compare book e x 011111 ----- ----- ----- 00000 00100 / tw trap word book e x 011111 ----- ----- ----- 00000 01000 0 subfc subtract from carrying book e x 011111 ----- ----- ----- 00000 01000 1 subfc. subtract from carrying & record cr book e x 011111 ----- ----- ----- 00000 01010 0 addc add carrying book e x 011111 ----- ----- ----- 00000 01010 1 addc. add carrying & record cr book e x 011111 ----- ----- ----- 00000 10011 / mfcr move from condition register book e x 011111 ----- ----- ----- 00000 10100 / lwarx load word & reserve indexed book e x 011111 ----- ----- ----- 00000 10110 / icbt instruction cache block touch indexed book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1006/1176 x 011111 ----- ----- ----- 00000 10111 / lwzx load word & zero indexed book e x 011111 ----- ----- ----- 00000 11000 0 slw shift left word book e x 011111 ----- ----- ----- 00000 11000 1 slw. shift left word & record cr book e x 011111 ----- ----- ----- 00000 11010 0 cntlzw count leading zeros word book e x 011111 ----- ----- ----- 00000 11010 1 cntlzw. count leading zeros word & record cr book e x 011111 ----- ----- ----- 00000 11100 0 and and book e x 011111 ----- ----- ----- 00000 11100 1 and. and & record cr book e x 011111 ----- ----- ----- 00001 00000 / cmpl compare logical book e x 011111 ----- ----- ----- 00001 01000 0 subf subtract from book e x 011111 ----- ----- ----- 00001 01000 1 subf. subtract from & record cr book e x 011111 ----- ----- ----- 00001 10110 / dcbst data cache block store indexed book e x 011111 ----- ----- ----- 00001 10111 / lwzux load word & zero with update indexed book e x 011111 ----- ----- ----- 00001 11100 0 andc and with complement book e x 011111 ----- ----- ----- 00001 11100 1 andc. and with complement & record cr book e x 011111 ----- ----- ----- 00010 10011 / mfmsr move from machine state register book e x 011111 ----- ----- ----- 00010 10110 / dcbf data cache block flush indexed book e x 011111 ----- ----- ----- 00010 10111 / lbzx load byte & zero indexed book e x 011111 ----- ----- ----- 00011 01000 0 neg negate book e x 011111 ----- ----- ----- 00011 01000 1 neg. negate & record cr book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1007/1176 x 011111 ----- ----- ----- 00011 10111 / lbzux load byte & zero with update indexed book e x 011111 ----- ----- ----- 00011 11100 0 nor nor book e x 011111 ----- ----- ----- 00011 11100 1 nor. nor & record cr book e x 011111 ----- ----- ----- 00100 00011 / wrtee write external enable book e x 011111 ----- ----- ----- 00100 01000 0 subfe subtract from extended with ca book e x 011111 ----- ----- ----- 00100 01000 1 subfe. subtract from extended with ca & record cr book e x 011111 ----- ----- ----- 00100 01010 0 adde add extended with ca book e x 011111 ----- ----- ----- 00100 01010 1 adde. add extended with ca & record cr book e xfx 011111 ----- ----- ----- 00100 10000 / mtcrf move to condition register fields book e x 011111 ----- ----- ----- 00100 10010 / mtmsr move to machine state register book e x 011111 ----- ----- ----- 00100 10110 1 stwcx. store word conditional indexed & record cr book e x 011111 ----- ----- ----- 00100 10111 / stwx store word indexed book e x 011111 ----- ----- ----- 00101 00011 / wrteei write external enable immediate book e x 011111 ----- ----- ----- 00101 10111 / stwux store word with update indexed book e x 011111 ----- ----- ----- 00110 01000 0 subfze subtract from zero extended with ca book e x 011111 ----- ----- ----- 00110 01000 1 subfze. subtract from zero extended with ca & record cr book e x 011111 ----- ----- ----- 00110 01010 0 addze add to zero extended with ca book e x 011111 ----- ----- ----- 00110 01010 1 addze. add to zero extended with ca & record cr book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1008/1176 x 011111 ----- ----- ----- 00110 10111 / stbx store byte indexed book e x 011111 ----- ----- ----- 00111 01000 0 subfme subtract from minus one extended with ca book e x 011111 ----- ----- ----- 00111 01000 1 subfme. subtract from minus one extended with ca & record cr book e x 011111 ----- ----- ----- 00111 01010 0 addme add to minus one extended with ca book e x 011111 ----- ----- ----- 00111 01010 1 addme. add to minus one extended with ca & record cr book e x 011111 ----- ----- ----- 00111 01011 0 mullw multiply low word book e x 011111 ----- ----- ----- 00111 01011 1 mullw. multiply low word & record cr book e x 011111 ----- ----- ----- 00111 10110 / dcbtst data cache block touch for store indexed book e x 011111 ----- ----- ----- 00111 10111 / stbux store byte with update indexed book e x 011111 ----- ----- ----- 01000 01010 0 add add book e x 011111 ----- ----- ----- 01000 01010 1 add. add & record cr book e x 011111 ----- ----- ----- 01000 10011 / mfapidi move from apid indirect book e x 011111 ----- ----- ----- 01000 10110 / dcbt data cache block touch indexed book e x 011111 ----- ----- ----- 01000 10111 / lhzx load halfword & zero indexed book e x 011111 ----- ----- ----- 01000 11100 0 eqv equivalent book e x 011111 ----- ----- ----- 01000 11100 1 eqv. equivalent & record cr book e x 011111 ----- ----- ----- 01001 10111 / lhzux load halfword & zero with update indexed book e x 011111 ----- ----- ----- 01001 11100 0 xor xor book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1009/1176 x 011111 ----- ----- ----- 01001 11100 1 xor. xor & record cr book e xfx 011111 ----- ----- ----- 01010 00011 / mfdcr move from device control register book e xfx 011111 ----- ----- ----- 01010 10011 / mfspr move from special purpose register book e x 011111 ----- ----- ----- 01010 10111 / lhax load halfword algebraic indexed book e x 011111 ----- ----- ----- 01011 10111 / lhaux load halfword algebraic with update indexed book e x 011111 ----- ----- ----- 01100 10111 / sthx store halfword indexed book e x 011111 ----- ----- ----- 01100 11100 0 orc or with complement book e x 011111 ----- ----- ----- 01100 11100 1 orc. or with complement & record cr book e x 011111 ----- ----- ----- 01101 10111 / sthux store halfword with update indexed book e x 011111 ----- ----- ----- 01101 11100 0 or or book e x 011111 ----- ----- ----- 01101 11100 1 or. or & record cr book e xfx 011111 ----- ----- ----- 01110 00011 / mtdcr move to device control register book e x 011111 ----- ----- ----- 01110 01011 0 divwu divide word unsigned book e x 011111 ----- ----- ----- 01110 01011 1 divwu. divide word unsigned & record cr book e xfx 011111 ----- ----- ----- 01110 10011 / mtspr move to special purpose register book e x 011111 ----- ----- ----- 01110 10110 / dcbi data cache block invalidate indexed book e x 011111 ----- ----- ----- 01110 11100 0 nand nand book e x 011111 ----- ----- ----- 01110 11100 1 nand. nand & record cr book e x 011111 ----- ----- ----- 01111 01011 0 divw divide word book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1010/1176 x 011111 ----- ----- ----- 01111 01011 1 divw. divide word & record cr book e x 011111 ----- ----- ----- 10000 00000 / mcrxr move to condition register from xer book e x 011111 ----- ----- ----- 10000 01000 0 subfco subtract from carrying & record ov book e x 011111 ----- ----- ----- 10000 01000 1 subfco. subtract from carrying & record ov & cr book e x 011111 ----- ----- ----- 10000 01010 0 addco add carrying & record ov book e x 011111 ----- ----- ----- 10000 01010 1 addco. add carrying & record ov & cr book e x 011111 ----- ----- ----- 10000 10110 / lwbrx load word byte- reverse indexed book e x 011111 ----- ----- ----- 10000 11000 0 srw shift right word book e x 011111 ----- ----- ----- 10000 11000 1 srw. shift right word & record cr book e x 011111 ----- ----- ----- 10001 01000 0 subfo subtract from & record ov book e x 011111 ----- ----- ----- 10001 01000 1 subfo. subtract from & record ov & cr book e x 011111 ----- ----- ----- 10001 10110 / tlbsync tlb synchronize book e x 011111 ----- ----- ----- 10010 10110 / msync memory synchronize book e x 011111 ----- ----- ----- 10011 01000 0 nego negate & record ov book e x 011111 ----- ----- ----- 10011 01000 1 nego. negate & record ov & record cr book e x 011111 ----- ----- ----- 10100 01000 0 subfeo subtract from extended with ca & record ov book e x 011111 ----- ----- ----- 10100 01000 1 subfeo. subtract from extended with ca & record ov & cr book e x 011111 ----- ----- ----- 10100 01010 0 addeo add extended with ca & record ov book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1011/1176 x 011111 ----- ----- ----- 10100 01010 1 addeo. add extended with ca & record ov & cr book e x 011111 ----- ----- ----- 10100 10101 / stswx store string word indexed book e x 011111 ----- ----- ----- 10100 10110 / stwbrx store word byte- reverse indexed book e x 011111 ----- ----- ----- 10110 01000 0 subfzeo subtract from zero extended with ca & record ov book e x 011111 ----- ----- ----- 10110 01000 1 subfzeo. subtract from zero extended with ca & record ov & cr book e x 011111 ----- ----- ----- 10110 01010 0 addzeo add to zero extended with ca & record ov book e x 011111 ----- ----- ----- 10110 01010 1 addzeo. add to zero extended with ca & record ov & cr book e x 011111 ----- ----- ----- 10110 10101 / stswi store string word immediate book e x 011111 ----- ----- ----- 10111 01000 0 subfmeo subtract from minus one extended with ca & record ov book e x 011111 ----- ----- ----- 10111 01000 1 subfmeo. subtract from minus one extended with ca & record ov & cr book e x 011111 ----- ----- ----- 10111 01010 0 addmeo add to minus one extended with ca & record ov book e x 011111 ----- ----- ----- 10111 01010 1 addmeo. add to minus one extended with ca & record ov & cr book e x 011111 ----- ----- ----- 10111 01011 0 mullwo multiply low word & record ov book e x 011111 ----- ----- ----- 10111 01011 1 mullwo. multiply low word & record ov & cr book e x 011111 ----- ----- ----- 10111 10110 / dcba data cache block allocate indexed book e x 011111 ----- ----- ----- 11000 01010 0 addo add & record ov book e x 011111 ----- ----- ----- 11000 01010 1 addo. add & record ov & cr book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1012/1176 x 011111 ----- ----- ----- 11000 10010 / tlbivax tlb invalidate virtual address indexed book e x 011111 ----- ----- ----- 11000 10110 / lhbrx load halfword byte- reverse indexed book e x 011111 ----- ----- ----- 11000 11000 0 sraw shift right algebraic word book e x 011111 ----- ----- ----- 11000 11000 1 sraw. shift right algebraic word & record cr book e x 011111 ----- ----- ----- 11001 11000 0 srawi shift right algebraic word immediate book e x 011111 ----- ----- ----- 11001 11000 1 srawi. shift right algebraic word immediate & record cr book e x 011111 ----- ----- ----- 11010 10110 / mbar memory barrier book e x 011111 ----- ----- ----- 11100 10010 ? tlbsx tlb search indexed book e x 011111 ----- ----- ----- 11100 10110 / sthbrx store halfword byte- reverse indexed book e x 011111 ----- ----- ----- 11100 11010 0 extsh extend sign halfword book e x 011111 ----- ----- ----- 11100 11010 1 extsh. extend sign halfword & record cr book e x 011111 ----- ----- ----- 11101 10010 / tlbre tlb read entry book e x 011111 ----- ----- ----- 11101 11010 0 extsb extend sign byte book e x 011111 ----- ----- ----- 11101 11010 1 extsb. extend sign byte & record cr book e x 011111 ----- ----- ----- 11110 01011 0 divwuo divide word unsigned & record ov book e x 011111 ----- ----- ----- 11110 01011 1 divwuo. divide word unsigned & record ov & cr book e x 011111 ----- ----- ----- 11110 10010 / tlbwe tlb write entry book e x 011111 ----- ----- ----- 11110 10110 / icbi instruction cache block invalidate indexed book e x 011111 ----- ----- ----- 11111 01011 0 divwo divide word & record ov book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1013/1176 x 011111 ----- ----- ----- 11111 01011 1 divwo. divide word & record ov & cr book e x 011111 ----- ----- ----- 11111 10110 / dcbz data cache block set to zero indexed book e table 266. 32-bit instruction encodings (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1014/1176 14.4 instruction index sorted by mnemonic table 267 lists all the 16-bit power*embedded instructions, sorted by mnemonic. table 267. instruction index sorted by mnemonic form at 16-bit opcodes (inst 0:15 ) mnemonic instruction page rr 0000 0100 yyyy xxxx se_add add -897 im5 0 0 1 0 0 0 0 i i i i i x x x x se_addi add immediate -898 rr 0100 0110 yyyy xxxx se_and and -901 rr 0100 0111 yyyy xxxx se_and. and and record -901 rr 0100 0101 yyyy xxxx se_andc and with complement -901 im5 0 0 1 0 1 1 1 i i i i i x x x x se_andi and immediate -901 b8 1 111 0o i i dddd dddd se_bc branch conditional -904 im5 0 1 1 0 0 0 0 i i i i i x x x x se_bclri bit clear immediate -905 c0000000000000110 se_bctr branch to count register -906 c0000000000000111 se_bctrl branch to count register & link -906 im5 0 1 1 0 0 0 1 i i i i i x x x x se_bgeni bit generate immediate -907 b8 1 111 1001 dddd dddd se_bl branch and link -903 c0000000000000100 se_blr branch to link register -908 c0000000000000101 se_blrl branch to link register & link -908 im5 0 0 1 0 1 1 0 i i i i i x x x x se_bmaski bit mask generate immediate -909 b8 1 111 1000 dddd dddd se_b branch -903 im5 0 1 1 0 0 1 0 i i i i i x x x x se_bseti bit set immediate -909 im5 0 1 1 0 0 1 1 i i i i i x x x x se_btsti bit test immediate -911 rr 0000 1100 yyyy xxxx se_cmp compare -912 im5 0 0 1 0 1 0 1 i i i i i x x x x se_cmpi compare immediate -912 rr 0000 1101 yyyy xxxx se_cmpl compare logical -918 im5 0 0 1 0 0 0 1 i i i i i x x x x se_cmpli compare logical immediate -918 r000000001101xxxx se_extsb extend sign byte -926 r000000001111xxxx se_extsh extend sign halfword -926 r000000001100xxxx se_extzb extend with zeros byte -927 r000000001110xxxx se_extzh extend with zeros halfword -927 c0000000000000001 se_isync instruction synchronize -929 vle instruction index RM0004 1015/1176 sd41000 i i i i zzzz xxxx se_lbz load byte and zero -930 r000000000100xxxx se_lmw load multiple word -934 sd41010 i i i i zzzz xxxx se_lhz load halfword and zero -932 im70100 1iii iiii xxxx se_li load immediate -933 sd41100 i i i i zzzz xxxx se_lwz load word and zero -935 rr 0000 0011 yyyy xxxx se_mfar move from alternate register -937 r000000001010xxxx se_mfctr move from count register -938 r000000001000xxxx se_mflr move from link register -939 rr 0000 1011 yyyy xxxx se_mr move register -940 rr 0000 0010 yyyy xxxx se_mtar move to alternate register -941 r000000001011xxxx se_mtctr move to count register -942 r000000001001xxxx se_mtlr move to link register -943 rr 0000 1010 yyyy xxxx se_mullw multiply low word -945 r000000000010xxxx se_not not -947 rr 0000 1111 yyyy xxxx se_or or -948 c0000000000001001 se_rfci return from critical interrupt -949 c0000000000001010 se_rfdi return from debug interrupt -859 c0000000000001000 se_rfi return from interrupt -950 rr 0100 0001 yyyy xxxx se_rlw rotate left word -951 im5 0 1 1 0 1 0 0 i i i i i x x x x se_rlwi rotate left word immediate -951 c0000000000000010 se_sc system call -954 rr 0100 0011 yyyy xxxx se_slw shift left word -955 im5 0 1 1 0 1 1 0 i i i i i x x x x se_slwi shift left word immediate -955 rr 0100 0000 yyyy xxxx se_sraw shift right algebraic word -956 im5 0 1 1 0 1 0 1 i i i i i x x x x se_srawi shift right algebraic word immediate -956 rr 0100 0010 yyyy xxxx se_srw shift right word -957 im5 0 1 1 0 1 1 1 i i i i i x x x x se_srwi shift right word immediate -957 table 267. instruction index sorted by mnemonic (continued) form at 16-bit opcodes (inst 0:15 ) mnemonic instruction page RM0004 vle instruction index 1016/1176 sd41001 i i i i zzzz xxxx se_stb store byte -958 sd41011 i i i i zzzz xxxx se_sth store halfword -959 r000000000101xxxx se_stmw store multiple word -960 sd41101 i i i i zzzz xxxx se_stw store word -961 rr 0000 0110 yyyy xxxx se_sub subtract -961 rr 0000 0111 yyyy xxxx se_sub. subtract and record -961 rr 0100 0100 yyyy xxxx se_subf subtract from -963 im5 0 0 1 0 1 0 0 i i i i i x x x x se_subfic subtract from immediate carrying -964 im5 0 0 1 0 0 1 0 i i i i i x x x x se_subi subtract immediate -965 im5 0 0 1 0 0 1 1 i i i i i x x x x se_subi. subtract immediate and record -965 rr 0000 1110 yyyy xxxx se_xor xor -966 table 267. instruction index sorted by mnemonic (continued) form at 16-bit opcodes (inst 0:15 ) mnemonic instruction page vle instruction index RM0004 1017/1176 table 268 sorts 32-bit instructions by mnemonic, ignoring the e_ prefix. table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) x 011111- - - - - - - - - - ----- 01000 01010 0 add add book e x 011111- - - - - - - - - - ----- 01000 01010 1 add. add & record cr book e x 011111- - - - - - - - - - ----- 11000 01010 0 addo add & record ov book e x 011111- - - - - - - - - - ----- 11000 01010 1 addo. add & record ov & cr book e x 011111- - - - - - - - - - ----- 00000 01010 0 addc add carrying book e x 011111- - - - - - - - - - ----- 00000 01010 1 addc. add carrying & record cr book e x 011111- - - - - - - - - - ----- 10000 01010 0 addco add carrying & record ov book e x 011111- - - - - - - - - - ----- 10000 01010 1 addco. add carrying & record ov & cr book e x 011111- - - - - - - - - - ----- 00100 01010 0 adde add extended with ca book e x 011111- - - - - - - - - - ----- 00100 01010 1 adde. add extended with ca & record cr book e x 011111- - - - - - - - - - ----- 10100 01010 0 addeo add extended with ca & record ov book e x 011111- - - - - - - - - - ----- 10100 01010 1 addeo. add extended with ca & record ov & cr book e d 001111t t t t t aaaaa iiiiiiiiii iiiii i e_add16i add immediate -898 sci8 001110t t t t t aaaaa 10000 fssi i i i i i i i e_addi add immediate -898 sci8 001110t t t t t aaaaa 11000 fssi i i i i i i i e_addi. add immediate and record -898 sci8 001110t t t t t aaaaa 10001 fssi i i i i i i i e_addic add immediate carrying -900 sci8 001110t t t t t aaaaa 11001 fssi i i i i i i i e_addic. add immediate carrying and record -900 x 011111- - - - - - - - - - ----- 00111 01010 0 addme add to minus one extended with ca book e RM0004 vle instruction index 1018/1176 x 011111- - - - - - - - - - ----- 00111 01010 1 addme. add to minus one extended with ca & record cr book e x 011111- - - - - - - - - - ----- 10111 01010 0 addmeo add to minus one extended with ca & record ov book e x 011111- - - - - - - - - - ----- 10111 01010 1 addmeo. add to minus one extended with ca & record ov & cr book e x 011111- - - - - - - - - - ----- 00110 01010 0 addze add to zero extended with ca book e x 011111- - - - - - - - - - ----- 00110 01010 1 addze. add to zero extended with ca & record cr book e x 011111- - - - - - - - - - ----- 10110 01010 0 addzeo add to zero extended with ca & record ov book e x 011111- - - - - - - - - - ----- 10110 01010 1 addzeo. add to zero extended with ca & record ov & cr book e x 011111- - - - - - - - - - ----- 00000 11100 0 and and book e x 011111- - - - - - - - - - ----- 00000 11100 1 and. and & record cr book e x 011111- - - - - - - - - - ----- 00001 11100 0 andc and with complement book e x 011111- - - - - - - - - - ----- 00001 11100 1 andc. and with complement & record cr book e sci8 001110t t t t t aaaaa 10010 fssi i i i i i i i e_andi and immediate -901 sci8 001110t t t t t aaaaa 11010 fssi i i i i i i i e_andi. and immediate and record -901 bd24 0111100dddd ddddd ddddd ddddd ddddd 0 e_b branch -903 bd15 0111101000o oi i i i ddddd ddddd ddddd 0 e_bc branch conditional -904 bd15 0111101000o oi i i i ddddd ddddd ddddd 1 e_bcl branch conditional & link -904 bd24 0111100dddd ddddd ddddd ddddd ddddd 1 e_bl branch & link -903 x 011111- - - - - - - - - - ----- 00000 00000 / cmp compare book e table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1019/1176 sci8 00111000000 aaaaa 010bffssi i i i i i i i e_cmpi compare immediate -912 x 011111- - - - - - - - - - ----- 00001 00000 / cmpl compare logical book e sci8 00111000000 aaaaa 011bffssi i i i i i i i e_cmpli compare logical immediate -918 x 011111- - - - - - - - - - ----- 00000 11010 0 cntlzw count leading zeros word book e x 011111- - - - - - - - - - ----- 00000 11010 1 cntlzw. count leading zeros word & record cr book e x 011111- - - - - - - - - - ----- 10111 10110 / dcba data cache block allocate indexed book e x 011111- - - - - - - - - - ----- 00010 10110 / dcbf data cache block flush indexed book e x 011111- - - - - - - - - - ----- 01110 10110 / dcbi data cache block invalidate indexed book e x 011111- - - - - - - - - - ----- 00001 10110 / dcbst data cache block store indexed book e x 011111- - - - - - - - - - ----- 00111 10110 / dcbtst data cache block touch for store indexed book e x 011111- - - - - - - - - - ----- 01000 10110 / dcbt data cache block touch indexed book e x 011111- - - - - - - - - - ----- 11111 10110 / dcbz data cache block set to zero indexed book e x 011111- - - - - - - - - - ----- 01111 01011 0 divw divide word book e x 011111- - - - - - - - - - ----- 01111 01011 1 divw. divide word & record cr book e x 011111- - - - - - - - - - ----- 11111 01011 0 divwo divide word & record ov book e x 011111- - - - - - - - - - ----- 11111 01011 1 divwo. divide word & record ov & cr book e x 011111- - - - - - - - - - ----- 01110 01011 0 divwu divide word unsigned book e x 011111- - - - - - - - - - ----- 01110 01011 1 divwu. divide word unsigned & record cr book e table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1020/1176 x 011111- - - - - - - - - - ----- 11110 01011 0 divwuo divide word unsigned & record ov book e x 011111- - - - - - - - - - ----- 11110 01011 1 divwuo. divide word unsigned & record ov & cr book e x 011111- - - - - - - - - - ----- 01000 11100 0 eqv equivalent book e x 011111- - - - - - - - - - ----- 01000 11100 1 eqv. equivalent & record cr book e x 011111- - - - - - - - - - ----- 11101 11010 0 extsb extend sign byte book e x 011111- - - - - - - - - - ----- 11101 11010 1 extsb. extend sign byte & record cr book e x 011111- - - - - - - - - - ----- 11100 11010 0 extsh extend sign halfword book e x 011111- - - - - - - - - - ----- 11100 11010 1 extsh. extend sign halfword & record cr book e x 011111- - - - - - - - - - ----- 11110 10110 / icbi instruction cache block invalidate indexed book e x 011111- - - - - - - - - - ----- 00000 10110 / icbt instruction cache block touch indexed book e x 011111- - - - - - - - - - ----- ----- 01111 / isel integer select book e d14 001100t t t t t aaaaa 00ddd ddddd ddddd d e_lbz load byte & zero -930 x 011111- - - - - - - - - - ----- 00010 10111 / lbzx load byte & zero indexed book e d8 001110t t t t t aaaaa 00000 000dd ddddd d e_lbzu load byte & zero with update -930 x 011111- - - - - - - - - - ----- 00011 10111 / lbzux load byte & zero with update indexed book e d14 001100t t t t t aaaaa 11ddd ddddd ddddd d e_ld load doubleword & zero (reserved for 64b gpr) table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1021/1176 d8 001110t t t t t aaaaa 00000 011dd ddddd d e_ldu load doubleword with update (reserved for 64b gpr) d14 001100t t t t t aaaaa 01ddd ddddd ddddd d e_lhz load halfword & zero -932 d8 001110t t t t t aaaaa 00000 001dd ddddd d e_lhzu load halfword & zero with update -932 x 011111- - - - - - - - - - ----- 01000 10111 / lhzx load halfword & zero indexed book e x 011111- - - - - - - - - - ----- 01001 10111 / lhzux load halfword & zero with update indexed book e d8 001110t t t t t aaaaa 00001 010dd ddddd d e_lha load halfword algebraic -931 x 011111- - - - - - - - - - ----- 01010 10111 / lhax load halfword algebraic indexed book e d8 001110t t t t t aaaaa 00001 011dd ddddd d e_lhau load halfword algebraic with update -931 x 011111- - - - - - - - - - ----- 01011 10111 / lhaux load halfword algebraic with update indexed book e x 011111- - - - - - - - - - ----- 11000 10110 / lhbrx load halfword byte-reverse indexed book e li20 011100t t t t t 0i i i i iiiiiiiiii iiiii i e_li load immediate -933 li20 011100t t t t t 1i i i i iiiiiiiiii iiiii i e_lis load immediate shifted -933 d8 001110t t t t t aaaaa 00001 000dd ddddd d e_lmw load multiple word -934 x 011111- - - - - - - - - - ----- 00000 10100 / lwarx load word & reserve indexed book e x 011111- - - - - - - - - - ----- 10000 10110 / lwbrx load word byte- reverse indexed book e d14 001100t t t t t aaaaa 10ddd ddddd ddddd d e_lwz load word & zero -936 d8 001110t t t t t aaaaa 00000 010dd ddddd d e_lwzu load word & zero with update -935 x 011111- - - - - - - - - - ----- 00000 10111 / lwzx load word & zero indexed book e table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1022/1176 x 011111- - - - - - - - - - ----- 00001 10111 / lwzux load word & zero with update indexed book e x 011111- - - - - - - - - - ----- 11010 10110 / mbar memory barrier book e x 011111- - - - - - - - - - ----- 01000 10011 / mfapidi move from apid indirect book e x 011111- - - - - - - - - - ----- 00000 10011 / mfcr move from condition register book e xfx 011111- - - - - - - - - - ----- 01010 00011 / mfdcr move from device control register book e x 011111- - - - - - - - - - ----- 00010 10011 / mfmsr move from machine state register book e xfx 011111- - - - - - - - - - ----- 01010 10011 / mfspr move from special purpose register book e x 011111- - - - - - - - - - ----- 10010 10110 / msync memory synchronize book e xfx 011111- - - - - - - - - - ----- 00100 10000 / mtcrf move to condition register fields book e x 011111- - - - - - - - - - ----- 10000 00000 / mcrxr move to condition register from xer book e xfx 011111- - - - - - - - - - ----- 01110 00011 / mtdcr move to device control register book e x 011111- - - - - - - - - - ----- 00100 10010 / mtmsr move to machine state register book e xfx 011111- - - - - - - - - - ----- 01110 10011 / mtspr move to special purpose register book e x 011111- - - - - - - - - - ----- /0010 01011 0 mulhw multiply high word book e x 011111- - - - - - - - - - ----- /0010 01011 1 mulhw. multiply high word & record cr book e x 011111- - - - - - - - - - ----- /0000 01011 0 mulhwu multiply high word unsigned book e x 011111- - - - - - - - - - ----- /0000 01011 1 mulhwu. multiply high word unsigned & record cr book e sci8 001110t t t t t aaaaa 10110 fssi i i i i i i i e_mulli multiply low immediate -944 table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1023/1176 sci8 001110t t t t t aaaaa 11110 fssi i i i i i i i e_mulli. multiply low immediate and record -944 x 011111- - - - - - - - - - ----- 00111 01011 0 mullw multiply low word book e x 011111- - - - - - - - - - ----- 00111 01011 1 mullw. multiply low word & record cr book e x 011111- - - - - - - - - - ----- 10111 01011 0 mullwo multiply low word & record ov book e x 011111- - - - - - - - - - ----- 10111 01011 1 mullwo. multiply low word & record ov & cr book e x 011111- - - - - - - - - - ----- 01110 11100 0 nand nand book e x 011111- - - - - - - - - - ----- 01110 11100 1 nand. nand & record cr book e x 011111- - - - - - - - - - ----- 00011 01000 0 neg negate book e x 011111- - - - - - - - - - ----- 00011 01000 1 neg. negate & record cr book e x 011111- - - - - - - - - - ----- 10011 01000 0 nego negate & record ov book e x 011111- - - - - - - - - - ----- 10011 01000 1 nego. negate & record ov & record cr book e x 011111- - - - - - - - - - ----- 00011 11100 0 nor nor book e x 011111- - - - - - - - - - ----- 00011 11100 1 nor. nor & record cr book e x 011111- - - - - - - - - - ----- 01101 11100 0 or or book e x 011111- - - - - - - - - - ----- 01101 11100 1 or. or & record cr book e x 011111- - - - - - - - - - ----- 01100 11100 0 orc or with complement book e x 011111- - - - - - - - - - ----- 01100 11100 1 orc. or with complement & record cr book e sci8 001110t t t t t aaaaa 10011 fssi i i i i i i i e_ori or immediate -948 sci8 001110t t t t t aaaaa 11011 fssi i i i i i i i e_ori. or immediate and record -951 table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1024/1176 011101sssss aaaaa hhhhh bbbbb eeeee 1 e_rlwinm. rotate left word immed then and with mask & record cr -953 011101sssss aaaaa hhhhh bbbbb eeeee 0 e_rlwimi. rotate left word immed then mask insert & record cr -952 x 011111- - - - - - - - - - ----- 00000 11000 0 slw shift left word book e x 011111- - - - - - - - - - ----- 00000 11000 1 slw. shift left word & record cr book e x 011111- - - - - - - - - - ----- 11000 11000 0 sraw shift right algebraic word book e x 011111- - - - - - - - - - ----- 11000 11000 1 sraw. shift right algebraic word & record cr book e x 011111- - - - - - - - - - ----- 11001 11000 0 srawi shift right algebraic word immediate book e x 011111- - - - - - - - - - ----- 11001 11000 1 srawi. shift right algebraic word immediate & record cr book e x 011111- - - - - - - - - - ----- 10000 11000 0 srw shift right word book e x 011111- - - - - - - - - - ----- 10000 11000 1 srw. shift right word & record cr book e d14 001101t t t t t aaaaa 00ddd ddddd ddddd d e_stb store byte -958 x 011111- - - - - - - - - - ----- 00110 10111 / stbx store byte indexed book e d8 001110t t t t t aaaaa 00000 100dd ddddd d e_stbu store byte with update -958 x 011111- - - - - - - - - - ----- 00111 10111 / stbux store byte with update indexed -958 d14 001101t t t t t aaaaa 11ddd ddddd ddddd d e_std store doubleword (reserved for 64b gpr) book e d8 001110t t t t t aaaaa 00000 111dd ddddd d e_stdu store doubleword with update (reserved for 64b gpr) table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1025/1176 d14 001101t t t t t aaaaa 01ddd ddddd ddddd d e_sth store halfword -959 x 011111- - - - - - - - - - ----- 11100 10110 / sthbrx store halfword byte-reverse indexed book e x 011111- - - - - - - - - - ----- 01100 10111 / sthx store halfword indexed book e d8 001110t t t t t aaaaa 00000 101dd ddddd d e_sthu store halfword with update -959 x 011111- - - - - - - - - - ----- 01101 10111 / sthux store halfword with update indexed book e d8 001110t t t t t aaaaa 00001 001dd ddddd d e_stmw store multiple word book e d14 001101t t t t t aaaaa 10ddd ddddd ddddd d e_stw store word -961 x 011111- - - - - - - - - - ----- 10100 10110 / stwbrx store word byte- reverse indexed book e x 011111- - - - - - - - - - ----- 00100 10110 1 stwcx. store word conditional indexed & record cr book e d8 001110t t t t t aaaaa 00000 110dd ddddd d e_stwu store word with update -961 x 011111- - - - - - - - - - ----- 00101 10111 / stwux store word with update indexed book e x 011111- - - - - - - - - - ----- 00100 10111 / stwx store word indexed book e x 011111- - - - - - - - - - ----- 00001 01000 0 subf subtract from book e x 011111- - - - - - - - - - ----- 00001 01000 1 subf. subtract from & record cr book e x 011111- - - - - - - - - - ----- 00000 01000 0 subfc subtract from carrying book e x 011111- - - - - - - - - - ----- 00000 01000 1 subfc. subtract from carrying & record cr book e x 011111- - - - - - - - - - ----- 10000 01000 0 subfco subtract from carrying & record ov book e x 011111- - - - - - - - - - ----- 10000 01000 1 subfco. subtract from carrying & record ov & cr book e table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 vle instruction index 1026/1176 x 011111- - - - - - - - - - ----- 10001 01000 0 subfo subtract from & record ov book e x 011111- - - - - - - - - - ----- 10001 01000 1 subfo. subtract from & record ov & cr book e x 011111- - - - - - - - - - ----- 00100 01000 0 subfe subtract from extended with ca book e x 011111- - - - - - - - - - ----- 00100 01000 1 subfe. subtract from extended with ca & record cr book e x 011111- - - - - - - - - - ----- 10100 01000 0 subfeo subtract from extended with ca & record ov book e x 011111- - - - - - - - - - ----- 10100 01000 1 subfeo. subtract from extended with ca & record ov & cr book e sci8 001110t t t t t aaaaa 10100 fssi i i i i i i i e_subfic subtract from immediate carrying -964 sci8 001110t t t t t aaaaa 11100 fssi i i i i i i i e_subfic. subtract from immediate carrying and record -964 x 011111- - - - - - - - - - ----- 00111 01000 0 subfme subtract from minus one extended with ca book e x 011111- - - - - - - - - - ----- 00111 01000 1 subfme. subtract from minus one extended with ca & record cr book e x 011111- - - - - - - - - - ----- 10111 01000 0 subfmeo subtract from minus one extended with ca & record ov book e x 011111- - - - - - - - - - ----- 10111 01000 1 subfmeo. subtract from minus one extended with ca & record ov & cr book e x 011111- - - - - - - - - - ----- 00110 01000 0 subfze subtract from zero extended with ca book e x 011111- - - - - - - - - - ----- 00110 01000 1 subfze. subtract from zero extended with ca & record cr book e table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) vle instruction index RM0004 1027/1176 x 011111- - - - - - - - - - ----- 10110 01000 0 subfzeo subtract from zero extended with ca & record ov book e x 011111- - - - - - - - - - ----- 10110 01000 1 subfzeo. subtract from zero extended with ca & record ov & cr book e x 011111- - - - - - - - - - ----- 11000 10010 / tlbivax tlb invalidate virtual address indexed book e x 011111- - - - - - - - - - ----- 11101 10010 / tlbre tlb read entry book e x 011111- - - - - - - - - - ----- 11100 10010 ? tlbsx tlb search indexed book e x 011111- - - - - - - - - - ----- 10001 10110 / tlbsync tlb synchronize book e x 011111- - - - - - - - - - ----- 11110 10010 / tlbwe tlb write entry book e x 011111- - - - - - - - - - ----- 00000 00100 / tw trap word book e x 011111- - - - - - - - - - ----- 00100 00011 / wrtee write external enable book e x 011111- - - - - - - - - - ----- 00101 00011 / wrteei write external enable immediate book e x 011111- - - - - - - - - - ----- 01001 11100 0 xor xor book e x 011111- - - - - - - - - - ----- 01001 11100 1 xor. xor & record cr book e sci8 001110t t t t t aaaaa 10111 fssi i i i i i i i e_xori xor immediate -966 sci8 001110t t t t t aaaaa 11111 fssi i i i i i i i e_xori. xor immediate and record -966 table 268. 32-bit instructions by mnemonic (ignoring the e_ prefix) (continued) format opcode mnemonic instruction page primary (inst 0:5 ) intermediate (inst 6:20 ) extended (inst 21:31 ) RM0004 instruction set listings 1028/1176 appendix a instruction set listings this appendix lists the instructions by bo th mnemonic and opcode, and includes a quick reference table with general information, such as the architecture level, privilege level, form, and whether the instruction is optional. the tables in the chapter are organized as follows: chapter a.1: instructions sorted by mnemonic (decimal and hexadecimal) ? chapter a.2: instructions sorted by primary opcodes (decimal and hexadecimal) ? chapter a.3: instructions sorted by mnemonic (binary) ? chapter a.4: instructions sorted by opcode (binary) ? chapter a.5: instruction set legend ? note that this appendix does not include instructions defined by the vle extension. these instructions are listed in chapter 14: vle instruction index on page 862. a.1 instructions sorted by mnem onic (decimal and hexadecimal) table 269 lists instructions in alphabetical order by mnemonic, showing decimal and hexadecimal values of the primary opcode (0?5) and binary values of the secondary opcode (21?31). this list also includes simplified mn emonics and their equivalents using standard mnemonics. table 269. instructions sorted by mnemonic (decimal and hexadecimal) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic add 31 (0x1f) rd ra rb 01000010100 x add add. 31 (0x1f) rd ra rb 01000010101 x add. addc 31 (0x1f) rd ra rb 00000010100 x addc addc. 31 (0x1f) rd ra rb 00000010101 x addc. addco 31 (0x1f) rd ra rb 10000010100 x addco addco. 31 (0x1f) rd ra rb 10000010101 x addco. adde 31 (0x1f) rd ra rb 00100010100 x adde adde. 31 (0x1f) rd ra rb 00100010101 x adde. addeo 31 (0x1f) rd ra rb 10100010100 x addeo addeo. 31 (0x1f) rd ra rb 10100010101 x addeo. addi 14 (0x0e) rd ra simm d addi addic 12 (0x0c) rd ra simm d addic addic. 13 (0x0d) rd ra simm d addic. addis 15 (0x0f) rd ra simm d addis addme 31 (0x1f) rd ra /// 00111010100 x addme addme. 31 (0x1f) rd ra /// 00111010101 x addme. addmeo 31 (0x1f) rd ra /// 10111010100 x addmeo addmeo. 31 (0x1f) rd ra /// 10111010101 x addmeo. addo 31 (0x1f) rd ra rb 11000010100 x addo addo. 31 (0x1f) rd ra rb 11000010101 x addo. instruction set listings RM0004 1029/1176 addze 31 (0x1f) rd ra /// 00110010100 x addze addze. 31 (0x1f) rd ra /// 00110010101 x addze. addzeo 31 (0x1f) rd ra /// 10110010100 x addzeo addzeo. 31 (0x1f) rd ra /// 10110010101 x addzeo. and 31 (0x1f) rs ra rb 00000111000 x and and. 31 (0x1f) rs ra rb 00000111001 x and. andc 31 (0x1f) rs ra rb 00001111000 x andc andc. 31 (0x1f) rs ra rb 00001111001 x andc. andi. 28 (0x1c) rs ra uimm d andi. andis. 29 (0x1d) rs ra uimm d andis. b 18 (0x12) li 0 0 i b ba 18 (0x12) li 1 0 i ba bc 16 (0x10) bo bi bd 0 0 b bc bca 16 (0x10) bo bi bd 1 0 b bca bcctr 19 (0x13) bo bi /// 10000100000 xl bcctr bcctrl 19 (0x13) bo bi /// 10000100001 xl bcctrl bcl 16 (0x10) bo bi bd 0 1 b bcl bcla 16 (0x10) bo bi bd 1 1 b bcla bclr 19 (0x13) bo bi /// 00000100000 xl bclr bclrl 19 (0x13) bo bi /// 00000100001 xl bclrl bctr bctr (1) equivalent to bcctr 20,0 bctr bctrl bctrl 1 equivalent to bcctrl 20,0 bctrl bdnz bdnz target 1 equivalent to bc 16,0, target bdnz bdnza bdnza target 1 equivalent to bca 16,0, targe t bdnza bdnzf bdnzf bi, target equivalent to bc 0,bi, target bdnzf bdnzfa bdnzfa bi, target equivalent to bca 0,bi, target bdnzfa bdnzfl bdnzfl bi, target equivalent to bcl 0,bi, target bdnzfl bdnzfla bdnzfla bi, target equivalent to bcla 0,bi, target bdnzfla bdnzflr bdnzflr bi equivalent to bclr 0,bi bdnzflr bdnzflrl bdnzflrl bi equivalent to bclrl 0,bi bdnzflrl bdnzl bdnzl target 1 equivalent to bcl 16,0, target bdnzl bdnzla bdnzla target 1 equivalent to bcla 16,0, target bdnzla bdnzlr bdnzlr bi equivalent to bclr 16,bi bdnzlr bdnzlrl bdnzlrl 1 equivalent to bclrl 16,0 bdnzlrl bdnzt bdnzt bi, target equivalent to bc 8,bi, target bdnzt bdnzta bdnzta bi, target equivalent to bca 8,bi, target bdnzta bdnztl bdnztl bi, target equivalent to bcl 8,0, target bdnztl bdnztla bdnztla bi, target equivalent to bcla 8,bi, target bdnztla bdnztlr bdnztlr bi equivalent to bclr 8,bi bdnztlr bdnztlr bdnztlr bi equivalent to bclr 8,bi bdnztlr table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1030/1176 bdnztlrl bdnztlrl bi equivalent to bclrl 8,bi bdnztlrl bdz bdz target 1 equivalent to bc 18,0, target bdz bdza bdza target 1 equivalent to bca 18,0, target bdza bdzf bdzf bi, target equivalent to bc 2,bi, target bdzf bdzfa bdzfa bi, target equivalent to bca 2,bi, target bdzfa bdzfl bdzfl bi, target equivalent to bcl 2,bi, target bdzfl bdzfla bdzfla bi, target equivalent to bcla 2,bi, target bdzfla bdzflr bdzflr bi equivalent to bclr 2,bi bdzflr bdzflrl bdzflrl bi equivalent to bclrl 2,bi bdzflrl bdzl bdzl target 1 equivalent to bcl 18,bi, target bdzl bdzla bdzla target 1 equivalent to bcla 18,bi, target bdzla bdzlr bdzlr 1 equivalent to bclr 18,0 bdzlr bdzlrl bdzlrl 1 equivalent to bclrl 18,0 bdzlrl bdzt bdzt bi, target equivalent to bc 10,bi, target bdzt bdzta bdzta bi, target equivalent to bca 10,bi, target bdzta bdztl bdztl bi, target equivalent to bcl 10,bi, target bdztl bdztla bdztla bi, target equivalent to bcla 10,bi, target bdztla bdztlrl bdztlrl bi equivalent to bclrl 10, bi bdztlrl beq beq cr s , target equivalent to bc 12, bi (2) , target beq beqa beqa cr s , target equivalent to bca 12, bi 2 , target beqa beqctr beqctr cr s , target equivalent to bcctr 12, bi 2 , target beqctr beqctrl beqctrl cr s , target equivalent to bcctrl 12, bi 2 , target beqctrl beql beql cr s , target equivalent to bcl 12, bi 2 , target beql beqla beqla cr s , target equivalent to bcla 12, bi 2 , target beqla beqlr beqlr cr s , target equivalent to bclr 12, bi 2 , target beqlr beqlrl beqlrl cr s , target equivalent to bclrl 12, bi 2 , target beqlrl bf bf bi, target equivalent to bc 4,bi, target bf bfa bfa bi, target equivalent to bca 4,bi, target bfa bfctr bfctr bi equivalent to bcctr 4,bi bfctr bfctrl bfctrl bi equivalent to bcctrl 4, bi bfctrl bfl bfl bi, target equivalent t bcl 4,bi, target bfl bfla bfla bi, target equivalent to bcla 4,bi, target bfla bflr bflr bi equivalent to bclr 4,bi bflr bflrl bflrl bi equivalent to bclrl 4,bi bflrl bge bge cr s , target equivalent to bc 4, bi (3) , target bge bgea bgea cr s , target equivalent to bca 4, bi 3 , target bgea bgectr bgectr cr s , target equivalent to bcctr 4, bi 3 , target bgectr bgectrl bgectrl cr s , target equivalent to bcctrl 4, bi 3 , target bgectrl bgel bgel cr s , target equivalent to bcl 4, bi 3 , target bgel bgela bgela cr s , target equivalent to bcla 4, bi 3 , target bgela table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1031/1176 bgelr bgelr cr s , target equivalent to bclr 4, bi 3 , target bgelr bgelrl bgelrl cr s , target equivalent to bclrl 4, bi 3 , target bgelrl bgt bgt cr s , target equivalent to bc 12, bi (4) , target bgt bgta bgta cr s , target equivalent to bca 12, bi 4 , target bgta bgtctr bgtctr cr s , target equivalent to bcctr 12, bi 4 , target bgtctr bgtctrl bgtctrl cr s , target equivalent to bcctrl 12, bi 4 , target bgtctrl bgtl bgtl cr s , target equivalent to bcl 12, bi 4 , target bgtl bgtla bgtla cr s , target equivalent to bcla 12, bi 4 , target bgtla bgtlr bgtlr cr s , target equivalent to bclr 12, bi 4 , target bgtlr bgtlrl bgtlrl cr s , target equivalent to bclrl 12, bi 4 , target bgtlrl bl 18 (0x12) li 0 1 i bl bla 18 (0x12) li 1 1 i bla ble ble cr s , target equivalent to bc 4, bi 4 , target ble blea blea cr s , target equivalent to bca 4, bi 4 , target blea blectr blectr cr s , target equivalent to bcctr 4, bi 4 , target blectr blectrl blectrl cr s , target equivalent to bcctrl 4, bi 4 , target blectrl blel blel cr s , target equivalent to bcl 4, bi 4 , target blel blela blela cr s , target equivalent to bcla 4, bi 4 , target blela blelr blelr cr s , target equivalent to bclr 4, bi 4 , target blelr blelrl blelrl cr s , target equivalent to bclrl 4, bi 4 , target blelrl blr blr 1 equivalent to bclr 20,0 blr blrl blrl 1 equivalent to bclrl 20,0 blrl blt blt cr s , target equivalent to bc 12, bi , target blt blta blta cr s , target equivalent to bca 12, bi 3 , target blta bltctr bltctr cr s , target equivalent to bcctr 12, bi 3 , target bltctr bltctrl bltctrl cr s , target equivalent to bcctrl 12, bi 3 , target bltctrl bltl bltl cr s , target equivalent to bcl 12, bi 3 , target bltl bltla bltla cr s , target equivalent to bcla 12, bi 3 , target bltla bltlr bltlr cr s , target equivalent to bclr 12, bi 3 , target bltlr bltlrl bltlrl cr s , target equivalent to bclrl 12, bi 3 , target bltlrl bne bne cr s , target equivalent to bc 4, bi 3 , target bne bnea bnea cr s , target equivalent to bca 4, bi 3 , target bnea bnectr bnectr cr s , target equivalent to bcctr 4, bi 3 , target bnectr bnectrl bnectrl cr s , target equivalent to bcctrl 4, bi 3 , target bnectrl bnel bnel cr s , target equivalent to bcl 4, bi 3 , target bnel bnela bnela cr s , target equivalent to bcla 4, bi 3 , target bnela bnelr bnelr cr s , target equivalent to bclr 4, bi 3 , target bnelr bnelrl bnelrl cr s , target equivalent to bclrl 4, bi 3 , target bnelrl bng bng cr s , target equivalent to bc 4, bi 4 , target bng bnga bnga cr s , target equivalent to bca 4, bi 4 , target bnga table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1032/1176 bngctr bngctr cr s , target equivalent to bcctr 4, bi 4 , target bngctr bngctrl bngctrl cr s , target equivalent to bcctrl 4, bi 4 , target bngctrl bngl bngl cr s , target equivalent to bcl 4, bi 4 , target bngl bngla bngla cr s , target equivalent to bcla 4, bi 4 , target bngla bnglr bnglr cr s , target equivalent to bclr 4, bi 4 , target bnglr bnglrl bnglrl cr s , target equivalent to bclrl 4, bi 4 , target bnglrl bnl bnl cr s , target equivalent to bc 4, bi 3 , target bnl bnla bnla cr s , target equivalent to bca 4, bi 3 , target bnla bnlctr bnlctr cr s , target equivalent to bcctr 4, bi 3 , target bnlctr bnlctrl bnlctrl cr s , target equivalent to bcctrl 4, bi 3 , target bnlctrl bnll bnll cr s , target equivalent to bcl 4, bi 3 , target bnll bnlla bnlla cr s , target equivalent to bcla 4, bi 3 , target bnlla bnllr bnllr cr s , target equivalent to bclr 4, bi 3 , target bnllr bnllrl bnllrl cr s , target equivalent to bclrl 4, bi 3 , target bnllrl bns bns cr s , target equivalent to bc 4, bi (5) , target bns bnsa bnsa cr s , target equivalent to bca 4, bi 5 , target bnsa bnsctr bnsctr cr s , target equivalent to bcctr 4, bi 5 , target bnsctr bnsctrl bnsctrl cr s , target equivalent to bcctrl 4, bi 5 , target bnsctrl bnsl bnsl cr s , target equivalent to bcl 4, bi 5 , target bnsl bnsla bnsla cr s , target equivalent to bcla 4, bi 5 , target bnsla bnslr bnslr cr s , target equivalent to bclr 4, bi 5 , target bnslr bnslrl bnslrl cr s , target equivalent to bclrl 4, bi 5 , target bnslrl bnu bnu cr s , target equivalent to bc 4, bi 5 , target bnu bnua bnua cr s , target equivalent to bca 4, bi 5 , target bnua bnuctr bnuctr cr s , target equivalent to bcctr 4, bi 5 , target bnuctr bnuctrl bnuctrl cr s , target equivalent to bcctrl 4, bi 5 , target bnuctrl bnul bnul cr s , target equivalent to bcl 4, bi 5 , target bnul bnula bnula cr s , target equivalent to bcla 4, bi 5 , target bnula bnulr bnulr cr s , target equivalent to bclr 4, bi 5 , target bnulr bnulrl bnulrl cr s , target equivalent to bclrl 4, bi 5 , target bnulrl brinc 04 rd ra rb 01000001111 evx brinc bso bso cr s , target equivalent to bc 12, bi 5 , target bso bsoa bsoa cr s , target equivalent to bca 12, bi 5 , target bsoa bsoctr bsoctr cr s , target equivalent to bcctr 12, bi 5 , target bsoctr bsoctrl bsoctrl cr s , target equivalent to bcctrl 12, bi 5 , target bsoctrl bsol bsol cr s , target equivalent to bcl 12, bi 5 , target bsol bsola bsola cr s , target equivalent to bcla 12, bi 5 , target bsola bsolr bsolr cr s , target equivalent to bclr 12, bi 5 , target bsolr bsolrl bsolrl cr s , target equivalent to bclrl 12, bi 5 , target bsolrl bt bt bi, target equivalent to bc 12,bi, target bt table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1033/1176 bta bta bi, target equivalent to bca 12,bi, target bta btctr btctr bi equivalent to bcctr 12,bi btctr btctrl btctrl bi equivalent to bcctrl 12,bi btctrl btl btl bi, target equivalent to bcl 12,bi, target btl btla btla bi, target equivalent to bcla 12,bi, target btla btlr btlr bi equivalent to bclr 12,bi btlr btlrl btlrl bi equivalent to bclrl 12,bi btlrl bun bun cr s , target equivalent to bc 12, bi 5 , target bun buna buna cr s , target equivalent to bca 12, bi 5 , target buna bunctr bunctr cr s , target equivalent to bcctr 12, bi 5 , target bunctr bunctrl bunctrl cr s , target equivalent to bcctrl 12, bi 5 , target bunctrl bunl bunl cr s , target equivalent to bcl 12, bi 5 , target bunl bunla bunla cr s , target equivalent to bcla 12, bi 5 , target bunla bunlr bunlr cr s , target equivalent to bclr 12, bi 5 , target bunlr bunlrl bunlrl cr s , target equivalent to bclrl 12, bi 5 , target bunlrl clrlslwi clrlslwi r a ,r s , b , n ( n b 31) equivalent to rlwinm r a ,r s , n , b ? n , 31 ? n clrlslwi clrlwi clrlwi r a ,r s , n (n < 32) equivalent to rlwinm r a ,r s ,0, n ,31 clrlwi clrrwi clrrwi r a ,r s , n (n < 32) equivalent to rlwinm r a ,r s ,0,0,31 ? n clrrwi cmp 31 (0x1f) crfd /l ra rb 0000000000 / x cmp cmpi 11 (0x0b) crfd / l ra simm d cmpi cmpl 31 (0x1f) /l ra rb /// 0000100000 / x cmpl cmpli 10 (0x0a) crfd / l ra uimm d cmpli cmplw cmplw cr d ,r a ,r b equivalent to cmpl cr d ,0,r a ,r b cmplw cmplwi cmplwi cr d ,r a ,uimm equivalent to cmpli cr d ,0,r a , uimm cmplwi cmpw cmpw cr d ,r a ,r b equivalent to cmp cr d ,0,r a ,r b cmpw cmpwi cmpwi cr d ,r a ,simm equivalent to cmpi cr d ,0,r a , simm cmpwi cntlzw 31 (0x1f) rs ra /// 00000110100 x cntlzw cntlzw. 31 (0x1f) rs ra /// 00000110101 x cntlzw. crand 19 (0x13) crbd crba crbb 0100000001 / xl crand crandc 19 (0x13) crbd crba crbb 0010000001 / xl crandc crclr crclr bx equivalent to crxor bx , bx , bx crclr creqv 19 (0x13) crbd crba crbb 0100100001 / xl creqv crmove crmove bx,by equivalent to cror bx , by , by crmove crnand 19 (0x13) crbd crba crbb 0011100001 / xl crnand crnor 19 (0x13) crbd crba crbb 0000100001 / xl crnor crnot crnot bx,by equivalent to crnor bx , by , by crnot cror 19 (0x13) crbd crba crbb 0111000001 / xl cror crorc 19 (0x13) crbd crba crbb 0110100001 / xl crorc crset crset bx equivalent to creqv bx , bx , bx crset crxor 19 (0x13) crbd crba crbb 0011000001 / xl crxor table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1034/1176 dcba (6) 31 (0x1f) /// ra rb 1011110110 / x dcba dcbf 31 (0x1f) /// ra rb 0001010110 / x dcbf dcb i (7) 31 (0x1f) /// ra rb 0111010110 / x dcbi dcblc 31 (0x1f) ct ra rb 01100001100 x dcblc dcbst 31 (0x1f) /// ra rb 0000110110 / x dcbst dcbt 31 (0x1f) ct ra rb 0100010110 / x dcbt dcbtls 31 (0x1f) ct ra rb 00101001100 x dcbtls dcbtst 31 (0x1f) ct ra rb 0011110110 / x dcbtst dcbtstls 31 (0x1f) ct ra rb 00100001100 x dcbtstls dcbz 31 (0x1f) /// ra rb 1111110110 / x dcbz divw 31 (0x1f) rd ra rb 01111010110 x divw divw. 31 (0x1f) rd ra rb 01111010111 x divw. divwo 31 (0x1f) rd ra rb 11111010110 x divwo divwo. 31 (0x1f) rd ra rb 11111010111 x divwo. divwu 31 (0x1f) rd ra rb 01110010110 x divwu divwu. 31 (0x1f) rd ra rb 01110010111 x divwu. divwuo 31 (0x1f) rd ra rb 11110010110 x divwuo divwuo. 31 (0x1f) rd ra rb 11110010111 x divwuo. dss dss strm equivalent to dss strm ,0 dss efdabs 04 rd ra /// 01011100100 efx efdabs efdadd 04 rd ra rb 01011100000 efx efdadd efdcfs 04 rd 00000 rb 0 1011101111 efx efdcfs efdcfsf 04 rd /// rb 01011110011 efx efdcfsf efdcfsi 04 rd /// rb 01011110001 efx efdcfsi efdcfuf 04 rd /// rb 01011110010 efx efdcfuf efdcfui 04 rd /// rb 01011110000 efx efdcfui efdcmpeq 04 crfd // ra rb 01011101110 efx efdcmpeq efdcmpgt 04 crfd // ra rb 01011101100 efx efdcmpgt efdcmplt 04 crfd // ra rb 01011101101 efx efdcmplt efdctsf 04 rd /// rb 01011110111 efx efdctsf efdctsi 04 rd /// rb 01011110101 efx efdctsi efdctsiz 04 rd /// rb 01011111010 efx efdctsiz efdctuf 04 rd /// rb 01011110110 efx efdctuf efdctui 04 rd /// rb 01011110100 efx efdctui efdctuiz 04 rd /// rb 01011111000 efx efdctuiz efddiv 04 rd ra rb 01011101001 efx efddiv efdmul 04 rd ra rb 01011101000 efx efdmul efdnabs 04 rd ra /// 01011100101 efx efdnabs efdneg 04 rd ra /// 01011100110 efx efdneg efdsub 04 rd ra rb 01011100001 efx efdsub table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1035/1176 efdtsteq 04 crfd // ra rb 01011111110 efx efdtsteq efdtstgt 04 crfd // ra rb 01011111100 efx efdtstgt efdtstlt 04 crfd // ra rb 01011111101 efx efdtstlt efsabs 04 rd ra /// 01011000100 efx efsabs efsadd 04 rd ra rb 01011000000 efx efsadd efscfd 04 rd 00000 rb 0 1011001111 efx efscfd efscfsf 04 rd /// rb 01011010011 efx efscfsf efscfsi 04 rd /// rb 01011010001 efx efscfsi efscfuf 04 rd /// rb 01011010010 efx efscfuf efscfui 04 rd /// rb 01011010000 efx efscfui efscmpeq 04 crfd // ra rb 01011001110 efx efscmpeq efscmpgt 04 crfd // ra rb 01011001100 efx efscmpgt efscmplt 04 crfd // ra rb 01011001101 efx efscmplt efsctsf 04 rd /// rb 01011010111 efx efsctsf efsctsi 04 rd /// rb 01011010101 efx efsctsi efsctsiz 04 rd /// rb 01011011010 efx efsctsiz efsctuf 04 rd /// rb 01011010110 efx efsctuf efsctui 04 rd /// rb 01011010100 efx efsctui efsctuiz 04 rd /// rb 01011011000 efx efsctuiz efsdiv 04 rd ra rb 01011001001 efx efsdiv efsmul 04 rd ra rb 01011001000 efx efsmul efsnabs 04 rd ra /// 01011000101 efx efsnabs efsneg 04 rd ra /// 01011000110 efx efsneg efssub 04 rd ra rb 01011000001 efx efssub efststeq 04 crfd // ra rb 01011011110 efx efststeq efststgt 04 crfd // ra rb 01011011100 efx efststgt efststlt 04 crfd // ra rb 01011011101 efx efststlt eqv 31 (0x1f) rd ra rb 01000111000 x eqv eqv. 31 (0x1f) rd ra rb 01000111001 x eqv. evabs 31 (0x1f) rd ra /// 01000001000 evx evabs evaddiw 31 (0x1f) rd uimm rb 01000000010 evx evaddiw evaddsm iaaw 31 (0x1f) rd ra /// 10011001001 evx evaddsmi aaw evaddssi aaw 31 (0x1f) rd ra /// 10011000001 evx evaddssia aw evaddum iaaw 31 (0x1f) rd ra /// 10011001000 evx evaddumi aaw evaddusi aaw 31 (0x1f) rd ra /// 10011000000 evx evaddusi aaw evaddw 31 (0x1f) rd ra rb 01000000000 evx evaddw evand 31 (0x1f) rd ra rb 01000010001 evx evand table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1036/1176 evandc 31 (0x1f) rd ra rb 01000010010 evx evandc evcmpeq 31 (0x1f) crfd // ra rb 01000110100 evx evcmpeq evcmpgt s 31 (0x1f) crfd // ra rb 01000110001 evx evcmpgts evcmpgt u 31 (0x1f) crfd // ra rb 01000110000 evx evcmpgtu evcmplts 31 (0x1f) crfd // ra rb 01000110011 evx evcmplts evcmpltu 31 (0x1f) crfd // ra rb 01000110010 evx evcmpltu evcntlsw 31 (0x1f) rd ra /// 01000001110 evx evcntlsw evcntlzw 31 (0x1f) rd ra /// 01000001101 evx evcntlzw evdivws 31 (0x1f) rd ra rb 10011000110 evx evdivws evdivwu 31 (0x1f) rd ra rb 10011000111 evx evdivwu eveqv 31 (0x1f) rd ra rb 01000011001 evx eveqv evextsb 31 (0x1f) rd ra /// 01000001010 evx evextsb evextsh 31 (0x1f) rd ra /// 01000001011 evx evextsh evfsabs 31 (0x1f) rd ra /// 01010000100 evx evfsabs evfsadd 31 (0x1f) rd ra rb 01010000000 evx evfsadd evfscfsf 31 (0x1f) rd /// rb 01010010011 evx evfscfsf evfscfsi 31 (0x1f) rd /// rb 01010010001 evx evfscfsi evfscfuf 31 (0x1f) rd /// rb 01010010010 evx evfscfuf evfscfui 31 (0x1f) rd /// rb 01010010000 evx evfscfui evfscmp eq 31 (0x1f) crfd // ra rb 01010001110 evx evfscmpe q evfscmp gt 31 (0x1f) crfd // ra rb 01010001100 evx evfscmpg t evfscmpl t 31 (0x1f) crfd // ra rb 01010001101 evx evfscmplt evfsctsf 31 (0x1f) rd /// rb 01010010111 evx evfsctsf evfsctsi 31 (0x1f) rd /// rb 01010010101 evx evfsctsi evfsctsiz 31 (0x1f) rd /// rb 01010011010 evx evfsctsiz evfsctuf 31 (0x1f) rd /// rb 01010010110 evx evfsctuf evfsctui 31 (0x1f) rd /// rb 01010010100 evx evfsctui evfsctuiz 31 (0x1f) rd /// rb 01010011000 evx evfsctuiz evfsdiv 31 (0x1f) rd ra rb 01010001001 evx evfsdiv evfsmul 31 (0x1f) rd ra rb 01010001000 evx evfsmul evfsnabs 31 (0x1f) rd ra /// 01010000101 evx evfsnabs evfsneg 31 (0x1f) rd ra /// 01010000110 evx evfsneg evfssub 31 (0x1f) rd ra rb 01010000001 evx evfssub evfststeq 31 (0x1f) crfd // ra rb 01010011110 evx evfststeq evfststgt 31 (0x1f) crfd // ra rb 01010011100 evx evfststgt evfststlt 31 (0x1f) crfd // ra rb 01010011101 evx evfststlt evldd 31 (0x1f) rd ra uimm 8 01100000001 evx evldd table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1037/1176 evlddx 31 (0x1f) rd ra rb 01100000000 evx evlddx evldh 31 (0x1f) rd ra uimm 8 01100000101 evx evldh evldhx 31 (0x1f) rd ra rb 01100000100 evx evldhx evldw 31 (0x1f) rd ra uimm 8 01100000011 evx evldw evldwx 31 (0x1f) rd ra rb 01100000010 evx evldwx evlhhesp lat 31 (0x1f) rd ra uimm 8 01100001001 evx evlhhespl at evlhhesp latx 31 (0x1f) rd ra rb 01100001000 evx evlhhespl atx evlhhoss plat 31 (0x1f) rd ra uimm 9 01100001111 evx evlhhoss plat evlhhoss platx 31 (0x1f) rd ra rb 01100001110 evx evlhhoss platx evlhhous plat 31 (0x1f) rd ra uimm 9 01100001101 evx evlhhous plat evlhhous platx 31 (0x1f) rd ra rb 01100001100 evx evlhhous platx evlwhe 31 (0x1f) rd ra uimm 8 01100010001 evx evlwhe evlwhex 31 (0x1f) rd ra rb 01100010000 evx evlwhex evlwhos 31 (0x1f) rd ra uimm 10 01100010111 evx evlwhos evlwhosx 31 (0x1f) rd ra rb 01100010110 evx evlwhosx evlwhou 31 (0x1f) rd ra uimm 10 01100010101 evx evlwhou evlwhoux 31 (0x1f) rd ra rb 01100010100 evx evlwhoux evlwhspl at 31 (0x1f) rd ra uimm 10 01100011101 evx evlwhsplat evlwhspl atx 31 (0x1f) rd ra rb 01100011100 evx evlwhspla tx evlwwspl at 31 (0x1f) rd ra uimm 10 01100011001 evx evlwwspl at evlwwspl atx 31 (0x1f) rd ra rb 01100011000 evx evlwwspl atx evmerge hi 31 (0x1f) rd ra rb 01000101100 evx evmergeh i evmerge hilo 31 (0x1f) rd ra rb 01000101110 evx evmergeh ilo evmergelo 31 (0x1f) rd ra rb 01000101101 evx evmergelo evmergel ohi 31 (0x1f) rd ra rb 01000101111 evx evmergel ohi evmhegs mfaa 31 (0x1f) rd ra rb 10100101011 evx evmhegs mfaa evmhegs mfan 31 (0x1f) rd ra rb 10110101011 evx evmhegs mfan evmhegs miaa 31 (0x1f) rd ra rb 10100101001 evx evmhegs miaa evmhegs mian 31 (0x1f) rd ra rb 10110101001 evx evmhegs mian evmhegu miaa 31 (0x1f) rd ra rb 10100101000 evx evmhegu miaa table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1038/1176 evmhegu mian 31 (0x1f) rd ra rb 10110101000 evx evmhegu mian evmhes mf 31 (0x1f) rd ra rb 10000001011 evx evmhesm f evmhes mfa 31 (0x1f) rd ra rb 10000101011 evx evmhesm fa evmhes mfaaw 31 (0x1f) rd ra rb 10100001011 evx evmhesm faaw evmhes mfanw 31 (0x1f) rd ra rb 10110001011 evx evmhesm fanw evmhes mi 31 (0x1f) rd ra rb 10000001001 evx evmhesm i evmhes mia 31 (0x1f) rd ra rb 10000101001 evx evmhesm ia evmhes miaaw 31 (0x1f) rd ra rb 10100001001 evx evmhesm iaaw evmhes mianw 31 (0x1f) rd ra rb 10110001001 evx evmhesm ianw evmhessf 31 (0x1f) rd ra rb 10000000011 evx evmhessf evmhess fa 31 (0x1f) rd ra rb 10000100011 evx evmhessf a evmhess faaw 31 (0x1f) rd ra rb 10100000011 evx evmhessf aaw evmhess fanw 31 (0x1f) rd ra rb 10110000011 evx evmhessf anw evmhess iaaw 31 (0x1f) rd ra rb 10100000001 evx evmhessi aaw evmhess ianw 31 (0x1f) rd ra rb 10110000001 evx evmhessi anw evmheu mi 31 (0x1f) rd ra rb 10000001000 evx evmheum i evmheu mia 31 (0x1f) rd ra rb 10000101000 evx evmheum ia evmheu miaaw 31 (0x1f) rd ra rb 10100001000 evx evmheum iaaw evmheu mianw 31 (0x1f) rd ra rb 10110001000 evx evmheum ianw evmheus iaaw 31 (0x1f) rd ra rb 10100000000 evx evmheusi aaw evmheus ianw 31 (0x1f) rd ra rb 10110000000 evx evmheusi anw evmhogs mfaa 31 (0x1f) rd ra rb 10100101111 evx evmhogs mfaa evmhogs mfan 31 (0x1f) rd ra rb 10110101111 evx evmhogs mfan evmhogs miaa 31 (0x1f) rd ra rb 10100101101 evx evmhogs miaa evmhogs mian 31 (0x1f) rd ra rb 10110101101 evx evmhogs mian evmhogu miaa 31 (0x1f) rd ra rb 10100101100 evx evmhogu miaa table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1039/1176 evmhogu mian 31 (0x1f) rd ra rb 10110101100 evx evmhogu mian evmhos mf 31 (0x1f) rd ra rb 10000001111 evx evmhosm f evmhos mfa 31 (0x1f) rd ra rb 10000101111 evx evmhosm fa evmhos mfaaw 31 (0x1f) rd ra rb 10100001111 evx evmhosm faaw evmhos mfanw 31 (0x1f) rd ra rb 10110001111 evx evmhosm fanw evmhos mi 31 (0x1f) rd ra rb 10000001101 evx evmhosm i evmhos mia 31 (0x1f) rd ra rb 10000101101 evx evmhosm ia evmhos miaaw 31 (0x1f) rd ra rb 10100001101 evx evmhosm iaaw evmhos mianw 31 (0x1f) rd ra rb 10110001101 evx evmhosm ianw evmhoss f 31 (0x1f) rd ra rb 10000000111 evx evmhossf evmhoss fa 31 (0x1f) rd ra rb 10000100111 evx evmhossf a evmhoss faaw 31 (0x1f) rd ra rb 10100000111 evx evmhossf aaw evmhoss fanw 31 (0x1f) rd ra rb 10110000111 evx evmhossf anw evmhoss iaaw 31 (0x1f) rd ra rb 10100000101 evx evmhossi aaw evmhoss ianw 31 (0x1f) rd ra rb 10110000101 evx evmhossi anw evmhou mi 31 (0x1f) rd ra rb 10000001100 evx evmhoum i evmhou mia 31 (0x1f) rd ra rb 10000101100 evx evmhoum ia evmhou miaaw 31 (0x1f) rd ra rb 10100001100 evx evmhoum iaaw evmhou mianw 31 (0x1f) rd ra rb 10110001100 evx evmhoum ianw evmhous iaaw 31 (0x1f) rd ra rb 10100000100 evx evmhousi aaw evmhous ianw 31 (0x1f) rd ra rb 10110000100 evx evmhousi anw evmr evmr r d ,r a equivalent to evor r d ,r a ,r a evmr evmra 31 (0x1f) rd ra /// 10011000100 evx evmra evmwhg smfaa 31 (0x1f) rd ra rb 10101101111 evx evmwhgs mfaa evmwhg smfan 31 (0x1f) rd ra rb 10111011111 evx evmwhgs mfan evmwhg smiaa 31 (0x1f) rd ra rb 10101101101 evx evmwhgs miaa table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1040/1176 evmwhg smian 31 (0x1f) rd ra rb 10111011101 evx evmwhgs mian evmwhg ssfaa 31 (0x1f) rd ra rb 10101100111 evx evmwhgs sfaa evmwhg ssfan 31 (0x1f) rd ra rb 10111010111 evx evmwhgs sfan evmwhg umiaa 31 (0x1f) rd ra rb 10101101100 evx evmwhgu miaa evmwhg umian 31 (0x1f) rd ra rb 10111011100 evx evmwhgu mian evmwhs mf 31 (0x1f) rd ra rb 10001001111 evx evmwhsm f evmwhs mfa 31 (0x1f) rd ra rb 10001101111 evx evmwhsm fa evmwhs mfaaw 31 (0x1f) rd ra rb 10101001111 evx evmwhsm faaw evmwhs mfanw 31 (0x1f) rd ra rb 10111001111 evx evmwhsm fanw evmwhs mi 31 (0x1f) rd ra rb 10001001101 evx evmwhsm i evmwhs mia 31 (0x1f) rd ra rb 10001101101 evx evmwhsm ia evmwhs miaaw 31 (0x1f) rd ra rb 10101001101 evx evmwhsm iaaw evmwhs mianw 31 (0x1f) rd ra rb 10111001101 evx evmwhsm ianw evmwhs sf 31 (0x1f) rd ra rb 10001000111 evx evmwhssf evmwhs sfa 31 (0x1f) rd ra rb 10001100111 evx evmwhssf a evmwhs sfaaw 31 (0x1f) rd ra rb 10101000111 evx evmwhssf aaw evmwhs sfanw 31 (0x1f) rd ra rb 10111000111 evx evmwhssf anw evmwhs sianw 31 (0x1f) rd ra rb 10111000101 evx evmwhssi anw evmwhs smaaw 31 (0x1f) rd ra rb 10101000101 evx evmwhss maaw evmwhu mi 31 (0x1f) rd ra rb 10001001100 evx evmwhu mi evmwhu mia 31 (0x1f) rd ra rb 10001101100 evx evmwhu mia evmwhu siaaw 31 (0x1f) rd ra rb 10101000100 evx evmwhusi aaw evmwhu sianw 31 (0x1f) rd ra rb 10111000100 evx evmwhusi anw evmwls mf 31 (0x1f) rd ra rb 10001001011 evx evmwlsmf evmwls mfa 31 (0x1f) rd ra rb 10001101011 evx evmwlsmf a evmwls mfaaw 31 (0x1f) rd ra rb 10101001011 evx evmwlsmf aaw table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1041/1176 evmwls mfanw 31 (0x1f) rd ra rb 10111001011 evx evmwlsmf anw evmwls miaaw 31 (0x1f) rd ra rb 10101001001 evx evmwlsmi aaw evmwls mianw 31 (0x1f) rd ra rb 10111001001 evx evmwlsmi anw evmwlss f 31 (0x1f) rd ra rb 10001000011 evx evmwlssf evmwlss fa 31 (0x1f) rd ra rb 10001100011 evx evmwlssf a evmwlss faaw 31 (0x1f) rd ra rb 10101000011 evx evmwlssf aaw evmwlss fanw 31 (0x1f) rd ra rb 10111000011 evx evmwlssf anw evmwlssi aaw 31 (0x1f) rd ra rb 10101000001 evx evmwlssi aaw evmwlssi anw 31 (0x1f) rd ra rb 10111000001 evx evmwlssi anw evmwlu mi 31 (0x1f) rd ra rb 10001001000 evx evmwlumi evmwlu mia 31 (0x1f) rd ra rb 10001101000 evx evmwlumi a evmwlu miaaw 31 (0x1f) rd ra rb 10101001000 evx evmwlumi aaw evmwlu mianw 31 (0x1f) rd ra rb 10111001000 evx evmwlumi anw evmwlus iaaw 31 (0x1f) rd ra rb 10101000000 evx evmwlusi aaw evmwlus ianw 31 (0x1f) rd ra rb 10111000000 evx evmwlusi anw evmwsm f 31 (0x1f) rd ra rb 10001011011 evx evmwsmf evmwsm fa 31 (0x1f) rd ra rb 10001111011 evx evmwsmf a evmwsm faa 31 (0x1f) rd ra rb 10101011011 evx evmwsmf aa evmwsm fan 31 (0x1f) rd ra rb 10111011011 evx evmwsmf an evmwsm i 31 (0x1f) rd ra rb 10001011001 evx evmwsmi evmwsm ia 31 (0x1f) rd ra rb 10001111001 evx evmwsmi a evmwsm iaa 31 (0x1f) rd ra rb 10101011001 evx evmwsmi aa evmwsm ian 31 (0x1f) rd ra rb 10111011001 evx evmwsmi an evmwssf 31 (0x1f) rd ra rb 10001010011 evx evmwssf evmwssf a 31 (0x1f) rd ra rb 10001110011 evx evmwssfa evmwssf aa 31 (0x1f) rd ra rb 10101010011 evx evmwssfa a table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1042/1176 evmwssf an 31 (0x1f) rd ra rb 10111010011 evx evmwssfa n evmwum i 31 (0x1f) rd ra rb 10001011000 evx evmwumi evmwum ia 31 (0x1f) rd ra rb 10001111000 evx evmwumi a evmwum iaa 31 (0x1f) rd ra rb 10101011000 evx evmwumi aa evmwum ian 31 (0x1f) rd ra rb 10111011000 evx evmwumi an evnand 31 (0x1f) rd ra rb 01000011110 evx evnand evneg 31 (0x1f) rd ra /// 01000001001 evx evneg evnor 31 (0x1f) rd ra rb 01000011000 evx evnor evnot evnot r d ,r a equivalent to evnor r d ,r a ,r a evnot evor 31 (0x1f) rd ra rb 01000010111 evx evor evorc 31 (0x1f) rd ra rb 01000011011 evx evorc evrlw 31 (0x1f) rd ra rb 01000101000 evx evrlw evrlwi 31 (0x1f) rd ra uimm 01000101010 evx evrlwi evrndw 31 (0x1f) rd ra uimm 01000001100 evx evrndw evsel 31 (0x1f) rd ra rb 01001111 crfs evx evsel evslw 31 (0x1f) rd ra rb 01000100100 evx evslw evslwi 31 (0x1f) rd ra uimm 01000100110 evx evslwi evsplatfi 31 (0x1f) rd simm /// 01000101011 evx evsplatfi evsplati 31 (0x1f) rd simm /// 01000101001 evx evsplati evsrwis 31 (0x1f) rd ra uimm 01000100011 evx evsrwis evsrwiu 31 (0x1f) rd ra uimm 01000100010 evx evsrwiu evsrws 31 (0x1f) rd ra rb 01000100001 evx evsrws evsrwu 31 (0x1f) rd ra rb 01000100000 evx evsrwu evstdd 31 (0x1f) rd ra uimm 8 01100100001 evx evstdd evstddx 31 (0x1f) rs ra rb 01100100000 evx evstddx evstdh 31 (0x1f) rs ra uimm 8 01100100101 evx evstdh evstdhx 31 (0x1f) rs ra rb 01100100100 evx evstdhx evstdw 31 (0x1f) rs ra uimm 8 01100100011 evx evstdw evstdwx 31 (0x1f) rs ra rb 01100100010 evx evstdwx evstwhe 31 (0x1f) rs ra uimm 10 01100110001 evx evstwhe evstwhex 31 (0x1f) rs ra rb 01100110000 evx evstwhex evstwho 31 (0x1f) rs ra uimm 10 01100110101 evx evstwho evstwhox 31 (0x1f) rs ra rb 01100110100 evx evstwhox evstwwe 31 (0x1f) rs ra uimm 10 01100111001 evx evstwwe evstwwex 31 (0x1f) rs ra rb 01100111000 evx evstwwex evstwwo 31 (0x1f) rs ra uimm 10 01100111101 evx evstwwo evstwwox 31 (0x1f) rs ra rb 01100111100 evx evstwwox table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1043/1176 evsubfs miaaw 31 (0x1f) rd ra /// 10011001011 evx evsubfsm iaaw evsubfss iaaw 31 (0x1f) rd ra /// 10011000011 evx evsubfssi aaw evsubfu miaaw 31 (0x1f) rd ra /// 10011001010 evx evsubfum iaaw evsubfus iaaw 31 (0x1f) rd ra /// 10011000010 evx evsubfusi aaw evsubfw 31 (0x1f) rd ra rb 01000000100 evx evsubfw evsubifw 31 (0x1f) rd uimm rb 01000000110 evx evsubifw evsubiw evsubiw r d ,r b ,uimm equivalent to evsubifw r d , uimm ,r b evsubiw evsubw evsubw r d ,r b ,r a equivalent to evsubfw r d ,r a ,r b evsubw evxor 31 (0x1f) rd ra rb 01000010110 evx evxor extlwi extlwi r a ,r s , n , b (n > 0) equivalent to rlwinm r a ,r s , b ,0, n ? 1 extlwi extrwi extrwi r a ,r s , n , b ( n > 0) equivalent to rlwinm r a ,r s , b + n , 32 ? n ,31 extrwi extsb 31 (0x1f) rs ra /// 11101110100 x extsb extsb. 31 (0x1f) rs ra /// 11101110101 x extsb. extsh 31 (0x1f) rs ra /// 11100110100 x extsh extsh. 31 (0x1f) rs ra /// 11100110101 x extsh. fres 6 59(0x3b) frd /// frb /// 1 1 0 0 0 0 a fres fres. 6 59(0x3b) frd /// frb /// 1 1 0 0 0 1 a fres. fsel 6 63(0x3f) frd fra frb frc 1 0 1 1 1 0 a fsel fsel. 6 63(0x3f) frd fra frb frc 1 0 1 1 1 1 a fsel. icbi 31 (0x1f) /// ra rb 1111010110 / x icbi icblc 31 (0x1f) ct ra rb 00111001100 x icblc icbt 31 (0x1f) ct ra rb 0000010110 / x icbt icbtls 31 (0x1f) ct ra rb 01111001100 x icbtls inslwi inslwi r a ,r s , n , b ( n > 0) equivalent to rlwimi r a ,r s , 32 ? b , b , ( b + n ) ? 1 inslwi insrwi insrwi r a ,r s , n , b ( n > 0) equivalent to rlwimi r a ,r s , 32 ? ( b + n ) , b , ( b + n ) ? 1 insrwi isel 31 (0x1f) rd ra rb crb 0 1 1 1 1 0 x isel iseleq iseleq r d ,r a ,r b equivalent to isel r d ,r a ,r b ,2 iseleq iselgt iselgt r d ,r a ,r b equivalent to isel r d ,r a ,r b ,1 iselgt isellt isellt r d ,r a ,r b equivalent to isel r d ,r a ,r b ,0 isellt isync 19 (0x13) /// 0010010110 / xl isync la la r d ,d(r a ) equivalent to addi r d, r a , d la lbz 34(0x22) rd ra d d lbz lbzu 35(0x23) rd ra d d lbzu lbzux 31 (0x1f) rd ra rb 0001110111 / x lbzux lbzx 31 (0x1f) rd ra rb 0001010111 / x lbzx lha 42(0x2a) rd ra d d lha lhau 43(0x2b) rd ra d d lhau table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1044/1176 lhaux 31 (0x1f) rd ra rb 0101110111 / x lhaux lhax 31 (0x1f) rd ra rb 0101010111 / x lhax lhbrx 31 (0x1f) rd ra rb 1100010110 / x lhbrx lhz 40(0x28) rd ra d d lhz lhzu 41(0x29) rd ra d d lhzu lhzux 31 (0x1f) rd ra rb 0100110111 / x lhzux lhzx 31 (0x1f) rd ra rb 0100010111 / x lhzx li li r d ,value equivalent to addi r d ,0, value li lis lis r d ,value equivalent to addis r d ,0, value lis lmw 46(0x2e) rd ra d d lmw lwarx 31 (0x1f) rd ra rb 0000010100 / x lwarx lwbrx 31 (0x1f) rd ra rb 1000010110 / x lwbrx lwz 32 (0x20) rd ra d d lwz lwzu 33 (0x21) rd ra d d lwzu lwzux 31 (0x1f) rd ra rb 0000110111 / x lwzux lwzx 31 (0x1f) rd ra rb 0000010111 / x lwzx mbar 31 (0x1f) mo /// 1101010110 / x mbar mcrf 19 (0x13) crfd // crfs /// 0000000000 / xl mcrf mcrxr 31 (0x1f) crfd /// 1000000000 / x mcrxr mfcr mtcr r s equivalent to mtcrf 0xff,r s mfcr mfcr 31 (0x1f) rd /// 0000010011 / x mfcr mfdcr 31 (0x1f) rd dcrn5?9 dcrn0?4 0 1 01000011 / xfx mfdcr mfmsr 7 31 (0x1f) rd /// 0001010011 / x mfmsr mfpmr31 (0x1f) rd pmrn5?9 pmrn0?4 01010011100 xfx mfpmr mf regname mf regname r d equivalent to mfspr r d ,spr n mf regname mfspr (8) 31 (0x1f) rd spr[5?9] spr[0?4] 0101010011 / xfx mfspr mr mr r a ,r s equivalent to or r a ,r s ,r s mr msync31 (0x1f) /// 1001010110 / x msync mtcr mtcr r s equivalent to mtcrf 0xff ,r s mtcr mtcrf 31 (0x1f) rs / crm / 0010010000 / xfx mtcrf mtdcr 31 (0x1f) rs dcrn5?9 dcrn0?4 0 1 11000011 / xfx mtdcr mtmsr 731 (0x1f) rs /// 0010010010 / x mtmsr mtpmr31 (0x1f) rs pmrn5?9 pmrn0?4 01110011100 xfx mtpmr mt regname mt regname r s equivalent to mtspr spr n r s mt regname mtspr 8 31 (0x1f) rs spr[5?9] spr[0?4] 0111010011 / xfx mtspr mulhw 31 (0x1f) rd ra rb / 0010010110 x mulhw mulhw. 31 (0x1f) rd ra rb / 0010010111 x mulhw. mulhwu 31 (0x1f) rd ra rb / 0000010110 x mulhwu mulhwu. 31 (0x1f) rd ra rb / 0000010111 x mulhwu. mulli 07 rd ra simm d mulli table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1045/1176 mullw 31 (0x1f) rd ra rb 00111010110 x mullw mullw. 31 (0x1f) rd ra rb 00111010111 x mullw. mullwo 31 (0x1f) rd ra rb 10111010110 x mullwo mullwo. 31 (0x1f) rd ra rb 10111010111 x mullwo. nand 31 (0x1f) rs ra rb 01110111000 x nand nand. 31 (0x1f) rs ra rb 01110111001 x nand. neg 31 (0x1f) rd ra /// 00011010000 x neg neg. 31 (0x1f) rd ra /// 00011010001 x neg. nego 31 (0x1f) rd ra /// 10011010000 x nego nego. 31 (0x1f) rd ra /// 10011010001 x nego. nop nop equivalent to ori 0,0,0 nop nor 31 (0x1f) rs ra rb 00011111000 x nor nor. 31 (0x1f) rs ra rb 00011111001 x nor. not not r a ,r s equivalent to nor r a ,r s ,r s not or 31 (0x1f) rs ra rb 01101111000 x or or. 31 (0x1f) rs ra rb 01101111001 x or. orc 31 (0x1f) rs ra rb 01100111000 x orc orc. 31 (0x1f) rs ra rb 01100111001 x orc. ori 24 (0x18) rs ra uimm d ori oris 25 (0x19) rs ra uimm d oris rfci 19 (0x13) /// 0000110011 / xl rfci rfdi 7 0 100110000 0 0 0 0 0 0 0 0 0 0 0 0 0 001001110 x rfdi rfi 7 19 (0x13) /// 0000110010 / xl rfi rfmci 7 19 (0x13) /// 0000100110 / xl rfmci rlwimi 20 (0x14) rs ra sh mb me 0 m rlwimi rlwimi. 20 (0x14) rs ra sh mb me 1 m rlwimi. rlwinm 21 (0x15) rs ra sh mb me 0 m rlwinm rlwinm. 21 (0x15) rs ra sh mb me 1 m rlwinm. rlwnm 23 (0x17) rs ra rb mb me 0 m rlwnm rlwnm. 23 (0x17) rs ra rb mb me 1 m rlwnm. rotlw rotlw r a ,r s ,r b equivalent to rlwnm r a ,r s ,r b ,0,31 rotlw rotlwi rotlwi r a ,r s , n equivalent to rlwinm r a ,r s , n ,0,31 rotlwi rotrwi rotrwi r a ,r s , n equivalent to rlwinm r a ,r s , 32 ? n ,0,31 rotrwi sc 17 (0x11) /// 1 / sc sc slw 31 (0x1f) rs ra rb 00000110000 x slw slw. 31 (0x1f) rs ra rb 00000110001 x slw. slwi slwi r a ,r s , n (n < 32) equivalent to rlwinm r a ,r s , n ,0, 31 ? n slwi sraw 31 (0x1f) rs ra rb 11000110000 x sraw sraw. 31 (0x1f) rs ra rb 11000110001 x sraw. srawi 31 (0x1f) rs ra sh 11001110000 x srawi table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1046/1176 srawi. 31 (0x1f) rs ra sh 11001110001 x srawi. srw 31 (0x1f) rs ra rb 10000110000 x srw srw. 31 (0x1f) rs ra rb 10000110001 x srw. srwi srwi r a ,r s , n (n < 32)equivalent to rlwinm r a ,r s , 32 ? n , n ,31 srwi stb 38(0x26) rs ra d d stb stbu 39(0x27) rs ra d d stbu stbux 31 (0x1f) rs ra rb 00111101110 x stbux stbx 31 (0x1f) rs ra rb 00110101110 x stbx sth 44(0x2c) rs ra d d sth sthbrx 31 (0x1f) rs ra rb 1110010110 / x sthbrx sthu 45(0x2d) rs ra d d sthu sthux 31 (0x1f) rs ra rb 0110110111 / x sthux sthx 31 (0x1f) rs ra rb 0110010111 / x sthx stmw 47(0x2f) rs ra d d stmw stw 36(0x24) rs ra d d stw stwbrx 31 (0x1f) rs ra rb 1010010110 / x stwbrx stwcx. 31 (0x1f) rs ra rb 00100101101 x stwcx. stwu 37(0x25) rs ra d d stwu stwux 31 (0x1f) rs ra rb 0010110111 / d stwux stwx 31 (0x1f) rs ra rb 0010010111 / d stwx sub sub r d ,r a ,r b equivalent to subf r d ,r b ,r a sub subc subc r d ,r a ,r b equivalent to subfc r d ,r b ,r a subc subf 31 (0x1f) rd ra rb 00001010000 x subf subf. 31 (0x1f) rd ra rb 00001010001 x subf. subfc 31 (0x1f) rd ra rb 00000010000 x subfc subfc. 31 (0x1f) rd ra rb 00000010001 x subfc. subfco 31 (0x1f) rd ra rb 10000010000 x subfco subfco. 31 (0x1f) rd ra rb 10000010001 x subfco. subfe 31 (0x1f) rd ra rb 00100010000 x subfe subfe. 31 (0x1f) rd ra rb 00100010001 x subfe. subfeo 31 (0x1f) rd ra rb 10100010000 x subfeo subfeo. 31 (0x1f) rd ra rb 10100010001 x subfeo. subfic 08 rd ra simm d subfic subfme 31 (0x1f) rd ra /// 00111010000 x subfme subfme. 31 (0x1f) rd ra /// 00111010001 x subfme. subfmeo 31 (0x1f) rd ra /// 10111010000 x subfmeo subfmeo. 31 (0x1f) rd ra /// 10111010001 x subfmeo. subfo 31 (0x1f) rd ra rb 10001010000 x subfo subfo. 31 (0x1f) rd ra rb 10001010001 x subfo. subfze 31 (0x1f) rd ra /// 00110010000 x subfze table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1047/1176 subfze. 31 (0x1f) rd ra /// 00110010001 x subfze. subfzeo 31 (0x1f) rd ra /// 10110010000 x subfzeo subfzeo. 31 (0x1f) rd ra /// 10110010001 x subfzeo. subi subi r d ,r a ,value equivalent to addi r d ,r a , ?value subi subic subic r d ,r a ,value equivalent to addic r d ,r a , ?value subic subic. subic. r d ,r a ,value equivalent to addic. r d ,r a , ?value subic. subis subis r d ,r a ,value equivalent to addis r d ,r a , ?value subis tlbie 6,731 (0x1f) /// /// rb 01001100100 x tlbie tlbivax31 (0x1f) /// ra rb 1100010010 / x tlbivax tlbre 31 (0x1f) ///9 1110110010 / x tlbre tlbsx 31 (0x1f) ///12 ra rb 1110010010/12 x tlbsx tlbsync 6,7 31 (0x1f) /// /// /// 1000110110 / x tlbsync tlbwe 31 (0x1f) ///12 1111010010 / x tlbwe tw 31 (0x1f) to ra rb 0000000100 / x tw tweq tweq r a ,simm equivalent to tw 4,r a , simm tweq tweqi tweqi r a ,simm equivalent to twi 4,r a , simm tweqi twge twge r a ,simm equivalent to tw 12,r a , simm twge twgei twgei r a ,simm equivalent to twi 12,r a , simm twgei twgt twgt r a ,simm equivalent to tw 8,r a , simm twgt twgti twgti r a ,simm equivalent to twi 8,r a , simm twgti twi 03 to ra simm d twi twle twle r a ,simm equivalent to tw 20,r a , simm twle twlei twlei r a ,simm equivalent to twi 20,r a , simm twlei twlge twlge r a ,simm equivalent to tw 12,r a , simm twlge twlgei twlgei r a ,simm equivalent to twi 12,r a , simm twlgei twlgt twlgt r a ,simm equivalent to tw 1,r a , simm twlgt twlgti twlgti r a ,simm equivalent to twi 1,r a , simm twlgti twlle twlle r a ,simm equivalent to tw 6,r a , simm twlle twllei twllei r a ,simm equivalent to twi 6,r a , simm twllei twllt twllt r a ,simm equivalent to tw 2,r a , simm twllt twllti twllti r a ,simm equivalent to twi 2,r a , simm twllti twlng twlng r a ,simm equivalent to tw 6,r a , simm twlng twlngi twlngi r a ,simm equivalent to twi 6,r a , simm twlngi twlnl twlnl r a ,simm equivalent to tw 5,r a , simm twlnl twlnli twlnli r a ,simm equivalent to twi 5,r a , simm twlnli twlt twlt r a ,simm equivalent to tw 16,r a , simm twlt twlti twlti r a ,simm equivalent to twi 16,r a , simm twlti twne twne r a ,simm equivalent to tw 24,r a , simm twne twnei twnei r a ,simm equivalent to twi 24,r a , simm twnei table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1048/1176 a.2 instructions sorted by primary opcodes (decimal and hexadecimal) table 270 lists instructions by their primary (0?5) opcodes in decimal and hexadecimal format. twng twng r a ,simm equivalent to tw 20,r a , simm twng twngi twngi r a ,simm equivalent to twi 20,r a , simm twngi twnl twnl r a ,simm equivalent to tw 12,r a , simm twnl twnli twnli r a ,simm equivalent to twi 12,r a , simm twnli wait 31 (0x1f) /// 0 000111110 /wait wrtee31 (0x1f) rs /// 0010000011 / x wrtee wrteei31 (0x1f) /// e /// 0010100011 / x wrteei xor 31 (0x1f) rs ra rb 01001111000 x xor xor. 31 (0x1f) rs ra rb 01001111001 x xor. xori 26 (0x1a) rs ra uimm d xori xoris 27 (0x1b) rs ra uimm d xoris 1. simplified mnemonics for branch instructions that do not test a cr bit should not specify one; a programming error may occur. 2. the value in the bi operand selects cr n [2], the eq bit. 3. the value in the bi operand selects cr n [0], the lt bit. 4. the value in the bi operand selects cr n [1], the gt bit. 5. the value in the bi operand selects cr n [3], the so bit. 6. optional to the powerpc classic architecture. 7. supervisor-level instruction 8. access level is detemined by whether the spr is defined as a user- or supervisor-level spr. table 269. instructions sorted by mnemonic (decimal and hexadecimal) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic table 270. instructions sorted by primary opcodes (decimal and hexadecimal) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic rfdi 1 01001100000000000000000001001110 x rfdi twi 03 to ra simm d twi brinc 04 rd ra rb 01000001111evx brinc efdabs 04 rd ra /// 01011100100efx efdabs efdadd 04 rd ra rb 01011100000efx efdadd efdcfs 04 rd 00000 rb 0 1011101111efx efdcfs efdcfsf 04 rd /// rb 01011110011efx efdcfsf efdcfsi 04 rd /// rb 01011110001efx efdcfsi efdcfuf 04 rd /// rb 01011110010efx efdcfuf efdcfui 04 rd /// rb 01011110000efx efdcfui efdcmpeq 04 crfd // ra rb 01011101110efx efdcmpeq efdcmpgt 04 crfd // ra rb 01011101100efx efdcmpgt efdcmplt 04 crfd // ra rb 01011101101efx efdcmplt instruction set listings RM0004 1049/1176 efdctsf 04 rd /// rb 01011110111efx efdctsf efdctsi 04 rd /// rb 01011110101efx efdctsi efdctsiz 04 rd /// rb 01011111010efx efdctsiz efdctuf 04 rd /// rb 01011110110efx efdctuf efdctui 04 rd /// rb 01011110100efx efdctui efdctuiz 04 rd /// rb 01011111000efx efdctuiz efddiv 04 rd ra rb 01011101001efx efddiv efdmul 04 rd ra rb 01011101000efx efdmul efdnabs 04 rd ra /// 01011100101efx efdnabs efdneg 04 rd ra /// 01011100110efx efdneg efdsub 04 rd ra rb 01011100001efx efdsub efdtsteq 04 crfd // ra rb 01011111110efx efdtsteq efdtstgt 04 crfd // ra rb 01011111100efx efdtstgt efdtstlt 04 crfd // ra rb 01011111101efx efdtstlt efsabs 04 rd ra /// 01011000100efx efsabs efsadd 04 rd ra rb 01011000000efx efsadd efscfd 04 rd 00000 rb 0 1011001111efx efscfd efscfsf 04 rd /// rb 01011010011efx efscfsf efscfsi 04 rd /// rb 01011010001efx efscfsi efscfuf 04 rd /// rb 01011010010efx efscfuf efscfui 04 rd /// rb 01011010000efx efscfui efscmpeq 04 crfd // ra rb 01011001110efx efscmpeq efscmpgt 04 crfd // ra rb 01011001100efx efscmpgt efscmplt 04 crfd // ra rb 01011001101efx efscmplt efsctsf 04 rd /// rb 01011010111efx efsctsf efsctsi 04 rd /// rb 01011010101efx efsctsi efsctsiz 04 rd /// rb 01011011010efx efsctsiz efsctuf 04 rd /// rb 01011010110efx efsctuf efsctui 04 rd /// rb 01011010100efx efsctui efsctuiz 04 rd /// rb 01011011000efx efsctuiz efsdiv 04 rd ra rb 01011001001efx efsdiv efsmul 04 rd ra rb 01011001000efx efsmul efsnabs 04 rd ra /// 01011000101efx efsnabs efsneg 04 rd ra /// 01011000110efx efsneg efssub 04 rd ra rb 01011000001efx efssub efststeq 04 crfd // ra rb 01011011110efx efststeq efststgt 04 crfd // ra rb 01011011100efx efststgt efststlt 04 crfd // ra rb 01011011101efx efststlt mulli 07 rd ra simm d mulli subfic 08 rd ra simm d subfic table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic RM0004 instruction set listings 1050/1176 cmpli 10 (0x0a) crfd / l ra uimm d cmpli cmpi 11 (0x0b) crfd / l ra simm d cmpi addic 12 (0x0c) rd ra simm d addic addic. 13 (0x0d) rd ra simm d addic. addi 14 (0x0e) rd ra simm d addi addis 15 (0x0f) rd ra simm d addis bc 16 (0x10) bo bi bd 0 0 b bc bca 16 (0x10) bo bi bd 1 0 b bca bcl 16 (0x10) bo bi bd 0 1 b bcl bcla 16 (0x10) bo bi bd 1 1 b bcla sc 17 (0x11) /// 1 / sc sc b 18 (0x12) li 0 0 i b ba 18 (0x12) li 1 0 i ba bl 18 (0x12) li 0 1 i bl bla 18 (0x12) li 1 1 i bla rfci 19 (0x13) /// 0000110011 / xl rfci rfmci 1 19 (0x13) /// 0000100110 / xl rfmci mcrf 19 (0x13) crfd // crfs /// 0000000000 / xl mcrf bclr 19 (0x13) bo bi /// 00000100000 xl bclr bclrl 19 (0x13) bo bi /// 00000100001 xl bclrl crnor 19 (0x13) crbd crba crbb 0000100001 / xl crnor rfi (1) 19 (0x13) /// 0000110010 / xl rfi crandc 19 (0x13) crbd crba crbb 0010000001 / xl crandc isync 19 (0x13) /// 0010010110 / xl isync crxor 19 (0x13) crbd crba crbb 0011000001 / xl crxor crand 19 (0x13) crbd crba crbb 0100000001 / xl crand crnand 19 (0x13) crbd crba crbb 0011100001 / xl crnand creqv 19 (0x13) crbd crba crbb 0100100001 / xl creqv crorc 19 (0x13) crbd crba crbb 0110100001 / xl crorc cror 19 (0x13) crbd crba crbb 0111000001 / xl cror bcctr 19 (0x13) bo bi /// 10000100000 xl bcctr bcctrl 19 (0x13) bo bi /// 10000100001 xl bcctrl rlwimi 20 (0x14) rs ra sh mb me 0 m rlwimi rlwimi. 20 (0x14) rs ra sh mb me 1 m rlwimi. rlwinm 21 (0x15) rs ra sh mb me 0 m rlwinm rlwinm. 21 (0x15) rs ra sh mb me 1 m rlwinm. rlwnm 23 (0x17) rs ra rb mb me 0 m rlwnm rlwnm. 23 (0x17) rs ra rb mb me 1 m rlwnm. ori 24 (0x18) rs ra uimm d ori oris 25 (0x19) rs ra uimm d oris table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic instruction set listings RM0004 1051/1176 xori 26 (0x1a) rs ra uimm d xori xoris 27 (0x1b) rs ra uimm d xoris andi. 28 (0x1c) rs ra uimm d andi. andis. 29 (0x1d) rs ra uimm d andis. dcblc 31 (0x1f) ct ra rb 01100001100 x dcblc dcbtls 31 (0x1f) ct ra rb 00101001100 x dcbtls dcbtstls 31 (0x1f) ct ra rb 00100001100 x dcbtstls evabs 31 (0x1f) rd ra /// 01000001000evx evabs evaddiw 31 (0x1f) rd uimm rb 01000000010evx evaddiw evaddsm iaaw 31 (0x1f) rd ra /// 10011001001evx evaddsm iaaw evaddssi aaw 31 (0x1f) rd ra /// 10011000001evx evaddssi aaw evaddum iaaw 31 (0x1f) rd ra /// 10011001000evx evaddum iaaw evaddusi aaw 31 (0x1f) rd ra /// 10011000000evx evaddusi aaw evaddw 31 (0x1f) rd ra rb 01000000000evx evaddw evand 31 (0x1f) rd ra rb 01000010001evx evand evandc 31 (0x1f) rd ra rb 01000010010evx evandc evcmpeq 31 (0x1f) crfd // ra rb 01000110100evx evcmpeq evcmpgts 31 (0x1f) crfd // ra rb 01000110001evx evcmpgts evcmpgtu 31 (0x1f) crfd // ra rb 01000110000evx evcmpgtu evcmplts 31 (0x1f) crfd // ra rb 01000110011evx evcmplts evcmpltu 31 (0x1f) crfd // ra rb 01000110010evx evcmpltu evcntlsw 31 (0x1f) rd ra /// 01000001110evx evcntlsw evcntlzw 31 (0x1f) rd ra /// 01000001101evx evcntlzw evdivws 31 (0x1f) rd ra rb 10011000110evx evdivws evdivwu 31 (0x1f) rd ra rb 10011000111evx evdivwu eveqv 31 (0x1f) rd ra rb 01000011001evx eveqv evextsb 31 (0x1f) rd ra /// 01000001010evx evextsb evextsh 31 (0x1f) rd ra /// 01000001011evx evextsh evfsabs 31 (0x1f) rd ra /// 01010000100evx evfsabs evfsadd 31 (0x1f) rd ra rb 01010000000evx evfsadd evfscfsf 31 (0x1f) rd /// rb 01010010011evx evfscfsf evfscfsi 31 (0x1f) rd /// rb 01010010001evx evfscfsi evfscfuf 31 (0x1f) rd /// rb 01010010010evx evfscfuf evfscfui 31 (0x1f) rd /// rb 01010010000evx evfscfui evfscmpeq 31 (0x1f) crfd // ra rb 01010001110evx evfscmpeq evfscmpgt 31 (0x1f) crfd // ra rb 01010001100evx evfscmpgt evfscmplt 31 (0x1f) crfd // ra rb 01010001101evx evfscmplt evfsctsf 31 (0x1f) rd /// rb 01010010111evx evfsctsf table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic RM0004 instruction set listings 1052/1176 evfsctsi 31 (0x1f) rd /// rb 01010010101evx evfsctsi evfsctsiz 31 (0x1f) rd /// rb 01010011010evx evfsctsiz evfsctuf 31 (0x1f) rd /// rb 01010010110evx evfsctuf evfsctui 31 (0x1f) rd /// rb 01010010100evx evfsctui evfsctuiz 31 (0x1f) rd /// rb 01010011000evx evfsctuiz evfsdiv 31 (0x1f) rd ra rb 01010001001evx evfsdiv evfsmul 31 (0x1f) rd ra rb 01010001000evx evfsmul evfsnabs 31 (0x1f) rd ra /// 01010000101evx evfsnabs evfsneg 31 (0x1f) rd ra /// 01010000110evx evfsneg evfssub 31 (0x1f) rd ra rb 01010000001evx evfssub evfststeq 31 (0x1f) crfd // ra rb 01010011110evx evfststeq evfststgt 31 (0x1f) crfd // ra rb 01010011100evx evfststgt evfststlt 31 (0x1f) crfd // ra rb 01010011101evx evfststlt evldd 31 (0x1f) rd ra uimm 2 01100000001evx evldd evlddx 31 (0x1f) rd ra rb 01100000000evx evlddx evldh 31 (0x1f) rd ra uimm 2 01100000101evx evldh evldhx 31 (0x1f) rd ra rb 01100000100evx evldhx evldw 31 (0x1f) rd ra uimm 2 01100000011evx evldw evldwx 31 (0x1f) rd ra rb 01100000010evx evldwx evlhhesp lat 31 (0x1f) rd ra uimm 2 01100001001evx evlhhesp lat evlhhesp latx 31 (0x1f) rd ra rb 01100001000evx evlhhesp latx evlhhoss plat 31 (0x1f) rd ra uimm 3 01100001111evx evlhhoss plat evlhhoss platx 31 (0x1f) rd ra rb 01100001110evx evlhhoss platx evlhhous plat 31 (0x1f) rd ra uimm 3 01100001101evx evlhhou splat evlhhous platx 31 (0x1f) rd ra rb 01100001100evx evlhhou splatx evlwhe 31 (0x1f) rd ra uimm 2 01100010001evx evlwhe evlwhex 31 (0x1f) rd ra rb 01100010000evx evlwhex evlwhos 31 (0x1f) rd ra uimm 4 01100010111evx evlwhos evlwhosx 31 (0x1f) rd ra rb 01100010110evx evlwhosx evlwhou 31 (0x1f) rd ra uimm 4 01100010101evx evlwhou evlwhoux 31 (0x1f) rd ra rb 01100010100evx evlwhoux evlwhsplat 31 (0x1f) rd ra uimm 4 01100011101evx evlwhsplat evlwhspl atx 31 (0x1f) rd ra rb 01100011100evx evlwhspl atx evlwwspl at 31 (0x1f) rd ra uimm 4 01100011001evx evlwwspl at table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic instruction set listings RM0004 1053/1176 evlwwspl atx 31 (0x1f) rd ra rb 01100011000evx evlwwspl atx evmerge hi 31 (0x1f) rd ra rb 01000101100evx evmerge hi evmerge hilo 31 (0x1f) rd ra rb 01000101110evx evmerge hilo evmergel o 31 (0x1f) rd ra rb 01000101101evx evmerge lo evmergel ohi 31 (0x1f) rd ra rb 01000101111evx evmerge lohi evmhegs mfaa 31 (0x1f) rd ra rb 10100101011evx evmhegs mfaa evmhegs mfan 31 (0x1f) rd ra rb 10110101011evx evmhegs mfan evmhegs miaa 31 (0x1f) rd ra rb 10100101001evx evmhegs miaa evmhegs mian 31 (0x1f) rd ra rb 10110101001evx evmhegs mian evmhegu miaa 31 (0x1f) rd ra rb 10100101000evx evmheg umiaa evmhegu mian 31 (0x1f) rd ra rb 10110101000evx evmheg umian evmhes mf 31 (0x1f) rd ra rb 10000001011evx evmhes mf evmhes mfa 31 (0x1f) rd ra rb 10000101011evx evmhes mfa evmhes mfaaw 31 (0x1f) rd ra rb 10100001011evx evmhes mfaaw evmhes mfanw 31 (0x1f) rd ra rb 10110001011evx evmhes mfanw evmhes mi 31 (0x1f) rd ra rb 10000001001evx evmhes mi evmhes mia 31 (0x1f) rd ra rb 10000101001evx evmhes mia evmhes miaaw 31 (0x1f) rd ra rb 10100001001evx evmhes miaaw evmhes mianw 31 (0x1f) rd ra rb 10110001001evx evmhes mianw evmhessf 31 (0x1f) rd ra rb 10000000011evx evmhessf evmhessfa 31 (0x1f) rd ra rb 10000100011evx evmhessfa evmhess faaw 31 (0x1f) rd ra rb 10100000011evx evmhess faaw evmhess fanw 31 (0x1f) rd ra rb 10110000011evx evmhess fanw evmhess iaaw 31 (0x1f) rd ra rb 10100000001evx evmhess iaaw evmhess ianw 31 (0x1f) rd ra rb 10110000001evx evmhess ianw evmheu mi 31 (0x1f) rd ra rb 10000001000evx evmheu mi table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic RM0004 instruction set listings 1054/1176 evmheu mia 31 (0x1f) rd ra rb 10000101000evx evmheu mia evmheu miaaw 31 (0x1f) rd ra rb 10100001000evx evmheu miaaw evmheu mianw 31 (0x1f) rd ra rb 10110001000evx evmheu mianw evmheus iaaw 31 (0x1f) rd ra rb 10100000000evx evmheus iaaw evmheus ianw 31 (0x1f) rd ra rb 10110000000evx evmheus ianw evmhogs mfaa 31 (0x1f) rd ra rb 10100101111evx evmhog smfaa evmhogs mfan 31 (0x1f) rd ra rb 10110101111evx evmhog smfan evmhogs miaa 31 (0x1f) rd ra rb 10100101101evx evmhog smiaa evmhogs mian 31 (0x1f) rd ra rb 10110101101evx evmhog smian evmhogu miaa 31 (0x1f) rd ra rb 10100101100evx evmhog umiaa evmhogu mian 31 (0x1f) rd ra rb 10110101100evx evmhog umian evmhos mf 31 (0x1f) rd ra rb 10000001111evx evmhos mf evmhos mfa 31 (0x1f) rd ra rb 10000101111evx evmhos mfa evmhos mfaaw 31 (0x1f) rd ra rb 10100001111evx evmhos mfaaw evmhos mfanw 31 (0x1f) rd ra rb 10110001111evx evmhos mfanw evmhos mi 31 (0x1f) rd ra rb 10000001101evx evmhos mi evmhos mia 31 (0x1f) rd ra rb 10000101101evx evmhos mia evmhos miaaw 31 (0x1f) rd ra rb 10100001101evx evmhos miaaw evmhos mianw 31 (0x1f) rd ra rb 10110001101evx evmhos mianw evmhoss f 31 (0x1f) rd ra rb 10000000111evx evmhoss f evmhoss fa 31 (0x1f) rd ra rb 10000100111evx evmhoss fa evmhoss faaw 31 (0x1f) rd ra rb 10100000111evx evmhoss faaw evmhoss fanw 31 (0x1f) rd ra rb 10110000111evx evmhoss fanw evmhoss iaaw 31 (0x1f) rd ra rb 10100000101evx evmhoss iaaw evmhoss ianw 31 (0x1f) rd ra rb 10110000101evx evmhoss ianw evmhou mi 31 (0x1f) rd ra rb 10000001100evx evmhou mi table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic instruction set listings RM0004 1055/1176 evmhou mia 31 (0x1f) rd ra rb 10000101100evx evmhou mia evmhou miaaw 31 (0x1f) rd ra rb 10100001100evx evmhou miaaw evmhou mianw 31 (0x1f) rd ra rb 10110001100evx evmhou mianw evmhous iaaw 31 (0x1f) rd ra rb 10100000100evx evmhou siaaw evmhous ianw 31 (0x1f) rd ra rb 10110000100evx evmhou sianw evmra 31 (0x1f) rd ra /// 10011000100evx evmra evmwhg smfaa 31 (0x1f) rd ra rb 10101101111evx evmwhg smfaa evmwhg smfan 31 (0x1f) rd ra rb 10111011111evx evmwhg smfan evmwhg smiaa 31 (0x1f) rd ra rb 10101101101evx evmwhg smiaa evmwhg smian 31 (0x1f) rd ra rb 10111011101evx evmwhg smian evmwhg ssfaa 31 (0x1f) rd ra rb 10101100111evx evmwhg ssfaa evmwhg ssfan 31 (0x1f) rd ra rb 10111010111evx evmwhg ssfan evmwhg umiaa 31 (0x1f) rd ra rb 10101101100evx evmwhg umiaa evmwhg umian 31 (0x1f) rd ra rb 10111011100evx evmwhg umian evmwhs mf 31 (0x1f) rd ra rb 10001001111evx evmwhs mf evmwhs mfa 31 (0x1f) rd ra rb 10001101111evx evmwhs mfa evmwhs mfaaw 31 (0x1f) rd ra rb 10101001111evx evmwhs mfaaw evmwhs mfanw 31 (0x1f) rd ra rb 10111001111evx evmwhs mfanw evmwhs mi 31 (0x1f) rd ra rb 10001001101evx evmwhs mi evmwhs mia 31 (0x1f) rd ra rb 10001101101evx evmwhs mia evmwhs miaaw 31 (0x1f) rd ra rb 10101001101evx evmwhs miaaw evmwhs mianw 31 (0x1f) rd ra rb 10111001101evx evmwhs mianw evmwhs sf 31 (0x1f) rd ra rb 10001000111evx evmwhs sf evmwhs sfa 31 (0x1f) rd ra rb 10001100111evx evmwhs sfa evmwhs sfaaw 31 (0x1f) rd ra rb 10101000111evx evmwhs sfaaw evmwhs sfanw 31 (0x1f) rd ra rb 10111000111evx evmwhs sfanw table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic RM0004 instruction set listings 1056/1176 evmwhs sianw 31 (0x1f) rd ra rb 10111000101evx evmwhs sianw evmwhs smaaw 31 (0x1f) rd ra rb 10101000101evx evmwhs smaaw evmwhu mi 31 (0x1f) rd ra rb 10001001100evx evmwhu mi evmwhu mia 31 (0x1f) rd ra rb 10001101100evx evmwhu mia evmwhu siaaw 31 (0x1f) rd ra rb 10101000100evx evmwhu siaaw evmwhu sianw 31 (0x1f) rd ra rb 10111000100evx evmwhu sianw evmwls mf 31 (0x1f) rd ra rb 10001001011evx evmwls mf evmwls mfa 31 (0x1f) rd ra rb 10001101011evx evmwls mfa evmwls mfaaw 31 (0x1f) rd ra rb 10101001011evx evmwls mfaaw evmwls mfanw 31 (0x1f) rd ra rb 10111001011evx evmwls mfanw evmwls miaaw 31 (0x1f) rd ra rb 10101001001evx evmwls miaaw evmwls mianw 31 (0x1f) rd ra rb 10111001001evx evmwls mianw evmwlss f 31 (0x1f) rd ra rb 10001000011evx evmwlss f evmwlss fa 31 (0x1f) rd ra rb 10001100011evx evmwlss fa evmwlss faaw 31 (0x1f) rd ra rb 10101000011evx evmwlss faaw evmwlss fanw 31 (0x1f) rd ra rb 10111000011evx evmwlss fanw evmwlssi aaw 31 (0x1f) rd ra rb 10101000001evx evmwlss iaaw evmwlssi anw 31 (0x1f) rd ra rb 10111000001evx evmwlss ianw evmwlu mi 31 (0x1f) rd ra rb 10001001000evx evmwlu mi evmwlu mia 31 (0x1f) rd ra rb 10001101000evx evmwlu mia evmwlu miaaw 31 (0x1f) rd ra rb 10101001000evx evmwlu miaaw evmwlu mianw 31 (0x1f) rd ra rb 10111001000evx evmwlu mianw evmwlus iaaw 31 (0x1f) rd ra rb 10101000000evx evmwlus iaaw evmwlus ianw 31 (0x1f) rd ra rb 10111000000evx evmwlus ianw evmwsm f 31 (0x1f) rd ra rb 10001011011evx evmwsm f evmwsm fa 31 (0x1f) rd ra rb 10001111011evx evmwsm fa table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic instruction set listings RM0004 1057/1176 evmwsm faa 31 (0x1f) rd ra rb 10101011011evx evmwsm faa evmwsm fan 31 (0x1f) rd ra rb 10111011011evx evmwsm fan evmwsm i 31 (0x1f) rd ra rb 10001011001evx evmwsm i evmwsm ia 31 (0x1f) rd ra rb 10001111001evx evmwsm ia evmwsm iaa 31 (0x1f) rd ra rb 10101011001evx evmwsm iaa evmwsm ian 31 (0x1f) rd ra rb 10111011001evx evmwsm ian evmwssf 31 (0x1f) rd ra rb 10001010011evx evmwssf evmwssf a 31 (0x1f) rd ra rb 10001110011evx evmwssf a evmwssf aa 31 (0x1f) rd ra rb 10101010011evx evmwssf aa evmwssf an 31 (0x1f) rd ra rb 10111010011evx evmwssf an evmwum i 31 (0x1f) rd ra rb 10001011000evx evmwum i evmwum ia 31 (0x1f) rd ra rb 10001111000evx evmwum ia evmwum iaa 31 (0x1f) rd ra rb 10101011000evx evmwum iaa evmwum ian 31 (0x1f) rd ra rb 10111011000evx evmwum ian evnand 31 (0x1f) rd ra rb 01000011110evx evnand evneg 31 (0x1f) rd ra /// 01000001001evx evneg evnor 31 (0x1f) rd ra rb 01000011000evx evnor evor 31 (0x1f) rd ra rb 01000010111evx evor evorc 31 (0x1f) rd ra rb 01000011011evx evorc evrlw 31 (0x1f) rd ra rb 01000101000evx evrlw evrlwi 31 (0x1f) rd ra uimm 01000101010evx evrlwi evrndw 31 (0x1f) rd ra uimm 01000001100evx evrndw evsel 31 (0x1f) rd ra rb 0 1 0 0 1 1 1 1 crfs evx evsel evslw 31 (0x1f) rd ra rb 01000100100evx evslw evslwi 31 (0x1f) rd ra uimm 01000100110evx evslwi evsplatfi 31 (0x1f) rd simm /// 01000101011evx evsplatfi evsplati 31 (0x1f) rd simm /// 01000101001evx evsplati evsrwis 31 (0x1f) rd ra uimm 01000100011evx evsrwis evsrwiu 31 (0x1f) rd ra uimm 01000100010evx evsrwiu evsrws 31 (0x1f) rd ra rb 01000100001evx evsrws evsrwu 31 (0x1f) rd ra rb 01000100000evx evsrwu evstdd 31 (0x1f) rd ra uimm 4 01100100001evx evstdd evstddx 31 (0x1f) rs ra rb 01100100000evx evstddx table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic RM0004 instruction set listings 1058/1176 evstdh 31 (0x1f) rs ra uimm 2 01100100101evx evstdh evstdhx 31 (0x1f) rs ra rb 01100100100evx evstdhx evstdw 31 (0x1f) rs ra uimm 2 01100100011evx evstdw evstdwx 31 (0x1f) rs ra rb 01100100010evx evstdwx evstwhe 31 (0x1f) rs ra uimm 4 01100110001evx evstwhe evstwhe x 31 (0x1f) rs ra rb 01100110000evx evstwhe x evstwho 31 (0x1f) rs ra uimm 4 01100110101evx evstwho evstwho x 31 (0x1f) rs ra rb 01100110100evx evstwho x evstwwe 31 (0x1f) rs ra uimm 4 01100111001evx evstwwe evstwwe x 31 (0x1f) rs ra rb 01100111000evx evstwwe x evstwwo 31 (0x1f) rs ra uimm 4 01100111101evx evstwwo evstwwo x 31 (0x1f) rs ra rb 01100111100evx evstwwo x evsubfs miaaw 31 (0x1f) rd ra /// 10011001011evx evsubfs miaaw evsubfss iaaw 31 (0x1f) rd ra /// 10011000011evx evsubfss iaaw evsubfu miaaw 31 (0x1f) rd ra /// 10011001010evx evsubfu miaaw evsubfus iaaw 31 (0x1f) rd ra /// 10011000010evx evsubfu siaaw evsubfw 31 (0x1f) rd ra rb 01000000100evx evsubfw evsubifw 31 (0x1f) rd uimm rb 01000000110evx evsubifw evxor 31 (0x1f) rd ra rb 01000010110evx evxor icblc 31 (0x1f) ct ra rb 00111001100 x icblc icbt 31 (0x1f) ct ra rb 0000010110 / x icbt icbtls 31 (0x1f) ct ra rb 01111001100 x icbtls isel 31 (0x1f) rd ra rb crb 0 1 1 1 1 0 x isel mbar 31 (0x1f) mo /// 1101010110 / x mbar mfdcr 31 (0x1f) rd dcrn5?9 dcrn0?4 0 1 0 1 0 0 0 0 1 1 / xfx mfdcr mfpmr 31 (0x1f) rd pmrn5?9 pmrn0?4 01010011100xfx mfpmr msync 31 (0x1f) /// 1001010110 / x msync mtdcr 31 (0x1f) rs dcrn5?9 dcrn0?4 0 1 1 1 0 0 0 0 1 1 / xfx mtdcr mtpmr 31 (0x1f) rs pmrn5?9 pmrn0?4 01110011100xfx mtpmr tlbivax 31 (0x1f) /// ra rb 1100010010 / x tlbivax tlbre 31 (0x1f) /// 2 1110110010 / x tlbre tlbsx 31 (0x1f) /// 5 ra rb 1110010010 / 5 x tlbsx tlbwe 31 (0x1f) /// 6 1111010010 / x tlbwe wait 31 (0x1f) /// 0 000111110 / wait table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic instruction set listings RM0004 1059/1176 wrtee 31 (0x1f) rs /// 0010000011 / x wrtee wrteei 31 (0x1f) /// e /// 0010100011 / x wrteei cmp 31 (0x1f) crfd /l ra rb 0000000000 / x cmp tw 31 (0x1f) to ra rb 0000000100 / x tw subfc 31 (0x1f) rd ra rb 00000010000 x subfc subfc. 31 (0x1f) rd ra rb 00000010001 x subfc. addc 31 (0x1f) rd ra rb 00000010100 x addc addc. 31 (0x1f) rd ra rb 00000010101 x addc. mulhwu 31 (0x1f) rd ra rb / 0000010110 x mulhwu mulhwu. 31 (0x1f) rd ra rb / 0000010111 x mulhwu. mfcr 31 (0x1f) rd /// 0000010011 / x mfcr lwarx 31 (0x1f) rd ra rb 0 0 0 0 0 1 0 1 0 0 / x lwarx lwzx 31 (0x1f) rd ra rb 0 0 0 0 0 1 0 1 1 1 / x lwzx slw 31 (0x1f) rs ra rb 00000110000 x slw slw. 31 (0x1f) rs ra rb 00000110001 x slw. cntlzw 31 (0x1f) rs ra /// 00000110100 x cntlzw cntlzw. 31 (0x1f) rs ra /// 00000110101 x cntlzw. and 31 (0x1f) rs ra rb 00000111000 x and and. 31 (0x1f) rs ra rb 00000111001 x and. cmpl 31 (0x1f) /l ra rb /// 0000100000 / x cmpl subf 31 (0x1f) rd ra rb 00001010000 x subf subf. 31 (0x1f) rd ra rb 00001010001 x subf. dcbst 31 (0x1f) /// ra rb 0000110110 / x dcbst lwzux 31 (0x1f) rd ra rb 0 0 0 0 1 1 0 1 1 1 / x lwzux andc 31 (0x1f) rs ra rb 00001111000 x andc andc. 31 (0x1f) rs ra rb 00001111001 x andc. mulhw 31 (0x1f) rd ra rb / 0010010110 x mulhw mulhw. 31 (0x1f) rd ra rb / 0010010111 x mulhw. mfmsr 1 31 (0x1f) rd /// 0001010011 / x mfmsr dcbf 31 (0x1f) /// ra rb 0001010110 / x dcbf lbzx 31 (0x1f) rd ra rb 0 0 0 1 0 1 0 1 1 1 / x lbzx neg 31 (0x1f) rd ra /// 00011010000 x neg neg. 31 (0x1f) rd ra /// 00011010001 x neg. lbzux 31 (0x1f) rd ra rb 0 0 0 1 1 1 0 1 1 1 / x lbzux nor 31 (0x1f) rs ra rb 00011111000 x nor nor. 31 (0x1f) rs ra rb 00011111001 x nor. subfe 31 (0x1f) rd ra rb 00100010000 x subfe subfe. 31 (0x1f) rd ra rb 00100010001 x subfe. adde 31 (0x1f) rd ra rb 00100010100 x adde adde. 31 (0x1f) rd ra rb 00100010101 x adde. table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic RM0004 instruction set listings 1060/1176 mtcrf 31 (0x1f) rs / crm / 0010010000 / xfx mtcrf mtmsr 1 31 (0x1f) rs /// 0010010010 / x mtmsr stwcx. 31 (0x1f) rs ra rb 00100101101 x stwcx. stwx 31 (0x1f) rs ra rb 0 0 1 0 0 1 0 1 1 1 / d stwx stwux 31 (0x1f) rs ra rb 0 0 1 0 1 1 0 1 1 1 / d stwux subfze 31 (0x1f) rd ra /// 00110010000 x subfze subfze. 31 (0x1f) rd ra /// 00110010001 x subfze. addze 31 (0x1f) rd ra /// 00110010100 x addze addze. 31 (0x1f) rd ra /// 00110010101 x addze. stbx 31 (0x1f) rs ra rb 00110101110 x stbx subfme 31 (0x1f) rd ra /// 00111010000 x subfme subfme. 31 (0x1f) rd ra /// 00111010001 x subfme. addme 31 (0x1f) rd ra /// 00111010100 x addme addme. 31 (0x1f) rd ra /// 00111010101 x addme. mullw 31 (0x1f) rd ra rb 00111010110 x mullw mullw. 31 (0x1f) rd ra rb 00111010111 x mullw. dcbtst 31 (0x1f) ct ra rb 0011110110 / x dcbtst stbux 31 (0x1f) rs ra rb 00111101110 x stbux add 31 (0x1f) rd ra rb 01000010100 x add add. 31 (0x1f) rd ra rb 01000010101 x add. dcbt 31 (0x1f) ct ra rb 0100010110 / x dcbt lhzx 31 (0x1f) rd ra rb 0 1 0 0 0 1 0 1 1 1 / x lhzx eqv 31 (0x1f) rd ra rb 01000111000 x eqv eqv. 31 (0x1f) rd ra rb 01000111001 x eqv. tlbie 1, 2 31 (0x1f) /// /// rb 01001100100 x tlbie lhzux 31 (0x1f) rd ra rb 0 1 0 0 1 1 0 1 1 1 / x lhzux xor 31 (0x1f) rs ra rb 01001111000 x xor xor. 31 (0x1f) rs ra rb 01001111001 x xor. mfspr 2 31 (0x1f) rd spr[5?9] spr[0?4] 0 1 0 1 0 1 0 0 1 1 / xfx mfspr lhax 31 (0x1f) rd ra rb 0 1 0 1 0 1 0 1 1 1 / x lhax lhaux 31 (0x1f) rd ra rb 0 1 0 1 1 1 0 1 1 1 / x lhaux sthx 31 (0x1f) rs ra rb 0 1 1 0 0 1 0 1 1 1 / x sthx orc 31 (0x1f) rs ra rb 01100111000 x orc orc. 31 (0x1f) rs ra rb 01100111001 x orc. sthux 31 (0x1f) rs ra rb 0 1 1 0 1 1 0 1 1 1 / x sthux or 31 (0x1f) rs ra rb 01101111000 x or or. 31 (0x1f) rs ra rb 01101111001 x or. divwu 31 (0x1f) rd ra rb 01110010110 x divwu divwu. 31 (0x1f) rd ra rb 01110010111 x divwu. table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic instruction set listings RM0004 1061/1176 mtspr 2 31 (0x1f) rs spr[5?9] spr[0?4] 0 1 1 1 0 1 0 0 1 1 / xfx mtspr dcb i 1 31 (0x1f) /// ra rb 0111010110 / x dcbi nand 31 (0x1f) rs ra rb 01110111000 x nand nand. 31 (0x1f) rs ra rb 01110111001 x nand. divw 31 (0x1f) rd ra rb 01111010110 x divw divw. 31 (0x1f) rd ra rb 01111010111 x divw. mcrxr 31 (0x1f) crfd /// 1000000000 / x mcrxr subfco 31 (0x1f) rd ra rb 10000010000 x subfco subfco. 31 (0x1f) rd ra rb 10000010001 x subfco. addco 31 (0x1f) rd ra rb 10000010100 x addco addco. 31 (0x1f) rd ra rb 10000010101 x addco. lwbrx 31 (0x1f) rd ra rb 1 0 0 0 0 1 0 1 1 0 / x lwbrx srw 31 (0x1f) rs ra rb 10000110000 x srw srw. 31 (0x1f) rs ra rb 10000110001 x srw. subfo 31 (0x1f) rd ra rb 10001010000 x subfo subfo. 31 (0x1f) rd ra rb 10001010001 x subfo. tlbsync 1,6 31 (0x1f) /// /// /// 1000110110 / x tlbsync nego mbc 31 (0x1f) rd ra /// 10011010000 x nego nego. 31 (0x1f) rd ra /// 10011010001 x nego. subfeo 31 (0x1f) rd ra rb 10100010000 x subfeo subfeo. 31 (0x1f) rd ra rb 10100010001 x subfeo. addeo 31 (0x1f) rd ra rb 10100010100 x addeo addeo. 31 (0x1f) rd ra rb 10100010101 x addeo. stwbrx 31 (0x1f) rs ra rb 1 0 1 0 0 1 0 1 1 0 / x stwbrx subfzeo 31 (0x1f) rd ra /// 10110010000 x subfzeo subfzeo. 31 (0x1f) rd ra /// 10110010001 x subfzeo. addzeo 31 (0x1f) rd ra /// 10110010100 x addzeo addzeo. 31 (0x1f) rd ra /// 10110010101 x addzeo. subfmeo 31 (0x1f) rd ra /// 10111010000 x subfmeo subfmeo. 31 (0x1f) rd ra /// 10111010001 x subfmeo . addmeo 31 (0x1f) rd ra /// 10111010100 x addmeo addmeo. 31 (0x1f) rd ra /// 10111010101 x addmeo. mullwo 31 (0x1f) rd ra rb 10111010110 x mullwo mullwo. 31 (0x1f) rd ra rb 10111010111 x mullwo. dcba 6 31 (0x1f) /// ra rb 1011110110 / x dcba addo 31 (0x1f) rd ra rb 11000010100 x addo addo. 31 (0x1f) rd ra rb 11000010101 x addo. lhbrx 31 (0x1f) rd ra rb 1 1 0 0 0 1 0 1 1 0 / x lhbrx table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic RM0004 instruction set listings 1062/1176 sraw 31 (0x1f) rs ra rb 11000110000 x sraw sraw. 31 (0x1f) rs ra rb 11000110001 x sraw. srawi 31 (0x1f) rs ra sh 11001110000 x srawi srawi. 31 (0x1f) rs ra sh 11001110001 x srawi. sthbrx 31 (0x1f) rs ra rb 1 1 1 0 0 1 0 1 1 0 / x sthbrx extsh 31 (0x1f) rs ra /// 11100110100 x extsh extsh. 31 (0x1f) rs ra /// 11100110101 x extsh. extsb 31 (0x1f) rs ra /// 11101110100 x extsb extsb. 31 (0x1f) rs ra /// 11101110101 x extsb. divwuo 31 (0x1f) rd ra rb 11110010110 x divwuo divwuo. 31 (0x1f) rd ra rb 11110010111 x divwuo. icbi 31 (0x1f) /// ra rb 1111010110 / x icbi divwo 31 (0x1f) rd ra rb 11111010110 x divwo divwo. 31 (0x1f) rd ra rb 11111010111 x divwo. dcbz 31 (0x1f) /// ra rb 1111110110 / x dcbz lwz 32 (0x20) rd ra d d lwz lwzu 33 (0x21) rd ra d d lwzu lbz 34(0x22) rd ra d d lbz lbzu 35(0x23) rd ra d d lbzu stw 36(0x24) rs ra d d stw stwu 37(0x25) rs ra d d stwu stb 38(0x26) rs ra d d stb stbu 39(0x27) rs ra d d stbu lhz 40(0x28) rd ra d d lhz lhzu 41(0x29) rd ra d d lhzu lha 42(0x2a) rd ra d d lha lhau 43(0x2b) rd ra d d lhau sth 44(0x2c) rs ra d d sth sthu 45(0x2d) rs ra d d sthu lmw 46(0x2e) rd ra d d lmw stmw 47(0x2f) rs ra d d stmw fres 6 59(0x3b) frd /// frb /// 1 1 0 0 0 0 a fres fres. 6 59(0x3b) frd /// frb /// 1 1 0 0 0 1 a fres. fsel 6 63(0x3f) frd fra frb frc 1 0 1 1 1 0 a fsel fsel. 6 63(0x3f) frd fra frb frc 1 0 1 1 1 1 a fsel. 1. supervisor-level instruction table 270. instructions sorted by primary opcodes (decimal and hexadecimal) (continued) mnemonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 form mnemonic instruction set listings RM0004 1063/1176 a.3 instructions sorted by mnemonic (binary) table 271 lists instructions in alphabetical order by mnemonic with binary values. this list also includes simplified mnemonics and their equivalents using standard mnemonics. table 271. instructions sorted by mnemonic (binary) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic add 011111 rd ra rb 0100001010 0 x add add. 011111 rd ra rb 0100001010 1 x add. addc 011111 rd ra rb 0000001010 0 x addc addc. 011111 rd ra rb 0000001010 1 x addc. addco 011111 rd ra rb 1000001010 0 x addco addco. 011111 rd ra rb 1000001010 1 x addco. adde 011111 rd ra rb 0010001010 0 x adde adde. 011111 rd ra rb 0010001010 1 x adde. addeo 011111 rd ra rb 1010001010 0 x addeo addeo. 011111 rd ra rb 1010001010 1 x addeo. addi 001110 rd ra simm d addi addic 001100 rd ra simm d addic addic. 001101 rd ra simm d addic. addis 001111 rd ra simm d addis addme 011111 rd ra /// 0011101010 0 x addme addme. 011111 rd ra /// 0011101010 1 x addme. addmeo 011111 rd ra /// 1011101010 0 x addmeo addmeo. 011111 rd ra /// 1011101010 1 x addmeo. addo 011111 rd ra rb 1100001010 0 x addo addo. 011111 rd ra rb 1100001010 1 x addo. addze 011111 rd ra /// 0011001010 0 x addze addze. 011111 rd ra /// 0011001010 1 x addze. addzeo 011111 rd ra /// 1011001010 0 x addzeo addzeo. 011111 rd ra /// 1011001010 1 x addzeo. and 011111 rs ra rb 0000011100 0 x and and. 011111 rs ra rb 0000011100 1 x and. andc 011111 rs ra rb 0000111100 0 x andc andc. 011111 rs ra rb 0000111100 1 x andc. andi. 011100 rs ra uimm d andi. andis. 011101 rs ra uimm d andis. b 010010 li 0 0 i b ba 010010 li 1 0 i ba bc 010000 bo bi bd 0 0 b bc bca 010000 bo bi bd 1 0 b bca bcctr 010011 bo bi /// 1000010000 0 xl bcctr bcctrl 010011 bo bi /// 1000010000 1 xl bcctrl RM0004 instruction set listings 1064/1176 bcl 010000 bo bi bd 0 1 b bcl bcla 010000 bo bi bd 1 1 b bcla bclr 010011 bo bi /// 0000010000 0 xl bclr bclrl 010011 bo bi /// 0000010000 1 xl bclrl bctr bctr (1) equivalent to bcctr 20,0 bctr bctrl bctrl 1 equivalent to bcctrl 20,0 bctrl bdnz bdnz target 1 equivalent to bc 16,0, target bdnz bdnza bdnza target 1 equivalent to bca 16,0, target bdnza bdnzf bdnzf bi, target equivalent to bc 0,bi, target bdnzf bdnzfa bdnzfa bi, target equivalent to bca 0,bi, target bdnzfa bdnzfl bdnzfl bi, target equivalent to bcl 0,bi, target bdnzfl bdnzfla bdnzfla bi, target equivalent to bcla 0,bi, target bdnzfla bdnzflr bdnzflr bi equivalent to bclr 0,bi bdnzflr bdnzflrl bdnzflrl bi equivalent to bclrl 0,bi bdnzflrl bdnzl bdnzl target 1 equivalent to bcl 16,0, target bdnzl bdnzla bdnzla target 1 equivalent to bcla 16,0, target bdnzla bdnzlr bdnzlr bi equivalent to bclr 16,bi bdnzlr bdnzlrl bdnzlrl 1 equivalent to bclrl 16,0 bdnzlrl bdnzt bdnzt bi, target equivalent to bc 8,bi, target bdnzt bdnzta bdnzta bi, target equivalent to bca 8,bi, target bdnzta bdnztl bdnztl bi, target equivalent to bcl 8,0, target bdnztl bdnztla bdnztla bi, target equivalent to bcla 8,bi, target bdnztla bdnztlr bdnztlr bi equivalent to bclr 8,bi bdnztlr bdnztlr bdnztlr bi equivalent to bclr 8,bi bdnztlr bdnztlrl bdnztlrl bi equivalent to bclrl 8,bi bdnztlrl bdz bdz target 1 equivalent to bc 18,0, target bdz bdza bdza target 1 equivalent to bca 18,0, target bdza bdzf bdzf bi, target equivalent to bc 2,bi, target bdzf bdzfa bdzfa bi, target equivalent to bca 2,bi, target bdzfa bdzfl bdzfl bi, target equivalent to bcl 2,bi, target bdzfl bdzfla bdzfla bi, target equivalent to bcla 2,bi, target bdzfla bdzflr bdzflr bi equivalent to bclr 2,bi bdzflr bdzflrl bdzflrl bi equivalent to bclrl 2,bi bdzflrl bdzl bdzl target 1 equivalent to bcl 18,bi, target bdzl bdzla bdzla target 1 equivalent to bcla 18,bi, target bdzla bdzlr bdzlr 1 equivalent to bclr 18,0 bdzlr bdzlrl bdzlrl 1 equivalent to bclrl 18,0 bdzlrl bdzt bdzt bi, target equivalent to bc 10,bi, target bdzt bdzta bdzta bi, target equivalent to bca 10,bi, target bdzta bdztl bdztl bi, target equivalent to bcl 10,bi, target bdztl table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1065/1176 bdztla bdztla bi, target equivalent to bcla 10,bi, target bdztla bdztlrl bdztlrl bi equivalent to bclrl 10, bi bdztlrl beq beq cr s , target equivalent to bc 12, bi (2) , target beq beqa beqa cr s , target equivalent to bca 12, bi 2 , target beqa beqctr beqctr cr s , target equivalent to bcctr 12, bi 2 , target beqctr beqctrl beqctrl cr s , targetequivalent to bcctrl 12, bi 2 , target beqctrl beql beql cr s , target equivalent to bcl 12, bi 2 , target beql beqla beqla cr s , target equivalent to bcla 12, bi 2 , target beqla beqlr beqlr cr s , target equivalent to bclr 12, bi 2 , target beqlr beqlrl beqlrl cr s , target equivalent to bclrl 12, bi 2 , target beqlrl bf bf bi, target equivalent to bc 4,bi, target bf bfa bfa bi, target equivalent to bca 4,bi, target bfa bfctr bfctr bi equivalent to bcctr 4,bi bfctr bfctrl bfctrl bi equivalent to bcctrl 4,bi bfctrl bfl bfl bi, target equivalent to bcl 4,bi, target bfl bfla bfla bi, target equivalent to bcla 4,bi, target bfla bflr bflr bi equivalent to bclr 4,bi bflr bflrl bflrl bi equivalent to bclrl 4,bi bflrl bge bge cr s , target equivalent to bc 4, bi (3) , target bge bgea bgea cr s , target equivalent to bca 4, bi 3 , target bgea bgectr bgectr cr s , target equivalent to bcctr 4, bi 3 , target bgectr bgectrl bgectrl cr s , targetequivalent to bcctrl 4, bi 3 , target bgectrl bgel bgel cr s , target equivalent to bcl 4, bi 3 , target bgel bgela bgela cr s , target equivalent to bcla 4, bi 3 , target bgela bgelr bgelr cr s , target equivalent to bclr 4, bi 3 , target bgelr bgelrl bgelrl cr s , target equivalent to bclrl 4, bi 3 , target bgelrl bgt bgt cr s , target equivalent to bc 12, bi (4) , target bgt bgta bgta cr s , target equivalent to bca 12, bi 4 , target bgta bgtctr bgtctr cr s , target equivalent to bcctr 12, bi 4 , target bgtctr bgtctrl bgtctrl cr s , target equivalent to bcctrl 12, bi 4 , target bgtctrl bgtl bgtl cr s , target equivalent to bcl 12, bi 4 , target bgtl bgtla bgtla cr s , target equivalent to bcla 12, bi 4 , target bgtla bgtlr bgtlr cr s , target equivalent to bclr 12, bi 4 , target bgtlr bgtlrl bgtlrl cr s , target equivalent to bclrl 12, bi 4 , target bgtlrl bl 010010 li 0 1 i bl bla 010010 li 1 1 i bla ble ble cr s , target equivalent to bc 4, bi 4 , target ble blea blea cr s , target equivalent to bca 4, bi 4 , target blea blectr blectr cr s , target equivalent to bcctr 4, bi 4 , target blectr blectrl blectrl cr s , target equivalent to bcctrl 4, bi 4 , target blectrl table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1066/1176 blel blel cr s , target equivalent to bcl 4, bi 4 , target blel blela blela cr s , target equivalent to bcla 4, bi 4 , target blela blelr blelr cr s , target equivalent to bclr 4, bi 4 , target blelr blelrl blelrl cr s , target equivalent to bclrl 4, bi 4 , target blelrl blr blr 1 equivalent to bclr 20,0 blr blrl blrl 1 equivalent to bclrl 20,0 blrl blt blt cr s , target equivalent to bc 12, bi , target blt blta blta cr s , target equivalent to bca 12, bi 3 , target blta bltctr bltctr cr s , target equivalent to bcctr 12, bi 3 , target bltctr bltctrl bltctrl cr s , target equivalent to bcctrl 12, bi 3 , target bltctrl bltl bltl cr s , target equivalent to bcl 12, bi 3 , target bltl bltla bltla cr s , target equivalent to bcla 12, bi 3 , target bltla bltlr bltlr cr s , target equivalent to bclr 12, bi 3 , target bltlr bltlrl bltlrl cr s , target equivalent to bclrl 12, bi 3 , target bltlrl bne bne cr s , target equivalent to bc 4, bi 3 , target bne bnea bnea cr s , target equivalent to bca 4, bi 3 , target bnea bnectr bnectr cr s , target equivalent to bcctr 4, bi 3 , target bnectr bnectrl bnectrl cr s , targetequivalent to bcctrl 4, bi 3 , target bnectrl bnel bnel cr s , target equivalent to bcl 4, bi 3 , target bnel bnela bnela cr s , target equivalent to bcla 4, bi 3 , target bnela bnelr bnelr cr s , target equivalent to bclr 4, bi 3 , target bnelr bnelrl bnelrl cr s , target equivalent to bclrl 4, bi 3 , target bnelrl bng bng cr s , target equivalent to bc 4, bi 4 , target bng bnga bnga cr s , target equivalent to bca 4, bi 4 , target bnga bngctr bngctr cr s , target equivalent to bcctr 4, bi 4 , target bngctr bngctrl bngctrl cr s , targetequivalent to bcctrl 4, bi 4 , target bngctrl bngl bngl cr s , target equivalent to bcl 4, bi 4 , target bngl bngla bngla cr s , target equivalent to bcla 4, bi 4 , target bngla bnglr bnglr cr s , target equivalent to bclr 4, bi 4 , target bnglr bnglrl bnglrl cr s , target equivalent to bclrl 4, bi 4 , target bnglrl bnl bnl cr s , target equivalent to bc 4, bi 3 , target bnl bnla bnla cr s , target equivalent to bca 4, bi 3 , target bnla bnlctr bnlctr cr s , target equivalent to bcctr 4, bi 3 , target bnlctr bnlctrl bnlctrl cr s , target equivalent to bcctrl 4, bi 3 , target bnlctrl bnll bnll cr s , target equivalent to bcl 4, bi 3 , target bnll bnlla bnlla cr s , target equivalent to bcla 4, bi 3 , target bnlla bnllr bnllr cr s , target equivalent to bclr 4, bi 3 , target bnllr bnllrl bnllrl cr s , target equivalent to bclrl 4, bi 3 , target bnllrl bns bns cr s , target equivalent to bc 4, bi (5) , target bns bnsa bnsa cr s , target equivalent to bca 4, bi 5 , target bnsa table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1067/1176 bnsctr bnsctr cr s , target equivalent to bcctr 4, bi 5 , target bnsctr bnsctrl bnsctrl cr s , targetequivalent to bcctrl 4, bi 5 , target bnsctrl bnsl bnsl cr s , target equivalent to bcl 4, bi 5 , target bnsl bnsla bnsla cr s , target equivalent to bcla 4, bi 5 , target bnsla bnslr bnslr cr s , target equivalent to bclr 4, bi 5 , target bnslr bnslrl bnslrl cr s , target equivalent to bclrl 4, bi 5 , target bnslrl bnu bnu cr s , target equivalent to bc 4, bi 5 , target bnu bnua bnua cr s , target equivalent to bca 4, bi 5 , target bnua bnuctr bnuctr cr s , target equivalent to bcctr 4, bi 5 , target bnuctr bnuctrl bnuctrl cr s , targetequivalent to bcctrl 4, bi 5 , target bnuctrl bnul bnul cr s , target equivalent to bcl 4, bi 5 , target bnul bnula bnula cr s , target equivalent to bcla 4, bi 5 , target bnula bnulr bnulr cr s , target equivalent to bclr 4, bi 5 , target bnulr bnulrl bnulrl cr s , target equivalent to bclrl 4, bi 5 , target bnulrl brinc 000100 rd ra rb 0100000111 1 evx brinc bso bso cr s , target equivalent to bc 12, bi 5 , target bso bsoa bsoa cr s , target equivalent to bca 12, bi 5 , target bsoa bsoctr bsoctr cr s , target equivalent to bcctr 12, bi 5 , target bsoctr bsoctrl bsoctrl cr s , targetequivalent to bcctrl 12, bi 5 , target bsoctrl bsol bsol cr s , target equivalent to bcl 12, bi 5 , target bsol bsola bsola cr s , target equivalent to bcla 12, bi 5 , target bsola bsolr bsolr cr s , target equivalent to bclr 12, bi 5 , target bsolr bsolrl bsolrl cr s , target equivalent to bclrl 12, bi 5 , target bsolrl bt bt bi, target equivalent to bc 12,bi, target bt bta bta bi, target equivalent to bca 12,bi, target bta btctr btctr bi equivalent to bcctr 12,bi btctr btctrl btctrl bi equivalent to bcctrl 12,bi btctrl btl btl bi, target equivalent to bcl 12,bi, target btl btla btla bi, target equivalent to bcla 12,bi, target btla btlr btlr bi equivalent to bclr 12,bi btlr btlrl btlrl bi equivalent to bclrl 12,bi btlrl bun bun cr s , target equivalent to bc 12, bi 5 , target bun buna buna cr s , target equivalent to bca 12, bi 5 , target buna bunctr bunctr cr s , target equivalent to bcctr 12, bi 5 , target bunctr bunctrl bunctrl cr s , targetequivalent to bcctrl 12, bi 5 , target bunctrl bunl bunl cr s , target equivalent to bcl 12, bi 5 , target bunl bunla bunla cr s , target equivalent to bcla 12, bi 5 , target bunla bunlr bunlr cr s , target equivalent to bclr 12, bi 5 , target bunlr bunlrl bunlrl cr s , target equivalent to bclrl 12, bi 5 , target bunlrl clrlslwi clrlslwi r a ,r s , b , n ( n b 31) equivalent to rlwinm r a ,r s , n , b ? n , 31 ? n clrlslwi table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1068/1176 clrlwi clrlwi r a ,r s , n (n < 32) equivalent to rlwinm r a ,r s ,0, n ,31 clrlwi clrrwi clrrwi r a ,r s , n (n < 32) equivalent to rlwinm r a ,r s ,0,0,31 ? n clrrwi cmp 011111 crfd / l ra rb 0000000000 / x cmp cmpi 001011 crfd / l ra simm d cmpi cmpl 011111 / l ra rb /// 0000100000 / x cmpl cmpli 001010 crfd / l ra uimm d cmpli cmplw cmplw cr d ,r a ,r b equivalent to cmpl cr d ,0,r a ,r b cmplw cmplwi cmplwi cr d ,r a ,uimm equivalent to cmpli cr d ,0,r a , uimm cmplwi cmpw cmpw cr d ,r a ,r b equivalent to cmp cr d ,0,r a ,r b cmpw cmpwi cmpwi cr d ,r a ,simm equivalent to cmpi cr d ,0,r a , simm cmpwi cntlzw 011111 rs ra /// 0000011010 0 x cntlzw cntlzw. 011111 rs ra /// 0000011010 1 x cntlzw. crand 010011 crbd crba crbb 0100000001 / xl crand crandc 010011 crbd crba crbb 0010000001 / xl crandc crclr crclr bx equivalent to crxor bx , bx , bx crclr creqv 010011 crbd crba crbb 0100100001 / xl creqv crmove crmove bx,by equivalent to cror bx , by , by crmove crnand 010011 crbd crba crbb 0011100001 / xl crnand crnor 010011 crbd crba crbb 0000100001 / xl crnor crnot crnot bx,by equivalent to crnor bx , by , by crnot cror 010011 crbd crba crbb 0111000001 / xl cror crorc 010011 crbd crba crbb 0110100001 / xl crorc crset crset bx equivalent to creqv bx , bx , bx crset crxor 010011 crbd crba crbb 0011000001 / xl crxor dcba (6) 011111 /// ra rb 1011110110 / x dcba dcbf 011111 /// ra rb 0001010110 / x dcbf dcbi (7) 011111 /// ra rb 0111010110 / x dcbi dcblc 011111 ct ra rb 0110000110 0 x dcblc dcbst 011111 /// ra rb 0000110110 / x dcbst dcbt 011111 ct ra rb 0100010110 / x dcbt dcbtls 011111 ct ra rb 0010100110 0 x dcbtls dcbtst 011111 ct ra rb 0011110110 / x dcbtst dcbtstls 011111 ct ra rb 0010000110 0 x dcbtstls dcbz 011111 /// ra rb 1111110110 / x dcbz divw 011111 rd ra rb 0111101011 0 x divw divw. 011111 rd ra rb 0111101011 1 x divw. divwo 011111 rd ra rb 1111101011 0 x divwo divwo. 011111 rd ra rb 1111101011 1 x divwo. divwu 011111 rd ra rb 0111001011 0 x divwu divwu. 011111 rd ra rb 0111001011 1 x divwu. table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1069/1176 divwuo 011111 rd ra rb 1111001011 0 x divwuo divwuo. 011111 rd ra rb 1111001011 1 x divwuo. dss dss strm equivalent to dss strm ,0 dss efdabs 000100 rd ra /// 0101110010 0 efx efdabs efdadd 000100 rd ra rb 0101110000 0 efx efdadd efdcfs 000100 rd 00000 rb 0 101110111 1 efx efdcfs efdcfsf 000100 rd /// rb 0101111001 1 efx efdcfsf efdcfsi 000100 rd /// rb 0101111000 1 efx efdcfsi efdcfuf 000100 rd /// rb 0101111001 0 efx efdcfuf efdcfui 000100 rd /// rb 0101111000 0 efx efdcfui efdcmpeq 000100 crfd / / ra rb 0101110111 0 efx efdcmpeq efdcmpgt 000100 crfd / / ra rb 0101110110 0 efx efdcmpgt efdcmplt 000100 crfd / / ra rb 0101110110 1 efx efdcmplt efdctsf 000100 rd /// rb 0101111011 1 efx efdctsf efdctsi 000100 rd /// rb 0101111010 1 efx efdctsi efdctsiz 000100 rd /// rb 0101111101 0 efx efdctsiz efdctuf 000100 rd /// rb 0101111011 0 efx efdctuf efdctui 000100 rd /// rb 0101111010 0 efx efdctui efdctuiz 000100 rd /// rb 0101111100 0 efx efdctuiz efddiv 000100 rd ra rb 0101110100 1 efx efddiv efdmul 000100 rd ra rb 0101110100 0 efx efdmul efdnabs 000100 rd ra /// 0101110010 1 efx efdnabs efdneg 000100 rd ra /// 0101110011 0 efx efdneg efdsub 000100 rd ra rb 0101110000 1 efx efdsub efdtsteq 000100 crfd / / ra rb 0101111111 0 efx efdtsteq efdtstgt 000100 crfd / / ra rb 0101111110 0 efx efdtstgt efdtstlt 000100 crfd / / ra rb 0101111110 1 efx efdtstlt efsabs 000100 rd ra /// 0101100010 0 efx efsabs efsadd 000100 rd ra rb 0101100000 0 efx efsadd efscfd 000100 rd 00000 rb 0 101100111 1 efx efscfd efscfsf 000100 rd /// rb 0101101001 1 efx efscfsf efscfsi 000100 rd /// rb 0101101000 1 efx efscfsi efscfuf 000100 rd /// rb 0101101001 0 efx efscfuf efscfui 000100 rd /// rb 0101101000 0 efx efscfui efscmpeq 000100 crfd / / ra rb 0101100111 0 efx efscmpeq efscmpgt 000100 crfd / / ra rb 0101100110 0 efx efscmpgt efscmplt 000100 crfd / / ra rb 0101100110 1 efx efscmplt efsctsf 000100 rd /// rb 0101101011 1 efx efsctsf efsctsi 000100 rd /// rb 0101101010 1 efx efsctsi efsctsiz 000100 rd /// rb 0101101101 0 efx efsctsiz table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1070/1176 efsctuf 000100 rd /// rb 0101101011 0 efx efsctuf efsctui 000100 rd /// rb 0101101010 0 efx efsctui efsctuiz 000100 rd /// rb 0101101100 0 efx efsctuiz efsdiv 000100 rd ra rb 0101100100 1 efx efsdiv efsmul 000100 rd ra rb 0101100100 0 efx efsmul efsnabs 000100 rd ra /// 0101100010 1 efx efsnabs efsneg 000100 rd ra /// 0101100011 0 efx efsneg efssub 000100 rd ra rb 0101100000 1 efx efssub efststeq 000100 crfd / / ra rb 0101101111 0 efx efststeq efststgt 000100 crfd / / ra rb 0101101110 0 efx efststgt efststlt 000100 crfd / / ra rb 0101101110 1 efx efststlt eqv 011111 rd ra rb 0100011100 0 x eqv eqv. 011111 rd ra rb 0100011100 1 x eqv. evabs 011111 rd ra /// 0100000100 0 evx evabs evaddiw 011111 rd uimm rb 0100000001 0 evx evaddiw evaddsmi aaw 011111 rd ra /// 1001100100 1 evx evaddsmi aaw evaddssi aaw 011111 rd ra /// 1001100000 1 evx evaddssia aw evaddumi aaw 011111 rd ra /// 1001100100 0 evx evaddumi aaw evaddusi aaw 011111 rd ra /// 1001100000 0 evx evaddusia aw evaddw 011111 rd ra rb 0100000000 0 evx evaddw evand 011111 rd ra rb 0100001000 1 evx evand evandc 011111 rd ra rb 0100001001 0 evx evandc evcmpeq 011111 crfd / / ra rb 0100011010 0 evx evcmpeq evcmpgts 011111 crfd / / ra rb 0100011000 1 evx evcmpgts evcmpgtu 011111 crfd / / ra rb 0100011000 0 evx evcmpgtu evcmplts 011111 crfd / / ra rb 0100011001 1 evx evcmplts evcmpltu 011111 crfd / / ra rb 0100011001 0 evx evcmpltu evcntlsw 011111 rd ra /// 0100000111 0 evx evcntlsw evcntlzw 011111 rd ra /// 0100000110 1 evx evcntlzw evdivws 011111 rd ra rb 1001100011 0 evx evdivws evdivwu 011111 rd ra rb 1001100011 1 evx evdivwu eveqv 011111 rd ra rb 0100001100 1 evx eveqv evextsb 011111 rd ra /// 0100000101 0 evx evextsb evextsh 011111 rd ra /// 0100000101 1 evx evextsh evfsabs 011111 rd ra /// 0101000010 0 evx evfsabs evfsadd 011111 rd ra rb 0101000000 0 evx evfsadd evfscfsf 011111 rd /// rb 0101001001 1 evx evfscfsf evfscfsi 011111 rd /// rb 0101001000 1 evx evfscfsi table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1071/1176 evfscfuf 011111 rd /// rb 0101001001 0 evx evfscfuf evfscfui 011111 rd /// rb 0101001000 0 evx evfscfui evfscmpeq 011111 crfd / / ra rb 0101000111 0 evx evfscmpe q evfscmpg t 011111 crfd / / ra rb 0101000110 0 evx evfscmpg t evfscmplt 011111 crfd / / ra rb 0101000110 1 evx evfscmplt evfsctsf 011111 rd /// rb 0101001011 1 evx evfsctsf evfsctsi 011111 rd /// rb 0101001010 1 evx evfsctsi evfsctsiz 011111 rd /// rb 0101001101 0 evx evfsctsiz evfsctuf 011111 rd /// rb 0101001011 0 evx evfsctuf evfsctui 011111 rd /// rb 0101001010 0 evx evfsctui evfsctuiz 011111 rd /// rb 0101001100 0 evx evfsctuiz evfsdiv 011111 rd ra rb 0101000100 1 evx evfsdiv evfsmul 011111 rd ra rb 0101000100 0 evx evfsmul evfsnabs 011111 rd ra /// 0101000010 1 evx evfsnabs evfsneg 011111 rd ra /// 0101000011 0 evx evfsneg evfssub 011111 rd ra rb 0101000000 1 evx evfssub evfststeq 011111 crfd / / ra rb 0101001111 0 evx evfststeq evfststgt 011111 crfd / / ra rb 0101001110 0 evx evfststgt evfststlt 011111 crfd / / ra rb 0101001110 1 evx evfststlt evldd 011111 rd ra uimm (8) 0110000000 1 evx evldd evlddx 011111 rd ra rb 0110000000 0 evx evlddx evldh 011111 rd ra uimm 8 0110000010 1 evx evldh evldhx 011111 rd ra rb 0110000010 0 evx evldhx evldw 011111 rd ra uimm 8 0110000001 1 evx evldw evldwx 011111 rd ra rb 0110000001 0 evx evldwx evlhhespl at 011111 rd ra uimm 9 0110000100 1 evx evlhhespl at evlhhespl atx 011111 rd ra rb 0110000100 0 evx evlhhespl atx evlhhoss plat 011111 rd ra uimm 9 0110000111 1 evx evlhhoss plat evlhhoss platx 011111 rd ra rb 0110000111 0 evx evlhhoss platx evlhhous plat 011111 rd ra uimm 9 0110000110 1 evx evlhhous plat evlhhous platx 011111 rd ra rb 0110000110 0 evx evlhhous platx evlwhe 011111 rd ra uimm 9 0110001000 1 evx evlwhe evlwhex 011111 rd ra rb 0110001000 0 evx evlwhex evlwhos 011111 rd ra uimm 10 0110001011 1 evx evlwhos evlwhosx 011111 rd ra rb 0110001011 0 evx evlwhosx table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1072/1176 evlwhou 011111 rd ra uimm 10 0110001010 1 evx evlwhou evlwhoux 011111 rd ra rb 0110001010 0 evx evlwhoux evlwhspl at 011111 rd ra uimm 10 0110001110 1 evx evlwhspla t evlwhspl atx 011111 rd ra rb 0110001110 0 evx evlwhspla tx evlwwspl at 011111 rd ra uimm 10 0110001100 1 evx evlwwspl at evlwwspl atx 011111 rd ra rb 0110001100 0 evx evlwwspl atx evmerge hi 011111 rd ra rb 0100010110 0 evx evmergeh i evmerge hilo 011111 rd ra rb 0100010111 0 evx evmergeh ilo evmergel o 011111 rd ra rb 0100010110 1 evx evmergel o evmergel ohi 011111 rd ra rb 0100010111 1 evx evmergel ohi evmhegs mfaa 011111 rd ra rb 1010010101 1 evx evmhegs mfaa evmhegs mfan 011111 rd ra rb 1011010101 1 evx evmhegs mfan evmhegs miaa 011111 rd ra rb 1010010100 1 evx evmhegs miaa evmhegs mian 011111 rd ra rb 1011010100 1 evx evmhegs mian evmhegu miaa 011111 rd ra rb 1010010100 0 evx evmhegu miaa evmhegu mian 011111 rd ra rb 1011010100 0 evx evmhegu mian evmhesm f 011111 rd ra rb 1000000101 1 evx evmhesm f evmhesm fa 011111 rd ra rb 1000010101 1 evx evmhesm fa evmhesm faaw 011111 rd ra rb 1010000101 1 evx evmhesm faaw evmhesm fanw 011111 rd ra rb 1011000101 1 evx evmhesm fanw evmhesm i 011111 rd ra rb 1000000100 1 evx evmhesm i evmhesm ia 011111 rd ra rb 1000010100 1 evx evmhesm ia evmhesm iaaw 011111 rd ra rb 1010000100 1 evx evmhesm iaaw evmhesm ianw 011111 rd ra rb 1011000100 1 evx evmhesm ianw evmhessf 011111 rd ra rb 1000000001 1 evx evmhessf evmhessf a 011111 rd ra rb 1000010001 1 evx evmhessf a evmhessf aaw 011111 rd ra rb 1010000001 1 evx evmhessf aaw table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1073/1176 evmhessf anw 011111 rd ra rb 1011000001 1 evx evmhessf anw evmhessi aaw 011111 rd ra rb 1010000000 1 evx evmhessi aaw evmhessi anw 011111 rd ra rb 1011000000 1 evx evmhessi anw evmheum i 011111 rd ra rb 1000000100 0 evx evmheum i evmheum ia 011111 rd ra rb 1000010100 0 evx evmheum ia evmheum iaaw 011111 rd ra rb 1010000100 0 evx evmheum iaaw evmheum ianw 011111 rd ra rb 1011000100 0 evx evmheum ianw evmheusi aaw 011111 rd ra rb 1010000000 0 evx evmheusi aaw evmheusi anw 011111 rd ra rb 1011000000 0 evx evmheusi anw evmhogs mfaa 011111 rd ra rb 1010010111 1 evx evmhogs mfaa evmhogs mfan 011111 rd ra rb 1011010111 1 evx evmhogs mfan evmhogs miaa 011111 rd ra rb 1010010110 1 evx evmhogs miaa evmhogs mian 011111 rd ra rb 1011010110 1 evx evmhogs mian evmhogu miaa 011111 rd ra rb 1010010110 0 evx evmhogu miaa evmhogu mian 011111 rd ra rb 1011010110 0 evx evmhogu mian evmhosm f 011111 rd ra rb 1000000111 1 evx evmhosm f evmhosm fa 011111 rd ra rb 1000010111 1 evx evmhosm fa evmhosm faaw 011111 rd ra rb 1010000111 1 evx evmhosm faaw evmhosm fanw 011111 rd ra rb 1011000111 1 evx evmhosm fanw evmhosm i 011111 rd ra rb 1000000110 1 evx evmhosm i evmhosm ia 011111 rd ra rb 1000010110 1 evx evmhosm ia evmhosm iaaw 011111 rd ra rb 1010000110 1 evx evmhosm iaaw evmhosm ianw 011111 rd ra rb 1011000110 1 evx evmhosm ianw evmhossf 011111 rd ra rb 1000000011 1 evx evmhossf evmhossf a 011111 rd ra rb 1000010011 1 evx evmhossf a evmhossf aaw 011111 rd ra rb 1010000011 1 evx evmhossf aaw table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1074/1176 evmhossf anw 011111 rd ra rb 1011000011 1 evx evmhossf anw evmhossi aaw 011111 rd ra rb 1010000010 1 evx evmhossi aaw evmhossi anw 011111 rd ra rb 1011000010 1 evx evmhossi anw evmhou mi 011111 rd ra rb 1000000110 0 evx evmhoum i evmhou mia 011111 rd ra rb 1000010110 0 evx evmhoum ia evmhou miaaw 011111 rd ra rb 1010000110 0 evx evmhoum iaaw evmhou mianw 011111 rd ra rb 1011000110 0 evx evmhoum ianw evmhousi aaw 011111 rd ra rb 1010000010 0 evx evmhousi aaw evmhousi anw 011111 rd ra rb 1011000010 0 evx evmhousi anw evmr evmr r d ,r a equivalent to evor r d ,r a ,r a evmr evmra 011111 rd ra /// 1001100010 0 evx evmra evmwhgs mfaa 011111 rd ra rb 1010110111 1 evx evmwhgs mfaa evmwhgs mfan 011111 rd ra rb 1011101111 1 evx evmwhgs mfan evmwhgs miaa 011111 rd ra rb 1010110110 1 evx evmwhgs miaa evmwhgs mian 011111 rd ra rb 1011101110 1 evx evmwhgs mian evmwhgs sfaa 011111 rd ra rb 1010110011 1 evx evmwhgs sfaa evmwhgs sfan 011111 rd ra rb 1011101011 1 evx evmwhgs sfan evmwhgu miaa 011111 rd ra rb 1010110110 0 evx evmwhgu miaa evmwhgu mian 011111 rd ra rb 1011101110 0 evx evmwhgu mian evmwhs mf 011111 rd ra rb 1000100111 1 evx evmwhsm f evmwhs mfa 011111 rd ra rb 1000110111 1 evx evmwhsm fa evmwhs mfaaw 011111 rd ra rb 1010100111 1 evx evmwhsm faaw evmwhs mfanw 011111 rd ra rb 1011100111 1 evx evmwhsm fanw evmwhs mi 011111 rd ra rb 1000100110 1 evx evmwhsm i evmwhs mia 011111 rd ra rb 1000110110 1 evx evmwhsm ia evmwhs miaaw 011111 rd ra rb 1010100110 1 evx evmwhsm iaaw evmwhs mianw 011111 rd ra rb 1011100110 1 evx evmwhsm ianw table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1075/1176 evmwhss f 011111 rd ra rb 1000100011 1 evx evmwhssf evmwhss fa 011111 rd ra rb 1000110011 1 evx evmwhssf a evmwhss faaw 011111 rd ra rb 1010100011 1 evx evmwhssf aaw evmwhss fanw 011111 rd ra rb 1011100011 1 evx evmwhssf anw evmwhss ianw 011111 rd ra rb 1011100010 1 evx evmwhssi anw evmwhss maaw 011111 rd ra rb 1010100010 1 evx evmwhss maaw evmwhu mi 011111 rd ra rb 1000100110 0 evx evmwhu mi evmwhu mia 011111 rd ra rb 1000110110 0 evx evmwhu mia evmwhus iaaw 011111 rd ra rb 1010100010 0 evx evmwhusi aaw evmwhus ianw 011111 rd ra rb 1011100010 0 evx evmwhusi anw evmwlsm f 011111 rd ra rb 1000100101 1 evx evmwlsmf evmwlsm fa 011111 rd ra rb 1000110101 1 evx evmwlsmf a evmwlsm faaw 011111 rd ra rb 1010100101 1 evx evmwlsmf aaw evmwlsm fanw 011111 rd ra rb 1011100101 1 evx evmwlsmf anw evmwlsm iaaw 011111 rd ra rb 1010100100 1 evx evmwlsmi aaw evmwlsm ianw 011111 rd ra rb 1011100100 1 evx evmwlsmi anw evmwlssf 011111 rd ra rb 1000100001 1 evx evmwlssf evmwlssf a 011111 rd ra rb 1000110001 1 evx evmwlssf a evmwlssf aaw 011111 rd ra rb 1010100001 1 evx evmwlssf aaw evmwlssf anw 011111 rd ra rb 1011100001 1 evx evmwlssf anw evmwlssi aaw 011111 rd ra rb 1010100000 1 evx evmwlssi aaw evmwlssi anw 011111 rd ra rb 1011100000 1 evx evmwlssi anw evmwlum i 011111 rd ra rb 1000100100 0 evx evmwlumi evmwlum ia 011111 rd ra rb 1000110100 0 evx evmwlumi a evmwlum iaaw 011111 rd ra rb 1010100100 0 evx evmwlumi aaw evmwlum ianw 011111 rd ra rb 1011100100 0 evx evmwlumi anw table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1076/1176 evmwlusi aaw 011111 rd ra rb 1010100000 0 evx evmwlusi aaw evmwlusi anw 011111 rd ra rb 1011100000 0 evx evmwlusi anw evmwsmf 011111 rd ra rb 1000101101 1 evx evmwsmf evmwsmf a 011111 rd ra rb 1000111101 1 evx evmwsmf a evmwsmf aa 011111 rd ra rb 1010101101 1 evx evmwsmf aa evmwsmf an 011111 rd ra rb 1011101101 1 evx evmwsmf an evmwsmi 011111 rd ra rb 1000101100 1 evx evmwsmi evmwsmi a 011111 rd ra rb 1000111100 1 evx evmwsmi a evmwsmi aa 011111 rd ra rb 1010101100 1 evx evmwsmi aa evmwsmi an 011111 rd ra rb 1011101100 1 evx evmwsmi an evmwssf 011111 rd ra rb 1000101001 1 evx evmwssf evmwssf a 011111 rd ra rb 1000111001 1 evx evmwssfa evmwssf aa 011111 rd ra rb 1010101001 1 evx evmwssfa a evmwssf an 011111 rd ra rb 1011101001 1 evx evmwssfa n evmwumi 011111 rd ra rb 1000101100 0 evx evmwumi evmwumi a 011111 rd ra rb 1000111100 0 evx evmwumi a evmwumi aa 011111 rd ra rb 1010101100 0 evx evmwumi aa evmwumi an 011111 rd ra rb 1011101100 0 evx evmwumi an evnand 011111 rd ra rb 0100001111 0 evx evnand evneg 011111 rd ra /// 0100000100 1 evx evneg evnor 011111 rd ra rb 0100001100 0 evx evnor evnot evnot r d ,r a equivalent to evnor r d ,r a ,r a evnot evor 011111 rd ra rb 0100001011 1 evx evor evorc 011111 rd ra rb 0100001101 1 evx evorc evrlw 011111 rd ra rb 0100010100 0 evx evrlw evrlwi 011111 rd ra uimm 0100010101 0 evx evrlwi evrndw 011111 rd ra uimm 0100000110 0 evx evrndw evsel 011111 rd ra rb 01001111 crfs evx evsel evslw 011111 rd ra rb 0100010010 0 evx evslw evslwi 011111 rd ra uimm 0100010011 0 evx evslwi evsplatfi 011111 rd simm /// 0100010101 1 evx evsplatfi evsplati 011111 rd simm /// 0100010100 1 evx evsplati evsrwis 011111 rd ra uimm 0100010001 1 evx evsrwis table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1077/1176 evsrwiu 011111 rd ra uimm 0100010001 0 evx evsrwiu evsrws 011111 rd ra rb 0100010000 1 evx evsrws evsrwu 011111 rd ra rb 0100010000 0 evx evsrwu evstdd 011111 rd ra uimm 8 0110010000 1 evx evstdd evstddx 011111 rs ra rb 0110010000 0 evx evstddx evstdh 011111 rs ra uimm 8 0110010010 1 evx evstdh evstdhx 011111 rs ra rb 0110010010 0 evx evstdhx evstdw 011111 rs ra uimm 8 0110010001 1 evx evstdw evstdwx 011111 rs ra rb 0110010001 0 evx evstdwx evstwhe 011111 rs ra uimm 10 0110011000 1 evx evstwhe evstwhex 011111 rs ra rb 0110011000 0 evx evstwhex evstwho 011111 rs ra uimm 10 0110011010 1 evx evstwho evstwhox 011111 rs ra rb 0110011010 0 evx evstwhox evstwwe 011111 rs ra uimm 10 0110011100 1 evx evstwwe evstwwex 011111 rs ra rb 0110011100 0 evx evstwwex evstwwo 011111 rs ra uimm 10 0110011110 1 evx evstwwo evstwwo x 011111 rs ra rb 0110011110 0 evx evstwwox evsubfsm iaaw 011111 rd ra /// 1001100101 1 evx evsubfsm iaaw evsubfssi aaw 011111 rd ra /// 1001100001 1 evx evsubfssi aaw evsubfu miaaw 011111 rd ra /// 1001100101 0 evx evsubfum iaaw evsubfusi aaw 011111 rd ra /// 1001100001 0 evx evsubfusi aaw evsubfw 011111 rd ra rb 0100000010 0 evx evsubfw evsubifw 011111 rd uimm rb 0100000011 0 evx evsubifw evsubiw evsubiw r d ,r b ,uimm equivalent to evsubifw r d , uimm ,r b evsubiw evsubw evsubw r d ,r b ,r a equivalent to evsubfw r d ,r a ,r b evsubw evxor 011111 rd ra rb 0100001011 0 evx evxor extlwi extlwi r a ,r s , n , b (n > 0) equivalent to rlwinm r a ,r s , b ,0, n ? 1 extlwi extrwi extrwi r a ,r s , n , b ( n > 0) equivalent to rlwinm r a ,r s , b + n , 32 ? n ,31 extrwi extsb 011111 rs ra /// 1110111010 0 x extsb extsb. 011111 rs ra /// 1110111010 1 x extsb. extsh 011111 rs ra /// 1110011010 0 x extsh extsh. 011111 rs ra /// 1110011010 1 x extsh. fres 6 111011 frd /// frb /// 11000 0 a fres fres. 6 111011 frd /// frb /// 11000 1 a fres. fsel 6 111111 frd fra frb frc 10111 0 a fsel fsel. 6 111111 frd fra frb frc 10111 1 a fsel. table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1078/1176 icbi 011111 /// ra rb 1111010110 / x icbi icblc 011111 ct ra rb 0011100110 0 x icblc icbt 011111 ct ra rb 0000010110 / x icbt icbtls 011111 ct ra rb 0111100110 0 x icbtls inslwi inslwi r a ,r s , n , b ( n > 0) equivalent to rlwimi r a ,r s , 32 ? b , b , ( b + n ) ? 1 inslwi insrwi insrwi r a ,r s , n , b ( n > 0) equivalent to rlwimi r a ,r s , 32 ? ( b + n ) , b , ( b + n ) ? 1 insrwi isel 011111 rd ra rb crb 01111 0 x isel iseleq iseleq r d ,r a ,r b equivalent to isel r d ,r a ,r b ,2 iseleq iselgt iselgt r d ,r a ,r b equivalent to isel r d ,r a ,r b ,1 iselgt isellt isellt r d ,r a ,r b equivalent to isel r d ,r a ,r b ,0 isellt isync 010011 /// 0010010110 / xl isync la la r d ,d(r a ) equivalent to addi r d, r a , d la lbz 100010 rd ra d d lbz lbzu 100011 rd ra d d lbzu lbzux 011111 rd ra rb 0001110111 / x lbzux lbzx 011111 rd ra rb 0001010111 / x lbzx lha 101010 rd ra d d lha lhau 101011 rd ra d d lhau lhaux 011111 rd ra rb 0101110111 / x lhaux lhax 011111 rd ra rb 0101010111 / x lhax lhbrx 011111 rd ra rb 1100010110 / x lhbrx lhz 101000 rd ra d d lhz lhzu 101001 rd ra d d lhzu lhzux 011111 rd ra rb 0100110111 / x lhzux lhzx 011111 rd ra rb 0100010111 / x lhzx li li r d ,value equivalent to addi r d ,0, value li lis lis r d ,value equivalent to addis r d ,0, value lis lmw 101110 rd ra d d lmw lwarx 011111 rd ra rb 0000010100 / x lwarx lwbrx 011111 rd ra rb 1000010110 / x lwbrx lwz 100000 rd ra d d lwz lwzu 100001 rd ra d d lwzu lwzux 011111 rd ra rb 0000110111 / x lwzux lwzx 011111 rd ra rb 0000010111 / x lwzx mbar 011111 mo /// 1101010110 / x mbar mcrf 010011 crfd // crfs /// 0000000000 / xl mcrf mcrxr 011111 crfd /// 1000000000 / x mcrxr mfcr mtcr r s equivalent to mtcrf 0xff,r s mfcr mfcr 011111 rd /// 0000010011 / x mfcr mfdcr 0 1 1 1 1 1 rd dcrn5?9 dcrn0?4 0 1 0 1 0 0 0 0 1 1 / xfx mfdcr table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1079/1176 mfmsr 7 011111 rd /// 0001010011 / x mfmsr mfpmr 011111 rd pmrn5?9 pmrn0?4 0101001110 0 xfx mfpmr mf regna me mf regname r d equivalent to mfspr r d ,spr n mf regnam e mfspr 9 011111 rd spr[5?9] spr[0?4] 0101010011 / xfx mfspr mr mr r a ,r s equivalent to or r a ,r s ,r s mr msync 011111 /// 1001010110 / x msync mtcr mtcr r s equivalent to mtcrf 0xff ,r s mtcr mtcrf 011111 rs / crm / 0010010000 / xfx mtcrf mtdcr 0 1 1 1 1 1 rs dcrn5?9 dcrn0?4 0 1 1 1 0 0 0 0 1 1 / xfx mtdcr mtmsr 7 011111 rs /// 0010010010 / x mtmsr mtpmr 011111 rs pmrn5?9 pmrn0?4 0111001110 0 xfx mtpmr mt regna me mt regname r s equivalent to mtspr spr n r s mt regnam e mtspr (9) 011111 rs spr[5?9] spr[0?4] 0111010011 / xfx mtspr mulhw 011111 rd ra rb / 001001011 0 x mulhw mulhw. 011111 rd ra rb / 001001011 1 x mulhw. mulhwu 011111 rd ra rb / 000001011 0 x mulhwu mulhwu. 011111 rd ra rb / 000001011 1 x mulhwu. mulli 000111 rd ra simm d mulli mullw 011111 rd ra rb 0011101011 0 x mullw mullw. 011111 rd ra rb 0011101011 1 x mullw. mullwo 011111 rd ra rb 1011101011 0 x mullwo mullwo. 011111 rd ra rb 1011101011 1 x mullwo. nand 011111 rs ra rb 0111011100 0 x nand nand. 011111 rs ra rb 0111011100 1 x nand. neg 011111 rd ra /// 0001101000 0 x neg neg. 011111 rd ra /// 0001101000 1 x neg. nego 011111 rd ra /// 1001101000 0 x nego nego. 011111 rd ra /// 1001101000 1 x nego. nop nop equivalent to ori 0,0,0 nop nor 011111 rs ra rb 0001111100 0 x nor nor. 011111 rs ra rb 0001111100 1 x nor. not not r a ,r s equivalent to nor r a ,r s ,r s not or 011111 rs ra rb 0110111100 0 x or or. 011111 rs ra rb 0110111100 1 x or. orc 011111 rs ra rb 0110011100 0 x orc orc. 011111 rs ra rb 0110011100 1 x orc. ori 011000 rs ra uimm d ori oris 011001 rs ra uimm d oris rfci 010011 /// 0000110011 / xl rfci table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1080/1176 rfdi 7 0100110000000000000000000100111 0 x rfdi rfi 7 010011 /// 0000110010 / xl rfi rfmci 7 010011 /// 0000100110 / xl rfmci rlwimi 010100 rs ra sh mb me 0 m rlwimi rlwimi. 010100 rs ra sh mb me 1 m rlwimi. rlwinm 010101 rs ra sh mb me 0 m rlwinm rlwinm. 010101 rs ra sh mb me 1 m rlwinm. rlwnm 010111 rs ra rb mb me 0 m rlwnm rlwnm. 010111 rs ra rb mb me 1 m rlwnm. rotlw rotlw r a ,r s ,r b equivalent to rlwnm r a ,r s ,r b ,0,31 rotlw rotlwi rotlwi r a ,r s , n equivalent to rlwinm r a ,r s , n ,0,31 rotlwi rotrwi rotrwi r a ,r s , n equivalent to rlwinm r a ,r s , 32 ? n ,0,31 rotrwi sc 010001 /// 1 / sc sc slw 011111 rs ra rb 0000011000 0 x slw slw. 011111 rs ra rb 0000011000 1 x slw. slwi slwi r a ,r s , n (n < 32)equivalent to rlwinm r a ,r s , n ,0, 31 ? n slwi sraw 011111 rs ra rb 1100011000 0 x sraw sraw. 011111 rs ra rb 1100011000 1 x sraw. srawi 011111 rs ra sh 1100111000 0 x srawi srawi. 011111 rs ra sh 1100111000 1 x srawi. srw 011111 rs ra rb 1000011000 0 x srw srw. 011111 rs ra rb 1000011000 1 x srw. srwi srwi r a ,r s , n (n < 32)equivalent to rlwinm r a ,r s , 32 ? n , n ,31 srwi stb 100110 rs ra d d stb stbu 100111 rs ra d d stbu stbux 011111 rs ra rb 0011110111 0 x stbux stbx 011111 rs ra rb 0011010111 0 x stbx sth 101100 rs ra d d sth sthbrx 011111 rs ra rb 1110010110 / x sthbrx sthu 101101 rs ra d d sthu sthux 011111 rs ra rb 0110110111 / x sthux sthx 011111 rs ra rb 0110010111 / x sthx stmw 101111 rs ra d d stmw stw 100100 rs ra d d stw stwbrx 011111 rs ra rb 1010010110 / x stwbrx stwcx. 011111 rs ra rb 0010010110 1 x stwcx. stwu 100101 rs ra d d stwu stwux 011111 rs ra rb 0010110111 / d stwux stwx 011111 rs ra rb 0010010111 / d stwx sub sub r d ,r a ,r b equivalent to subf r d ,r b ,r a sub table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1081/1176 subc subc r d ,r a ,r b equivalent to subfc r d ,r b ,r a subc subf 011111 rd ra rb 0000101000 0 x subf subf. 011111 rd ra rb 0000101000 1 x subf. subfc 011111 rd ra rb 0000001000 0 x subfc subfc. 011111 rd ra rb 0000001000 1 x subfc. subfco 011111 rd ra rb 1000001000 0 x subfco subfco. 011111 rd ra rb 1000001000 1 x subfco. subfe 011111 rd ra rb 0010001000 0 x subfe subfe. 011111 rd ra rb 0010001000 1 x subfe. subfeo 011111 rd ra rb 1010001000 0 x subfeo subfeo. 011111 rd ra rb 1010001000 1 x subfeo. subfic 001000 rd ra simm d subfic subfme 011111 rd ra /// 0011101000 0 x subfme subfme. 011111 rd ra /// 0011101000 1 x subfme. subfmeo 011111 rd ra /// 1011101000 0 x subfmeo subfmeo. 011111 rd ra /// 1011101000 1 x subfmeo. subfo 011111 rd ra rb 1000101000 0 x subfo subfo. 011111 rd ra rb 1000101000 1 x subfo. subfze 011111 rd ra /// 0011001000 0 x subfze subfze. 011111 rd ra /// 0011001000 1 x subfze. subfzeo 011111 rd ra /// 1011001000 0 x subfzeo subfzeo. 011111 rd ra /// 1011001000 1 x subfzeo. subi subi r d ,r a ,value equivalent to addi r d ,r a , ?value subi subic subic r d ,r a ,value equivalent to addic r d ,r a , ?value subic subic. subic. r d ,r a ,value equivalent to addic. r d ,r a , ?value subic. subis subis r d ,r a ,value equivalent to addis r d ,r a , ?value subis tlbie 6 , 7 011111 /// /// rb 0100110010 0 x tlbie tlbivax 011111 /// ra rb 1100010010 / x tlbivax tlbre 011111 /// 10 1110110010 / x tlbre tlbsx 011111 /// 12 ra rb 1110010010/12 x tlbsx tlbsync 6 , 7 011111 /// /// /// 1000110110 / x tlbsync tlbwe 011111 /// 12 1111010010 / x tlbwe tw 011111 to ra rb 0000000100 / x tw tweq tweq r a ,simm equivalent to tw 4,r a , simm tweq tweqi tweqi r a ,simm equivalent to twi 4,r a , simm tweqi twge twge r a ,simm equivalent to tw 12,r a , simm twge twgei twgei r a ,simm equivalent to twi 12,r a , simm twgei twgt twgt r a ,simm equivalent to tw 8,r a , simm twgt twgti twgti r a ,simm equivalent to twi 8,r a , simm twgti table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic RM0004 instruction set listings 1082/1176 twi 000011 to ra simm d twi twle twle r a ,simm equivalent to tw 20,r a , simm twle twlei twlei r a ,simm equivalent to twi 20,r a , simm twlei twlge twlge r a ,simm equivalent to tw 12,r a , simm twlge twlgei twlgei r a ,simm equivalent to twi 12,r a , simm twlgei twlgt twlgt r a ,simm equivalent to tw 1,r a , simm twlgt twlgti twlgti r a ,simm equivalent to twi 1,r a , simm twlgti twlle twlle r a ,simm equivalent to tw 6,r a , simm twlle twllei twllei r a ,simm equivalent to twi 6,r a , simm twllei twllt twllt r a ,simm equivalent to tw 2,r a , simm twllt twllti twllti r a ,simm equivalent to twi 2,r a , simm twllti twlng twlng r a ,simm equivalent to tw 6,r a , simm twlng twlngi twlngi r a ,simm equivalent to twi 6,r a , simm twlngi twlnl twlnl r a ,simm equivalent to tw 5,r a , simm twlnl twlnli twlnli r a ,simm equivalent to twi 5,r a , simm twlnli twlt twlt r a ,simm equivalent to tw 16,r a , simm twlt twlti twlti r a ,simm equivalent to twi 16,r a , simm twlti twne twne r a ,simm equivalent to tw 24,r a , simm twne twnei twnei r a ,simm equivalent to twi 24,r a , simm twnei twng twng r a ,simm equivalent to tw 20,r a , simm twng twngi twngi r a ,simm equivalent to twi 20,r a , simm twngi twnl twnl r a ,simm equivalent to tw 12,r a , simm twnl twnli twnli r a ,simm equivalent to twi 12,r a , simm twnli wait 011111 /// 0 000111110 / wait wrtee 011111 rs /// 0010000011 / x wrtee wrteei 011111 /// e /// 0010100011 / x wrteei xor 011111 rs ra rb 0100111100 0 x xor xor. 011111 rs ra rb 0100111100 1 x xor. xori 011010 rs ra uimm d xori xoris 011011 rs ra uimm d xoris 1. simplified mnemonics for branch instructions that do not test a cr bit should not specify one; a programming error may occur. 2. the value in the bi operand selects crn[2], the eq bit. 3. the value in the bi operand selects crn[0], the lt bit. 4. the value in the bi operand selects crn[1], the gt bit. 5. the value in the bi operand selects crn[3], the so bit. 6. optional to the powerpc classic architecture. 7. supervisor-level instruction. 8. d = uimm * 8 9. access level is detemined by whether the spr is defined as a user or supervisor level spr. table 271. instructions sorted by mnemonic (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031form mnemonic instruction set listings RM0004 1083/1176 a.4 instructions sorted by opcode (binary) table 272 lists instructions by opcode, shown in binary. table 272. instructions sorted by opcode (binary) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic rfdi 1 01001100000000000000000001001110 x rfdi twi 000011 to ra simm d twi brinc 000100 rd ra rb 01000001111evx brinc efdabs 000100 rd ra /// 01011100100efx efdabs efdadd 000100 rd ra rb 01011100000efx efdadd efdcfs 000100 rd 00000 rb 0 1011101111efx efdcfs efdcfsf 000100 rd /// rb 01011110011efx efdcfsf efdcfsi 000100 rd /// rb 01011110001efx efdcfsi efdcfuf 000100 rd /// rb 01011110010efx efdcfuf efdcfui 000100 rd /// rb 01011110000efx efdcfui efdcmp eq 000100 crfd / / ra rb 01011101110efx efdcmpe q efdcmp gt 000100 crfd / / ra rb 01011101100efx efdcmpg t efdcmpl t 000100 crfd / / ra rb 01011101101efx efdcmplt efdctsf 000100 rd /// rb 01011110111efx efdctsf efdctsi 000100 rd /// rb 01011110101efx efdctsi efdctsiz 000100 rd /// rb 01011111010efx efdctsiz efdctuf 000100 rd /// rb 01011110110efx efdctuf efdctui 000100 rd /// rb 01011110100efx efdctui efdctuiz 000100 rd /// rb 01011111000efx efdctuiz efddiv 000100 rd ra rb 01011101001efx efddiv efdmul 000100 rd ra rb 01011101000efx efdmul efdnabs 000100 rd ra /// 01011100101efx efdnabs efdneg 000100 rd ra /// 01011100110efx efdneg efdsub 000100 rd ra rb 01011100001efx efdsub efdtsteq 000100 crfd / / ra rb 01011111110efx efdtsteq efdtstgt 000100 crfd / / ra rb 01011111100efx efdtstgt efdtstlt 000100 crfd / / ra rb 01011111101efx efdtstlt efsabs 000100 rd ra /// 01011000100efx efsabs efsadd 000100 rd ra rb 01011000000efx efsadd efscfd 000100 rd 00000 rb 0 1011001111efx efscfd efscfsf 000100 rd /// rb 01011010011efx efscfsf efscfsi 000100 rd /// rb 01011010001efx efscfsi efscfuf 000100 rd /// rb 01011010010efx efscfuf efscfui 000100 rd /// rb 01011010000efx efscfui RM0004 instruction set listings 1084/1176 efscmp eq 000100 crfd / / ra rb 01011001110efx efscmpe q efscmp gt 000100 crfd / / ra rb 01011001100efx efscmpg t efscmpl t 000100 crfd / / ra rb 01011001101efx efscmplt efsctsf 000100 rd /// rb 01011010111efx efsctsf efsctsi 000100 rd /// rb 01011010101efx efsctsi efsctsiz 000100 rd /// rb 01011011010efx efsctsiz efsctuf 000100 rd /// rb 01011010110efx efsctuf efsctui 000100 rd /// rb 01011010100efx efsctui efsctuiz 000100 rd /// rb 01011011000efx efsctuiz efsdiv 000100 rd ra rb 01011001001efx efsdiv efsmul 000100 rd ra rb 01011001000efx efsmul efsnabs 000100 rd ra /// 01011000101efx efsnabs efsneg 000100 rd ra /// 01011000110efx efsneg efssub 000100 rd ra rb 01011000001efx efssub efststeq 000100 crfd / / ra rb 01011011110efx efststeq efststgt 000100 crfd / / ra rb 01011011100efx efststgt efststlt 000100 crfd / / ra rb 01011011101efx efststlt mulli 000111 rd ra simm d mulli subfic 001000 rd ra simm d subfic cmpli 001010 crfd / l ra uimm d cmpli cmpi 001011 crfd / l ra simm d cmpi addic 001100 rd ra simm d addic addic. 001101 rd ra simm d addic. addi 001110 rd ra simm d addi addis 001111 rd ra simm d addis bc 010000 bo bi bd 00 b bc bca 010000 bo bi bd 10 b bca bcl 010000 bo bi bd 01 b bcl bcla 010000 bo bi bd 11 b bcla sc 010001 /// 1 / sc sc b 010010 li 00 i b ba 010010 li 10 i ba bl 010010 li 01 i bl bla 010010 li 11 i bla rfci 010011 /// 0000110011 / xl rfci rfmci 1 010011 /// 0000100110 / xl rfmci mcrf 010011 crfd // crfs /// 0000000000 / xl mcrf bclr 010011 bo bi /// 00000100000 xl bclr table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic instruction set listings RM0004 1085/1176 bclrl 010011 bo bi /// 00000100001 xl bclrl crnor 010011 crbd crba crbb 0000100001 / xl crnor rfi (1) 010011 /// 0000110010 / xl rfi crandc 010011 crbd crba crbb 0010000001 / xl crandc isync 010011 /// 0010010110 / xl isync crxor 010011 crbd crba crbb 0011000001 / xl crxor crand 010011 crbd crba crbb 0100000001 / xl crand crnand 010011 crbd crba crbb 0011100001 / xl crnand creqv 010011 crbd crba crbb 0100100001 / xl creqv crorc 010011 crbd crba crbb 0110100001 / xl crorc cror 010011 crbd crba crbb 0111000001 / xl cror bcctr 010011 bo bi /// 10000100000 xl bcctr bcctrl 010011 bo bi /// 10000100001 xl bcctrl rlwimi 010100 rs ra sh mb me 0 m rlwimi rlwimi. 010100 rs ra sh mb me 1 m rlwimi. rlwinm 010101 rs ra sh mb me 0 m rlwinm rlwinm. 010101 rs ra sh mb me 1 m rlwinm. rlwnm 010111 rs ra rb mb me 0 m rlwnm rlwnm. 010111 rs ra rb mb me 1 m rlwnm. ori 011000 rs ra uimm d ori oris 011001 rs ra uimm d oris xori 011010 rs ra uimm d xori xoris 011011 rs ra uimm d xoris andi. 011100 rs ra uimm d andi. andis. 011101 rs ra uimm d andis. dcblc 011111 ct ra rb 01100001100 x dcblc dcbtls 011111 ct ra rb 00101001100 x dcbtls dcbtstls 011111 ct ra rb 00100001100 x dcbtstls evabs 011111 rd ra /// 01000001000evx evabs evaddiw 011111 rd uimm rb 01000000010evx evaddiw evadds miaaw 011111 rd ra /// 10011001001evx evadds miaaw evaddss iaaw 011111 rd ra /// 10011000001evx evaddssi aaw evaddu miaaw 011111 rd ra /// 10011001000evx evaddu miaaw evaddus iaaw 011111 rd ra /// 10011000000evx evaddus iaaw evaddw 011111 rd ra rb 01000000000evx evaddw evand 011111 rd ra rb 01000010001evx evand evandc 011111 rd ra rb 01000010010evx evandc table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic RM0004 instruction set listings 1086/1176 evcmpe q 011111 crfd / / ra rb 01000110100evx evcmpe q evcmpg ts 011111 crfd / / ra rb 01000110001evx evcmpgt s evcmpg tu 011111 crfd / / ra rb 01000110000evx evcmpgt u evcmplt s 011111 crfd / / ra rb 01000110011evx evcmplt s evcmplt u 011111 crfd / / ra rb 01000110010evx evcmplt u evcntls w 011111 rd ra /// 01000001110evx evcntlsw evcntlz w 011111 rd ra /// 01000001101evx evcntlzw evdivws 011111 rd ra rb 10011000110evx evdivws evdivwu 011111 rd ra rb 10011000111evx evdivwu eveqv 011111 rd ra rb 01000011001evx eveqv evextsb 011111 rd ra /// 01000001010evx evextsb evextsh 011111 rd ra /// 01000001011evx evextsh evfsabs 011111 rd ra /// 01010000100evx evfsabs evfsadd 011111 rd ra rb 01010000000evx evfsadd evfscfsf 011111 rd /// rb 01010010011evx evfscfsf evfscfsi 011111 rd /// rb 01010010001evx evfscfsi evfscfuf 011111 rd /// rb 01010010010evx evfscfuf evfscfui 011111 rd /// rb 01010010000evx evfscfui evfscm peq 011111 crfd / / ra rb 01010001110evx evfscmp eq evfscm pgt 011111 crfd / / ra rb 01010001100evx evfscmp gt evfscm plt 011111 crfd / / ra rb 01010001101evx evfscmp lt evfsctsf 011111 rd /// rb 01010010111evx evfsctsf evfsctsi 011111 rd /// rb 01010010101evx evfsctsi evfsctsi z 011111 rd /// rb 01010011010evx evfsctsiz evfsctuf 011111 rd /// rb 01010010110evx evfsctuf evfsctui 011111 rd /// rb 01010010100evx evfsctui evfsctui z 011111 rd /// rb 01010011000evx evfsctui z evfsdiv 011111 rd ra rb 01010001001evx evfsdiv evfsmul 011111 rd ra rb 01010001000evx evfsmul evfsnab s 011111 rd ra /// 01010000101evx evfsnab s evfsneg 011111 rd ra /// 01010000110evx evfsneg evfssub 011111 rd ra rb 01010000001evx evfssub table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic instruction set listings RM0004 1087/1176 evfstste q 011111 crfd / / ra rb 01010011110evx evfstste q evfststg t 011111 crfd / / ra rb 01010011100evx evfststgt evfststlt 011111 crfd / / ra rb 01010011101evx evfststlt evldd 011111 rd ra uimm (2) 01100000001evx evldd evlddx 011111 rd ra rb 01100000000evx evlddx evldh 011111 rd ra uimm 2 01100000101evx evldh evldhx 011111 rd ra rb 01100000100evx evldhx evldw 011111 rd ra uimm 2 01100000011evx evldw evldwx 011111 rd ra rb 01100000010evx evldwx evlhhes plat 011111 rd ra uimm 3 01100001001evx evlhhes plat evlhhes platx 011111 rd ra rb 01100001000evx evlhhes platx evlhhos splat 011111 rd ra uimm 3 01100001111evx evlhhos splat evlhhos splatx 011111 rd ra rb 01100001110evx evlhhos splatx evlhhou splat 011111 rd ra uimm 3 01100001101evx evlhhou splat evlhhou splatx 011111 rd ra rb 01100001100evx evlhhou splatx evlwhe 011111 rd ra uimm 3 01100010001evx evlwhe evlwhex 011111 rd ra rb 01100010000evx evlwhex evlwhos 011111 rd ra uimm 4 01100010111evx evlwhos evlwhos x 011111 rd ra rb 01100010110evx evlwhos x evlwhou 011111 rd ra uimm 4 01100010101evx evlwhou evlwhou x 011111 rd ra rb 01100010100evx evlwhou x evlwhsp lat 011111 rd ra uimm 4 01100011101evx evlwhspl at evlwhsp latx 011111 rd ra rb 01100011100evx evlwhspl atx evlwws plat 011111 rd ra uimm 4 01100011001evx evlwwsp lat evlwws platx 011111 rd ra rb 01100011000evx evlwwsp latx evmerg ehi 011111 rd ra rb 01000101100evx evmerge hi evmerg ehilo 011111 rd ra rb 01000101110evx evmerge hilo evmerg elo 011111 rd ra rb 01000101101evx evmerge lo evmerg elohi 011111 rd ra rb 01000101111evx evmerge lohi table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic RM0004 instruction set listings 1088/1176 evmheg smfaa 011111 rd ra rb 10100101011evx evmheg smfaa evmheg smfan 011111 rd ra rb 10110101011evx evmheg smfan evmheg smiaa 011111 rd ra rb 10100101001evx evmheg smiaa evmheg smian 011111 rd ra rb 10110101001evx evmheg smian evmheg umiaa 011111 rd ra rb 10100101000evx evmheg umiaa evmheg umian 011111 rd ra rb 10110101000evx evmheg umian evmhes mf 011111 rd ra rb 10000001011evx evmhes mf evmhes mfa 011111 rd ra rb 10000101011evx evmhes mfa evmhes mfaaw 011111 rd ra rb 10100001011evx evmhes mfaaw evmhes mfanw 011111 rd ra rb 10110001011evx evmhes mfanw evmhes mi 011111 rd ra rb 10000001001evx evmhes mi evmhes mia 011111 rd ra rb 10000101001evx evmhes mia evmhes miaaw 011111 rd ra rb 10100001001evx evmhes miaaw evmhes mianw 011111 rd ra rb 10110001001evx evmhes mianw evmhes sf 011111 rd ra rb 10000000011evx evmhes sf evmhes sfa 011111 rd ra rb 10000100011evx evmhes sfa evmhes sfaaw 011111 rd ra rb 10100000011evx evmhes sfaaw evmhes sfanw 011111 rd ra rb 10110000011evx evmhes sfanw evmhes siaaw 011111 rd ra rb 10100000001evx evmhes siaaw evmhes sianw 011111 rd ra rb 10110000001evx evmhes sianw evmheu mi 011111 rd ra rb 10000001000evx evmheu mi evmheu mia 011111 rd ra rb 10000101000evx evmheu mia evmheu miaaw 011111 rd ra rb 10100001000evx evmheu miaaw evmheu mianw 011111 rd ra rb 10110001000evx evmheu mianw evmheu siaaw 011111 rd ra rb 10100000000evx evmheu siaaw evmheu sianw 011111 rd ra rb 10110000000evx evmheu sianw table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic instruction set listings RM0004 1089/1176 evmhog smfaa 011111 rd ra rb 10100101111evx evmhog smfaa evmhog smfan 011111 rd ra rb 10110101111evx evmhog smfan evmhog smiaa 011111 rd ra rb 10100101101evx evmhog smiaa evmhog smian 011111 rd ra rb 10110101101evx evmhog smian evmhog umiaa 011111 rd ra rb 10100101100evx evmhog umiaa evmhog umian 011111 rd ra rb 10110101100evx evmhog umian evmhos mf 011111 rd ra rb 10000001111evx evmhos mf evmhos mfa 011111 rd ra rb 10000101111evx evmhos mfa evmhos mfaaw 011111 rd ra rb 10100001111evx evmhos mfaaw evmhos mfanw 011111 rd ra rb 10110001111evx evmhos mfanw evmhos mi 011111 rd ra rb 10000001101evx evmhos mi evmhos mia 011111 rd ra rb 10000101101evx evmhos mia evmhos miaaw 011111 rd ra rb 10100001101evx evmhos miaaw evmhos mianw 011111 rd ra rb 10110001101evx evmhos mianw evmhos sf 011111 rd ra rb 10000000111evx evmhos sf evmhos sfa 011111 rd ra rb 10000100111evx evmhos sfa evmhos sfaaw 011111 rd ra rb 10100000111evx evmhos sfaaw evmhos sfanw 011111 rd ra rb 10110000111evx evmhos sfanw evmhos siaaw 011111 rd ra rb 10100000101evx evmhos siaaw evmhos sianw 011111 rd ra rb 10110000101evx evmhos sianw evmhou mi 011111 rd ra rb 10000001100evx evmhou mi evmhou mia 011111 rd ra rb 10000101100evx evmhou mia evmhou miaaw 011111 rd ra rb 10100001100evx evmhou miaaw evmhou mianw 011111 rd ra rb 10110001100evx evmhou mianw evmhou siaaw 011111 rd ra rb 10100000100evx evmhou siaaw evmhou sianw 011111 rd ra rb 10110000100evx evmhou sianw table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic RM0004 instruction set listings 1090/1176 evmra 011111 rd ra /// 10011000100evx evmra evmwhg smfaa 011111 rd ra rb 10101101111evx evmwhg smfaa evmwhg smfan 011111 rd ra rb 10111011111evx evmwhg smfan evmwhg smiaa 011111 rd ra rb 10101101101evx evmwhg smiaa evmwhg smian 011111 rd ra rb 10111011101evx evmwhg smian evmwhg ssfaa 011111 rd ra rb 10101100111evx evmwhg ssfaa evmwhg ssfan 011111 rd ra rb 10111010111evx evmwhg ssfan evmwhg umiaa 011111 rd ra rb 10101101100evx evmwhg umiaa evmwhg umian 011111 rd ra rb 10111011100evx evmwhg umian evmwhs mf 011111 rd ra rb 10001001111evx evmwhs mf evmwhs mfa 011111 rd ra rb 10001101111evx evmwhs mfa evmwhs mfaaw 011111 rd ra rb 10101001111evx evmwhs mfaaw evmwhs mfanw 011111 rd ra rb 10111001111evx evmwhs mfanw evmwhs mi 011111 rd ra rb 10001001101evx evmwhs mi evmwhs mia 011111 rd ra rb 10001101101evx evmwhs mia evmwhs miaaw 011111 rd ra rb 10101001101evx evmwhs miaaw evmwhs mianw 011111 rd ra rb 10111001101evx evmwhs mianw evmwhs sf 011111 rd ra rb 10001000111evx evmwhs sf evmwhs sfa 011111 rd ra rb 10001100111evx evmwhs sfa evmwhs sfaaw 011111 rd ra rb 10101000111evx evmwhs sfaaw evmwhs sfanw 011111 rd ra rb 10111000111evx evmwhs sfanw evmwhs sianw 011111 rd ra rb 10111000101evx evmwhs sianw evmwhs smaaw 011111 rd ra rb 10101000101evx evmwhs smaaw evmwhu mi 011111 rd ra rb 10001001100evx evmwhu mi evmwhu mia 011111 rd ra rb 10001101100evx evmwhu mia evmwhu siaaw 011111 rd ra rb 10101000100evx evmwhu siaaw table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic instruction set listings RM0004 1091/1176 evmwhu sianw 011111 rd ra rb 10111000100evx evmwhu sianw evmwls mf 011111 rd ra rb 10001001011evx evmwls mf evmwls mfa 011111 rd ra rb 10001101011evx evmwls mfa evmwls mfaaw 011111 rd ra rb 10101001011evx evmwls mfaaw evmwls mfanw 011111 rd ra rb 10111001011evx evmwls mfanw evmwls miaaw 011111 rd ra rb 10101001001evx evmwls miaaw evmwls mianw 011111 rd ra rb 10111001001evx evmwls mianw evmwls sf 011111 rd ra rb 10001000011evx evmwlss f evmwls sfa 011111 rd ra rb 10001100011evx evmwlss fa evmwls sfaaw 011111 rd ra rb 10101000011evx evmwlss faaw evmwls sfanw 011111 rd ra rb 10111000011evx evmwlss fanw evmwls siaaw 011111 rd ra rb 10101000001evx evmwlss iaaw evmwls sianw 011111 rd ra rb 10111000001evx evmwlss ianw evmwlu mi 011111 rd ra rb 10001001000evx evmwlu mi evmwlu mia 011111 rd ra rb 10001101000evx evmwlu mia evmwlu miaaw 011111 rd ra rb 10101001000evx evmwlu miaaw evmwlu mianw 011111 rd ra rb 10111001000evx evmwlu mianw evmwlu siaaw 011111 rd ra rb 10101000000evx evmwlus iaaw evmwlu sianw 011111 rd ra rb 10111000000evx evmwlus ianw evmws mf 011111 rd ra rb 10001011011evx evmwsm f evmws mfa 011111 rd ra rb 10001111011evx evmwsm fa evmws mfaa 011111 rd ra rb 10101011011evx evmwsm faa evmws mfan 011111 rd ra rb 10111011011evx evmwsm fan evmws mi 011111 rd ra rb 10001011001evx evmwsm i evmws mia 011111 rd ra rb 10001111001evx evmwsm ia evmws miaa 011111 rd ra rb 10101011001evx evmwsm iaa table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic RM0004 instruction set listings 1092/1176 evmws mian 011111 rd ra rb 10111011001evx evmwsm ian evmwss f 011111 rd ra rb 10001010011evx evmwssf evmwss fa 011111 rd ra rb 10001110011evx evmwssf a evmwss faa 011111 rd ra rb 10101010011evx evmwssf aa evmwss fan 011111 rd ra rb 10111010011evx evmwssf an evmwu mi 011111 rd ra rb 10001011000evx evmwu mi evmwu mia 011111 rd ra rb 10001111000evx evmwu mia evmwu miaa 011111 rd ra rb 10101011000evx evmwu miaa evmwu mian 011111 rd ra rb 10111011000evx evmwu mian evnand 011111 rd ra rb 01000011110evx evnand evneg 011111 rd ra /// 01000001001evx evneg evnor 011111 rd ra rb 01000011000evx evnor evor 011111 rd ra rb 01000010111evx evor evorc 011111 rd ra rb 01000011011evx evorc evrlw 011111 rd ra rb 01000101000evx evrlw evrlwi 011111 rd ra uimm 01000101010evx evrlwi evrndw 011111 rd ra uimm 01000001100evx evrndw evsel 011111 rd ra rb 01001111 crfs evx evsel evslw 011111 rd ra rb 01000100100evx evslw evslwi 011111 rd ra uimm 01000100110evx evslwi evsplatf i 011111 rd simm /// 01000101011evx evsplatfi evsplati 011111 rd simm /// 01000101001evx evsplati evsrwis 011111 rd ra uimm 01000100011evx evsrwis evsrwiu 011111 rd ra uimm 01000100010evx evsrwiu evsrws 011111 rd ra rb 01000100001evx evsrws evsrwu 011111 rd ra rb 01000100000evx evsrwu evstdd 011111 rd ra uimm 2 01100100001evx evstdd evstddx 011111 rs ra rb 01100100000evx evstddx evstdh 011111 rs ra uimm 2 01100100101evx evstdh evstdhx 011111 rs ra rb 01100100100evx evstdhx evstdw 011111 rs ra uimm 2 01100100011evx evstdw evstdwx 011111 rs ra rb 01100100010evx evstdwx evstwhe 011111 rs ra uimm 4 01100110001evx evstwhe table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic instruction set listings RM0004 1093/1176 evstwhe x 011111 rs ra rb 01100110000evx evstwhe x evstwho 011111 rs ra uimm 4 01100110101evx evstwho evstwho x 011111 rs ra rb 01100110100evx evstwho x evstww e 011111 rs ra uimm 4 01100111001evx evstwwe evstww ex 011111 rs ra rb 01100111000evx evstwwe x evstww o 011111 rs ra uimm 4 01100111101evx evstwwo evstww ox 011111 rs ra rb 01100111100evx evstwwo x evsubfs miaaw 011111 rd ra /// 10011001011evx evsubfs miaaw evsubfs siaaw 011111 rd ra /// 10011000011evx evsubfs siaaw evsubfu miaaw 011111 rd ra /// 10011001010evx evsubfu miaaw evsubfu siaaw 011111 rd ra /// 10011000010evx evsubfu siaaw evsubfw 011111 rd ra rb 01000000100evx evsubfw evsubif w 011111 rd uimm rb 01000000110evx evsubif w evxor 011111 rd ra rb 01000010110evx evxor icblc 011111 ct ra rb 00111001100 x icblc icbt 011111 ct ra rb 0000010110 / x icbt icbtls 011111 ct ra rb 01111001100 x icbtls isel 011111 rd ra rb crb 011110 x isel mbar 011111 mo /// 1101010110 / x mbar mfdcr 011111 rd dcrn5?9 dcrn0?4 0 1 0 1000011 /xfx mfdcr mfpmr 011111 rd pmrn5?9 pmrn0?4 01010011100xfx mfpmr msync 011111 /// 1001010110 / x msync mtdcr 011111 rs dcrn5?9 dcrn0?4 0 1 1 1000011 /xfx mtdcr mtpmr 011111 rs pmrn5?9 pmrn0?4 01110011100xfx mtpmr tlbivax 011111 /// ra rb 1100010010 / x tlbivax tlbre 011111 /// 3 1110110010 / x tlbre tlbsx 011111 /// 5 ra rb 1110010010 / 5 x tlbsx tlbwe 011111 /// 5 1111010010 / x tlbwe wait 011111 /// 0 000111110 / wait wrtee 011111 rs /// 0010000011 / x wrtee wrteei 011111 /// e /// 0010100011 / x wrteei cmp 011111 crfd / l ra rb 0000000000 / x cmp tw 011111 to ra rb 0000000100 / x tw table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic RM0004 instruction set listings 1094/1176 subfc 011111 rd ra rb 00000010000 x subfc subfc. 011111 rd ra rb 00000010001 x subfc. addc 011111 rd ra rb 00000010100 x addc addc. 011111 rd ra rb 00000010101 x addc. mulhwu 011111 rd ra rb / 0000010110 x mulhwu mulhwu . 011111 rd ra rb / 0000010111 x mulhwu. mfcr 011111 rd /// 0000010011 / x mfcr lwarx 011111 rd ra rb 0000010100 / x lwarx lwzx 011111 rd ra rb 0000010111 / x lwzx slw 011111 rs ra rb 00000110000 x slw slw. 011111 rs ra rb 00000110001 x slw. cntlzw 011111 rs ra /// 00000110100 x cntlzw cntlzw. 011111 rs ra /// 00000110101 x cntlzw. and 011111 rs ra rb 00000111000 x and and. 011111 rs ra rb 00000111001 x and. cmpl 011111 / l ra rb /// 0000100000 / x cmpl subf 011111 rd ra rb 00001010000 x subf subf. 011111 rd ra rb 00001010001 x subf. dcbst 011111 /// ra rb 0000110110 / x dcbst lwzux 011111 rd ra rb 0000110111 / x lwzux andc 011111 rs ra rb 00001111000 x andc andc. 011111 rs ra rb 00001111001 x andc. mulhw 011111 rd ra rb / 0010010110 x mulhw mulhw. 011111 rd ra rb / 0010010111 x mulhw. mfmsr 1 011111 rd /// 0001010011 / x mfmsr dcbf 011111 /// ra rb 0001010110 / x dcbf lbzx 011111 rd ra rb 0001010111 / x lbzx neg 011111 rd ra /// 00011010000 x neg neg. 011111 rd ra /// 00011010001 x neg. lbzux 011111 rd ra rb 0001110111 / x lbzux nor 011111 rs ra rb 00011111000 x nor nor. 011111 rs ra rb 00011111001 x nor. subfe 011111 rd ra rb 00100010000 x subfe subfe. 011111 rd ra rb 00100010001 x subfe. adde 011111 rd ra rb 00100010100 x adde adde. 011111 rd ra rb 00100010101 x adde. mtcrf 011111 rs / crm / 0010010000 /xfx mtcrf mtmsr 1 011111 rs /// 0010010010 / x mtmsr stwcx. 011111 rs ra rb 00100101101 x stwcx. table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic instruction set listings RM0004 1095/1176 stwx 011111 rs ra rb 0010010111 / d stwx stwux 011111 rs ra rb 0010110111 / d stwux subfze 011111 rd ra /// 00110010000 x subfze subfze. 011111 rd ra /// 00110010001 x subfze. addze 011111 rd ra /// 00110010100 x addze addze. 011111 rd ra /// 00110010101 x addze. stbx 011111 rs ra rb 00110101110 x stbx subfme 011111 rd ra /// 00111010000 x subfme subfme. 011111 rd ra /// 00111010001 x subfme. addme 011111 rd ra /// 00111010100 x addme addme. 011111 rd ra /// 00111010101 x addme. mullw 011111 rd ra rb 00111010110 x mullw mullw. 011111 rd ra rb 00111010111 x mullw. dcbtst 011111 ct ra rb 0011110110 / x dcbtst stbux 011111 rs ra rb 00111101110 x stbux add 011111 rd ra rb 01000010100 x add add. 011111 rd ra rb 01000010101 x add. dcbt 011111 ct ra rb 0100010110 / x dcbt lhzx 011111 rd ra rb 0100010111 / x lhzx eqv 011111 rd ra rb 01000111000 x eqv eqv. 011111 rd ra rb 01000111001 x eqv. tlbie 1,3 011111 /// /// rb 01001100100 x tlbie lhzux 011111 rd ra rb 0100110111 / x lhzux xor 011111 rs ra rb 01001111000 x xor xor. 011111 rs ra rb 01001111001 x xor. mfspr 3 011111 rd spr[5?9] spr[0?4] 0101010011 /xfx mfspr lhax 011111 rd ra rb 0101010111 / x lhax lhaux 011111 rd ra rb 0101110111 / x lhaux sthx 011111 rs ra rb 0110010111 / x sthx orc 011111 rs ra rb 01100111000 x orc orc. 011111 rs ra rb 01100111001 x orc. sthux 011111 rs ra rb 0110110111 / x sthux or 011111 rs ra rb 01101111000 x or or. 011111 rs ra rb 01101111001 x or. divwu 011111 rd ra rb 01110010110 x divwu divwu. 011111 rd ra rb 01110010111 x divwu. mtspr 2 011111 rs spr[5?9] spr[0?4] 0111010011 /xfx mtspr dcbi 1 011111 /// ra rb 0111010110 / x dcbi nand 011111 rs ra rb 01110111000 x nand table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic RM0004 instruction set listings 1096/1176 nand. 011111 rs ra rb 01110111001 x nand. divw 011111 rd ra rb 01111010110 x divw divw. 011111 rd ra rb 01111010111 x divw. mcrxr 011111 crfd /// 1000000000 / x mcrxr subfco 011111 rd ra rb 10000010000 x subfco subfco. 011111 rd ra rb 10000010001 x subfco. addco 011111 rd ra rb 10000010100 x addco addco. 011111 rd ra rb 10000010101 x addco. lwbrx 011111 rd ra rb 1000010110 / x lwbrx srw 011111 rs ra rb 10000110000 x srw srw. 011111 rs ra rb 10000110001 x srw. subfo 011111 rd ra rb 10001010000 x subfo subfo. 011111 rd ra rb 10001010001 x subfo. tlbsync 1,6 011111 /// /// /// 1000110110 / x tlbsync nego 011111 rd ra /// 10011010000 x nego nego. 011111 rd ra /// 10011010001 x nego. subfeo 011111 rd ra rb 10100010000 x subfeo subfeo. 011111 rd ra rb 10100010001 x subfeo. addeo 011111 rd ra rb 10100010100 x addeo addeo. 011111 rd ra rb 10100010101 x addeo. stwbrx 011111 rs ra rb 1010010110 / x stwbrx subfzeo 011111 rd ra /// 10110010000 x subfzeo subfzeo . 011111 rd ra /// 10110010001 x subfzeo. addzeo 011111 rd ra /// 10110010100 x addzeo addzeo. 011111 rd ra /// 10110010101 x addzeo. subfme o 011111 rd ra /// 10111010000 x subfmeo subfme o. 011111 rd ra /// 10111010001 x subfmeo . addmeo 011111 rd ra /// 10111010100 x addmeo addmeo . 011111 rd ra /// 10111010101 x addmeo. mullwo 011111 rd ra rb 10111010110 x mullwo mullwo. 011111 rd ra rb 10111010111 x mullwo. dcba 6 011111 /// ra rb 1011110110 / x dcba addo 011111 rd ra rb 11000010100 x addo addo. 011111 rd ra rb 11000010101 x addo. lhbrx 011111 rd ra rb 1100010110 / x lhbrx sraw 011111 rs ra rb 11000110000 x sraw sraw. 011111 rs ra rb 11000110001 x sraw. table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic instruction set listings RM0004 1097/1176 a.5 instruction set legend table 273 provides general information on the instruction set (such as architectural level, privilege level, and form). srawi 011111 rs ra sh 11001110000 x srawi srawi. 011111 rs ra sh 11001110001 x srawi. sthbrx 011111 rs ra rb 1110010110 / x sthbrx extsh 011111 rs ra /// 11100110100 x extsh extsh. 011111 rs ra /// 11100110101 x extsh. extsb 011111 rs ra /// 11101110100 x extsb extsb. 011111 rs ra /// 11101110101 x extsb. divwuo 011111 rd ra rb 11110010110 x divwuo divwuo. 011111 rd ra rb 11110010111 x divwuo. icbi 011111 /// ra rb 1111010110 / x icbi divwo 011111 rd ra rb 11111010110 x divwo divwo. 011111 rd ra rb 11111010111 x divwo. dcbz 011111 /// ra rb 1111110110 / x dcbz lwz 100000 rd ra d d lwz lwzu 100001 rd ra d d lwzu lbz 100010 rd ra d d lbz lbzu 100011 rd ra d d lbzu stw 100100 rs ra d d stw stwu 100101 rs ra d d stwu stb 100110 rs ra d d stb stbu 100111 rs ra d d stbu lhz 101000 rd ra d d lhz lhzu 101001 rd ra d d lhzu lha 101010 rd ra d d lha lhau 101011 rd ra d d lhau sth 101100 rs ra d d sth sthu 101101 rs ra d d sthu lmw 101110 rd ra d d lmw stmw 101111 rs ra d d stmw fres 6 111011 frd /// frb /// 110000 a fres fres. 6 111011 frd /// frb /// 110001 a fres. fsel 6 111111 frd fra frb frc 101110 a fsel fsel. 6 111111 frd fra frb frc 101111 a fsel. 1. supervisor-level instruction 2. d = uimm * 8 table 272. instructions sorted by opcode (binary) (continued) mnemonic 012345678910111213141516171819202122232425262728293031formm nemonic RM0004 instruction set listings 1098/1176 table 273. powerpc instruction set legend uisa vea oea supervisor level optional form addx xo addx addcx xo addcx addex xo addex addi d addi addic d addic addic. d addic. addis d addis addmex xo addmex addzex xo addzex andx x andx andcx x andcx andi. d andi. andis. d andis. bx i bx bcx b bcx bcctrx xl bcctrx bclrx xl bclrx cmp x cmp cmpi d cmpi cmpl x cmpl cmpli d cmpli cntlzwx x cntlzwx crand xl crand crandc xl crandc creqv xl creqv crnand xl crnand crnor xl crnor cror xl cror crorc xl crorc crxor xl crxor dcba ? x dcba dcbf x dcbf dcbi ? x dcbi instruction set listings RM0004 1099/1176 dcbst x dcbst dcbt x dcbt dcbtst x dcbtst dcbz x dcbz divwx xo divwx divwux xo divwux eciwx ? x eciwx ecowx ? x ecowx eieio x eieio eqvx x eqvx extsbx x extsbx extshx x extshx fabsx x fabsx faddx a faddx faddsx a faddsx fcmpo x fcmpo fcmpu x fcmpu fctiwx x fctiwx fctiwzx x fctiwzx fdivx a fdivx fdivsx a fdivsx fmaddx a fmaddx fmaddsx a fmaddsx fmrx x fmrx fmsubx a fmsubx fmsubsx a fmsubsx fmulx a fmulx fmulsx a fmulsx fnabsx x fnabsx fnegx x fnegx fnmaddx a fnmaddx fnmaddsx a fnmaddsx fnmsubx a fnmsubx table 273. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form RM0004 instruction set listings 1100/1176 fnmsubsx a fnmsubsx fresx ? a fresx frspx x frspx frsqrtex ? a frsqrtex fselx ? a fselx fsqrtx ? a fsqrtx fsqrtsx ? a fsqrtsx fsubx a fsubx fsubsx a fsubsx icbi x icbi isync xl isync lbz d lbz lbzu d lbzu lbzux x lbzux lbzx x lbzx lfd d lfd lfdu d lfdu lfdux x lfdux lfdx x lfdx lfs d lfs lfsu d lfsu lfsux x lfsux lfsx x lfsx lha d lha lhau d lhau lhaux x lhaux lhax x lhax lhbrx x lhbrx lhz d lhz lhzu d lhzu lhzux x lhzux lhzx x lhzx lmw (1) d lmw (2) table 273. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form instruction set listings RM0004 1101/1176 lswi (1) x lswi (1) lswx (1) x lswx (1) lwarx x lwarx lwbrx x lwbrx lwz d lwz lwzu d lwzu lwzux x lwzux lwzx x lwzx mcrf xl mcrf mcrfs x mcrfs mcrxr x mcrxr mfcr x mfcr mffs x mffs mfmsr ? x mfmsr mfspr (3) ?? xfx mfspr (3) mfsr ? x mfsr mfsrin ? x mfsrin mftb xfx mftb mtcrf xfx mtcrf mtfsb0x x mtfsb0x mtfsb1x x mtfsb1x mtfsfx xfl mtfsfx mtfsfix x mtfsfix mtmsr ? x mtmsr mtspr (3) ?? xfx mtspr (4) mtsr ? x mtsr mtsrin ? x mtsrin mulhwx xo mulhwx mulhwux xo mulhwux mulli d mulli nandx x nandx negx xo negx norx x norx table 273. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form RM0004 instruction set listings 1102/1176 orx x orx orcx x orcx ori d ori oris d oris rfi ? xl rfi rlwimix m rlwimix rlwinmx m rlwinmx rlwnmx m rlwnmx sc ? sc sc slwx x slwx srawx x srawx srawix x srawix srwx x srwx stb d stb stbu d stbu stbux x stbux stbx x stbx stfd d stfd stfdu d stfdu stfdux x stfdux stfdx x stfdx stfiwx x stfiwx stfs d stfs stfsu d stfsu stfsux x stfsux stfsx x stfsx sth d sth sthbrx x sthbrx sthu d sthu sthux x sthux sthx x sthx stmw (1) d stmw (1) stswi (1) x stswi (1) table 273. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form instruction set listings RM0004 1103/1176 stswx (1) x stswx (1) stw d stw stwbrx x stwbrx stwcx. x stwcx. stwu d stwu stwux x stwux stwx x stwx subfx xo subfx subfcx xo subfcx subfex xo subfex subfic d subfic subfmex xo subfmex subfzex xo subfzex sync x sync tlbiax ?? x tlbiax tlbiex ?? x tlbiex tlbsync ?? x tlbsync tw x tw twi d twi xorx x xorx xori d xori xoris d xoris 1. load/store string or multiple. 2. load/store string or multiple. 3. supervisor and user level instruction. 4. supervisor and user level instruction. table 273. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form table 274. powerpc instruction set legend uisa vea oea supervisor level optional form add x xo add x addc x xo addc x adde x xo adde x add i d add i addic d addic RM0004 instruction set listings 1104/1176 addic. d addic. addis d addis addme x xo addme x addze x xo addze x and x x and x andc x x andc x andi. d andi. andis. d andis. b x i b x bc x b bc x bcctr x xl bcctr x bclr x xl bclr x cmp x cmp cmpi d cmpi cmpl x cmpl cmpli d cmpli cntlzw x x cntlzw x crand xl crand crandc xl crandc creqv xl creqv crnand xl crnand crnor xl crnor cror xl cror crorc xl crorc crxor xl crxor dcba ? x dcba dcbf x dcbf dcbi ? x dcbi dcbst x dcbst dcbt x dcbt dcbts t x dcbts t dcbz x dcbz divw x xo divw x divwu x xo divwu x eciwx ? x eciwx table 274. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form instruction set listings RM0004 1105/1176 ecowx ? x ecowx eieio x eieio eqv x x eqv x extsb x x extsb x extsh x x extsh x fabs x x fabs x fadd x a fadd x fadds x a fadds x fcmpo x fcmpo fcmpu x fcmpu fctiw x x fctiw x fctiwz x x fctiwz x fdiv x a fdiv x fdivs x a fdivs x fmadd x a fmadd x fmadds x a fmadds x fmr x x fmr x fmsub x a fmsub x fmsubs x a fmsubs x fmul x a fmul x fmuls x a fmuls x fnabs x x fnabs x fneg x x fneg x fnmadd x a fnmadd x fnmadds x a fnmadds x fnmsub x a fnmsub x fnmsubs x a fnmsubs x fres x ? a fres x frsp x x frsp x frsqrte x ? a frsqrte x fsel x ? a fsel x fsqrt x ? a fsqrt x fsqrts x ? a fsqrts x table 274. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form RM0004 instruction set listings 1106/1176 fsub x a fsub x fsubs x a fsubs x icbi x icbi isync xl isync l bz dl bz lbzu d lbzu lbzux x lbzux lbzx x lbzx lfd d lfd lfdu d lfdu lfdux x lfdux lfdx x lfdx lfs d lfs lfsu d lfsu lfsux x lfsux lfsx x lfsx lha d lha lhau d lhau lhaux x lhaux lhax x lhax lhbrx x lhbrx lhz d lhz lhzu d lhzu lhzux x lhzux lhzx x lhzx lmw 1 d lmw 1 lswi 1 x lswi 1 lswx 1 x lswx 1 lwarx x lwarx lwbrx x lwbrx lwz d lwz lwzu d lwzu lwzux x lwzux lwzx x lwzx mcrf xl mcrf table 274. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form instruction set listings RM0004 1107/1176 mcrfs x mcrfs mcrx r x mcrx r mfcr x mfcr mffs x mffs mfmsr ? x mfmsr mfspr 3 ?? xfx mfspr 1 mfsr ? x mfsr mfsrin ? x mfsrin mftb xfx mftb mtcrf xfx mtcrf mtfsb0 x x mtfsb0 x mtfsb1 x x mtfsb1 x mtfs f x xfl mtfs f x mtfsfi x x mtfsfi x mtmsr ? x mtmsr mtspr 1 ?? xfx mtspr 1 mtsr ? x mtsr mtsrin ? x mtsrin mulhw x xo mulhw x mulhwu x xo mulhwu x mulli d mulli mullw x xo mullw x nand x x nand x neg x xo neg x nor x x nor x or x x or x orc x x orc x ori d ori oris d oris rfi ? xl rfi rlwimi x m rlwimi x rlwinm x m rlwinm x rlwnm x m rlwnm x sc ? sc sc slw x x slw x table 274. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form RM0004 instruction set listings 1108/1176 sraw x x sraw x srawi x x srawi x srw x x srw x stb d stb stbu d stbu stbux x stbux stbx x stbx stfd d stfd stfdu d stfdu stfdux x stfdux stfdx x stfdx stfiwx x stfiwx stfs d stfs stfsu d stfsu stfsux x stfsux stfsx x stfsx sth d sth sthbrx x sthbrx sthu d sthu sthux x sthux sthx x sthx stmw 1 d stmw 1 stswi 1 x stswi 1 stswx 1 x stswx 1 stw d stw stwbrx x stwbrx stwcx. x stwcx. stwu d stwu stwux x stwux stwx x stwx subf x xo subf x subfc x xo subfc x subfe x xo subfe x subfic d subfic subfme x xo subfme x table 274. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form instruction set listings RM0004 1109/1176 subfze x xo subfze x sync x sync tlbia x ?? x tlbia x tlbie x ?? x tlbie x tlbsync ?? x tlbsync tw x tw tw i d tw i xor x x xor x xori d xori xoris d xoris table 274. powerpc instruction set legend (continued) uisa vea oea supervisor level optional form RM0004 simplified mnemonics for powerpc instructions 1110/1176 appendix b simplified mnemonics for powerpc instructions this chapter describes simplified mnemonics, which are provided for easier coding of assembly language programs. simplified mnemonics are defined for the most frequently used forms of branch conditional, compare, trap, rotate and shift, and certain other instructions defined by the powerpc? architecture and by implementations of and extensions to the powerpc architecture. chapter b.11: comprehensive list of simplified mnemonics on page 1133 ,? provides an alphabetical listing of simplified mnemonics. some assemblers may define additional simplified mnemonics not included here. the simplified mnemonics listed here should be supported by all compilers. b.1 overview simplified (or extended) mnemonics allow an assembly-language programmer to program using more intuitive mnemonics and symbols than the instructions and syntax defined by the instruction set architecture. for example, to co de the conditional call ?branch to an absolute target if cr4 specifies a gr eater than condition, setting the lr without simplified mnemonics, the programmer would write the branch conditional instruction, bc 12,17, target . the simplified mnemonic, branch if greater than, bgt cr4, target , incorporates the conditions. not only is it easier to reme mber the symbols than the numbers when programming, it is also easier to interpret simplified mnemonics when reading existing code. although the original powerpc architecture documents include a set of simplified mnemonics, these are not a formal part of the architecture, but rather a recommendation for assemblers that support the instruction set. many simplified mnemonics have been added to those originally included in the architecture documentation. some assemblers created their own, and others have been added to support extensions to the instruction set (for example, altivec instructions and book e auxiliary processing units (apus)). simp lified mnemonics have been added for new architecturally defined and new implementation-specific special-purpose registers (sprs). these simplified mnemonics are described only in a very general way. b.2 subtract simplified mnemonics this section describes simplified mn emonics for subtract instructions. b.2.1 subtract immediate there is no subtract immediate instruction, however, its effect is achieved by negating the immediate operand of an add immediate instruction, addi . simplified mnemonics include this negation, making the intent of the computation more clear. these are listed in table 275 . simplified mnemonics for powerpc instructions RM0004 1111/1176 b.2.2 subtract subtract from instructions subtract the second operand ( r a) from the third ( r b). the simplified mnemonics in ta b l e 2 7 6 use the common order in which the third operand is subtracted from the second. b.3 rotate and shift simplified mnemonics rotate and shift instructions provide powerful, general ways to manipulate register contents, but can be difficult to understand. simplif ied mnemonics are provided for the following operations: extract?select a field of n bits starting at bit position b in the source register; left or right justify this field in the target register; clear all other bits of the target register. insert?select a left- or right-justified field of n bits in the source register; insert this field starting at bit position b of the target register; leave other bits of the target register unchanged. rotate?rotate the contents of a register right or left n bits without masking. shift?shift the contents of a register right or left n bits, clearing vacated bits (logical shift). clear?clear the leftmost or rightmost n bits of a register. clear left and shift le ft?clear the leftmost b bits of a register, then shift the register left by n bits. this operation can be used to scale a (known non-negative) array index by the width of an element. b.3.1 operations on words the simplified mnemonics in ta bl e 2 7 7 can be coded with a dot ( . ) suffix to cause the rc bit to be set in the underlying instruction. table 275. subtract immediate simplified mnemonics simplified mnemonic standard mnemonic subi r d ,r a , value addi r d ,r a , ?value subis r d ,r a , value addis r d ,r a , ?value subic r d ,r a , value addic r d ,r a , ?value subic. r d ,r a , value addic. r d ,r a , ?value table 276. subtract simplified mnemonics simplified mnemonic standard mnemonic (1) 1. r d ,r b ,r a is not the standard order for the operands. the order of r b and r a is reversed to show the equivalent behavior of the simplified mnemonic. sub [ o ][ . ] r d ,r a ,r b subf [ o ][ . ] r d ,r b ,r a subc [ o ][ . ] r d ,r a ,r b subfc [ o ][ . ] r d ,r b ,r a RM0004 simplified mnemonics for powerpc instructions 1112/1176 examples using word mnemonics follow: 1. extract the sign bit (bit 0) of r s and place the result right-justified into r a. extrwi r a ,r s ,1,0 equivalent to rlwinm r a ,r s ,1,31,31 2. insert the bit extracted in (1) into the sign bit (bit 0) of r b. insrwi r b ,r a ,1,0 equivalent to rlwimi r b ,r a ,31,0,0 3. shift the contents of r a left 8 bits. slwi r a ,r a ,8 equivalent to rlwinm r a ,r a ,8,0,23 4. clear the high-order 16 bits of r s and place the result into r a. clrlwi r a ,r s ,16 equivalent to rlwinm r a ,r s ,0,16,31 b.4 branch instruction simplified mnemonics branch conditional instructions can be coded with the operations, a condition to be tested, and a prediction, as part of the mnemonic rather than as numeric bo and bi operands. table 278 shows the four general types of branch instructions. simplified mnemonics are defined only for branch instructions that include bo and bi operands; there is no need to simplify unconditional branch mnemonics. table 277. word rotate and shift simplified mnemonics operation simplified mnemonic equivalent to: extract and left justify word immediate extlwi r a ,r s , n , b ( n > 0) rlwinm r a ,r s , b ,0, n ? 1 extract and right justify word immediate extrwi r a ,r s , n , b ( n > 0) rlwinm r a ,r s , b + n , 32 ? n ,31 insert from left word immediate inslwi r a ,r s , n , b ( n > 0) rlwimi r a ,r s , 32 ? b , b , ( b + n ) ? 1 insert from right word immediate insrwi r a ,r s , n , b ( n > 0) rlwimi r a ,r s , 32 ? ( b + n ) , b , ( b + n ) ? 1 rotate left word immediate rotlwi r a ,r s , n rlwinm r a ,r s , n ,0,31 rotate right word immediate rotrwi r a ,r s , n rlwinm r a ,r s , 32 ? n ,0,31 rotate word left rotlw r a ,r s ,r b rlwnm r a ,r s ,r b ,0,31 shift left word immediate slwi r a ,r s , n ( n < 32) rlwinm r a ,r s , n ,0, 31 ? n shift right word immediate srwi r a ,r s , n ( n < 32) rlwinm r a ,r s , 32 ? n , n ,31 clear left word immediate clrlwi r a ,r s , n ( n < 32) rlwinm r a ,r s ,0, n ,31 clear right word immediate clrrwi r a ,r s , n ( n < 32) rlwinm r a ,r s ,0,0, 31 ? n clear left and shift left word immediate clrlslwi r a ,r s , b , n ( n b 31) rlwinm r a ,r s , n , b ? n , 31 ? n table 278. branch instructions instruction name mnemonic syntax branch b (ba bl bla) target_addr branch conditional bc (bca bcl bcla) bo , bi,target_addr branch conditional to link register bclr (bclr l ) bo , bi branch conditional to count register bcctr (bcctr l ) bo , bi simplified mnemonics for powerpc instructions RM0004 1113/1176 the bo and bi operands correspond to two fields in the instruction opcode, as figure below shows for branch conditional ( bc , bca , bcl , and bcla ) instructions. the bo operand specifies branch operations that involve decrementing ctr. it is also used to determine whether testing a cr bit causes a branch to occur if the condition is true or false. the bi operand identifies a cr bit to test (whether a comparison is less than or greater than, for example). the simplified mnemonics avoid the need to memorize the numerical values for bo and bi. for example, bc 16,0, target is a conditional branch that, as a bo value of 16 (0b1_0000) indicates, decrements ctr, then branches if the decremented ctr is not zero. the operation specified by bo is abbreviated as d (for decrement) and nz (for not zero), which replace the c in the original mnemonic; so the simplified mnemonic for bc becomes bdnz . the branch does not depend on a condition in the cr, so bi can be eliminated, reducing the expression to bdnz target . in addition to ctr operations, the bo operand provides an optional prediction bit and a true or false indicator can be added. for example, if the previous instruction should branch only on an equal condition in cr0 , the instruction becomes bc 8,2, target . to incorporate a true condition, the bo value becomes 8 (as shown in ta b l e 2 8 0 ); the cr0 equal field is indicated by a bi value of 2 (as shown in ta bl e 2 8 1 ). incorporating the branch-if-true condition adds a ? t ? to the simplified mnemonic, bdnzt. the equal condition, that is specified by a bi value of 2 (indicating the eq bit in cr0) is replaced by the eq symbol. using the simplified mnemonic and the eq operand, the expression becomes bdnzt eq, target . this example tests cr0[eq]; however, to test the equal condition in cr5 (cr bit 22), the expression becomes bc 8,22, target . the bi operand of 22 indicates cr[22] (cr5[2], or bi field 0b10110), as shown in ta bl e 2 8 1 . this can be expressed as the simplified mnemonic. bdnzt 4 * cr5 + eq, target . the notation, 4 * cr5 + eq may at first seem awkward, but it eliminates computing the value of the cr bit. it can be seen that (4 * 5) + 2 = 22. note that although 32-bit registers in book e processors are numbered 32?63, only values 0?31 are valid (or possible) for bi operands. as shown in ta b l e 2 8 2 , a book e?compliant processor automatically translates the bit values; specifying a bi value of 22 selects bit 55 on a book e processor, or cr5[2] = cr5[eq]. 0 5 6 1011 1516 293031 001000 bo bi bd aalk RM0004 simplified mnemonics for powerpc instructions 1114/1176 b.4.1 key facts about si mplified branch mnemonics the following key points are helpful in understanding how to use simplified branch mnemonics: all simplified branch mnemonics eliminate the bo operand, so if any operand is present in a branch simplified mnemonic, it is the bi operand (or a reduced form of it). if the cr is not involved in the branch, the bi operand can be deleted. if the cr is involved in the branch, the bi operand can be treated in the following ways: ? it can be specified as a numeric value, just as it is in the architecturally defined instruction, or it can be indicated with an easier to remember formula, 4 * cr n + [test bit symbol], where n indicates the cr field number. ? the condition of the test bit (eq, lt, gt, and so) can be incorporated into the mnemonic, leaving the need for an operand that defines only the cr field. - if the test bit is in cr0, no operand is needed. - if the test bit is in cr1?cr7, the bi operand can be replaced with a cr s operand (that is, cr1 , cr2 , cr3 , and so forth). b.4.2 eliminating the bo operand the 5-bit bo field, shown below, encodes the following operations in conditional branch instructions: decrement count register (ctr) ? and test if result is equal to zero ? and test if result is not equal to zero test condition register (cr) ? test condition true ? test condition false branch prediction (taken, fall through). if the prediction bit, y , is needed, it is signified by appending a plus or minus sign as described in chapter b.4.3: incorporating the bo branch prediction on page 1116 .? simplified mnemonics for powerpc instructions RM0004 1115/1176 bo bits can be interpreted individually as described in ta bl e 2 7 9 . thus, a bo encoding of 10100 (decimal 20) means ignore the cr bit comparison and do not decrement the ctr?in other words, branch unconditionally. encodings for the bo operand are shown in ta b l e 2 8 0 . a z bit indicates that the bit is ignored. however, these bits should be cleared, as they may be assigned a meaning in a future version of the architecture. as shown in ta b l e 2 8 0 , the ? c ? in the standard mnemonic is replaced with the operations otherwise specified in the bo field, ( d for decrement, z for zero, nz for non-zero, t for true, and f for false). 01234 table 279. bo bit encodings bo bit description 0 if set, ignore the cr bit comparison. 1 if set, the cr bit comparison is against true, if not set the cr bit comparison is against false 2 if set, the ctr is not decremented. 3 if bo[2] is set, this bit determines whether the ctr comparison is for equal to zero or not equal to zero. 4 the y bit. if set, reverses the stat ic prediction. use of this bit is optional and independent from the interpretation of other bo bits. because simplified branch mnemonics eliminate the bo operand, this bit is programmed by adding a plus or minus sign to the simplified mnemonic, as described in chapter b.4.3 .? table 280. bo operand encodings bo field value (1) (decimal) description symbol 0000 y 0 decrement the ctr, then branch if the decremented ctr 0; condition is false. dnzf 0001 y 2 decrement the ctr, then br anch if the decremented ctr = 0; condition is false. dzf 001 zy 4 branch if the condition is false. (2) note that ?false? and ?four? both start with ?f?. f 0100 y 8 decrement the ctr, then branch if the decremented ctr 0; condition is true. dnzt 0101 y 10 decrement the ctr, then br anch if the decremented ctr = 0; condition is true. dzt 011 z (3) y 12 branch if the condition is true. 2 note that ?true? and ?twelve? both start with ?t?. t 1 z 00 y (4) 16 decrement the ctr, then br anch if the decremented ctr 0. dnz (5) 1 z 01 y 4 18 decrement the ctr, then bran ch if the decremented ctr = 0. dz 5 1 z 1 zz 4 20 branch always. ? 1. assumes y = z = 0. chapter b.4.3: incorporating the bo branch prediction ,? describes how to use simplified mnemonics to program the y bit for static prediction. 2. instructions for which b0 is 12 (branc h if condition true) or 4 (branch if condi tion false) do not depend on the ctr value an d can be alternately coded by incorpor ating the condition specified by the bi field, as described in chapter b.4.6 .? 3. a z bit indicates a bit that is ignored. however, these bits should be cleared, as they may be assigned a meaning in a future version of the architecture. RM0004 simplified mnemonics for powerpc instructions 1116/1176 b.4.3 incorporating the bo branch prediction as shown in ta b l e 2 8 0 , the low-order bit ( y bit) of the bo field provides a hint about whether the branch is likely to be taken (static branch prediction). assemblers should clear this bit unless otherwise directed. this default action indicates the following: a branch conditional with a negative displacement field is predicted to be taken. a branch conditional with a non-negative displacement field is predicted not to be taken (fall through). a branch conditional to an address in the lr or ctr is predicted not to be taken (fall through). if the likely outcome (branch or fall through) of a given branch conditional instruction is known, a suffix can be added to the mnemonic that tells the assembler how to set the y bit. that is, ?+? indicates that the branch is to be taken and ??? indicates that the branch is not to be taken. this suffix can be added to any branch conditional mnemonic, standard or simplified. for relative and absolute branches ( bc [ l ][ a ]), the setting of the y bit depends on whether the displacement field is negative or non-negative. for negative displacement fields, coding the suffix ?+? causes the bit to be cleared, and coding the suffix ??? causes the bit to be set. for non-negative displacement fields, coding the su ffix ?+? causes the bit to be set, and coding the suffix ??? causes the bit to be cleared. for branches to an address in the lr or ctr ( bclr [ l ] or bcctr [ l ]), coding the suffix ?+? causes the y bit to be set, and coding the suff ix ??? causes the bit to be cleared. examples of branch prediction follow: 1. branch if cr0 reflects less than condition, specifying that the branch should be predicted as taken. blt+ target 2. same as (1), but target address is in the lr and the branch should be predicted as not taken. bltlr ? 4. simplified mnemonics for branch instruct ions that do not test cr bits (bo = 16 , 18, and 20) should specify only a target. otherwise a programming error may occur. 5. notice that these instructions do not use the branch if condition true or false operations . for that reason, simplified mnemonics for these should not specify a bi operand. simplified mnemonics for powerpc instructions RM0004 1117/1176 b.4.4 the bi opera nd?cr bit and field representations with standard branch mnemonics, the bi operand is used when it is necessary to test a cr bit, as shown in the example in chapter b.4: branch instruct ion simplified mnemonics .? with simplified mnemonics, the bi operand is handled differently depending on whether the simplified mnemonic incorporates a cr condition to te st, as follows: some branch simplified mnemonics incorporate only the bo operand. these simplified mnemonics can use the architecturally defined bi operand to specify the cr bit, as follows: ? the bi operand can be presented exactly as it is with standard mnemonics?as a decimal number, 0?31. ? symbols can be used to replace the decimal operand, as shown in the example in chapter b.4: branch instruction simplified mnemonics ,? where bdnzt 4 * cr5 + eq, target could be used instead of bdnzt 22, target . this is described in specifying a cr bit on page 1118 .? the simplified mnemonics in chapter b.4.5: simplified mnemonics that incorporate the bo operand ,? use one of these two methods to specify a cr bit. ? additional simplified mnemonics are specified that incorporate cr conditions that would otherwise be specified by the bi operand, so the bi operand is replaced by the cr s operand to specify the cr field, cr0?cr7. see bi operand instruction encoding on page 1117 .? these mnemonics are described in chapter b.4.6: simplified mnemonics that incorporate cr conditions (eliminates bo and replaces bi with crs) .? bi operand instruction encoding the entire 5-bit bi field, shown in figure 180 , represents the bit number for the cr bit to be tested. for standard branch mnemonics and for branch simplified mnemonics that do not incorporate a cr condition, the bi operand provides all 5 bits. for simplified branch mnemonics described in chapter b.4.6 ,? the bi operand is replaced by a cr s operand. to understand this, it is useful to view the bi operand as comprised of two parts. as figure 180 shows, bi[0?2] indicates the cr field and bi[3?4] represents the condition to test. RM0004 simplified mnemonics for powerpc instructions 1118/1176 figure 180. bi field (bits 11?14 of the instruction encoding) integer record-form instructions update cr0 as described in ta bl e 2 8 1 . specifying a cr bit note that the aim version the powerpc architecture numbers cr bits 0?31 and book e numbers them 32?63. however, no adjustment is necessary to the code; in book e devices, 32 is automatically added to the bi value, as shown in ta b l e 2 8 1 and table 282 . some simplified mnemonics incorporate only the bo field (as described chapter b.4.2: eliminating the bo operand ? ). if one of these simplified mnemonics is used and the cr must be accessed, the bi operand can be specified either as a numeric value or by using the symbols in table 282 . compare word instructions (described in chapter b.5: compare word simplified mnemonics ? ), move to cr instructions, and others can also modify cr fields, so cr0 and cr1 may hold values that do not adhere to the meanings described in ta b l e 2 8 1 . cr logical instructions, described in chapter b.6: condition register logical simplified mnemonics ,? can update individual cr bits. table 281. cr0 and cr1 fields as updated by integer instructions cr n bit cr bits bi description aim book e 0?2 3?4 cr0[0] 0 32 000 00 negative (lt)?set when the result is negative. cr0[1] 1 33 000 01 positive (gt)?set when t he result is positive (and not zero). cr0[2] 2 34 000 10 zero (eq)?set when the result is zero. cr0[3] 3 35 000 11 summary overflow (so). copy of xer[so] at the instruction?s completion. 01234 bi[0?2] specifies cr field, cr0?cr7. simplified mnem onics based on cr conditions but not ctr values?bo = 12 (branch if true) and bo = 4 branch if false) specified by a separate, reduced bi operand ( cr s) incorporated into the simplified mnemonic. standard branch mnemonics and simplified mnem onics based on ctr values the bi operand specifies the entire 5-bit field. if cr0 is used, the bit can be identified by lt, gt, eq, or so. if cr1?cr7 are used, the form 4 * cr s + lt|gt|eq|so can be used. bi opcode field bi[3?4] specifies one of the 4 bits in a cr field. (lt, gt, eq,so) simplified mnemonics for powerpc instructions RM0004 1119/1176 to provide simplified mnemonics for every possible combination of bo and bi (that is, including bits that identified the cr field) would require 2 10 = 1024 mnemonics, most of that would be only marginally useful. the abbreviated set in chapter b.4.5: simplified mnemonics that incorporate the bo operand ,? covers useful cases. unusual cases can be coded using a standard branch conditional syntax. the crs operand the cr s symbols are shown in ta bl e 2 8 3 . note that either the symbol or the operand value can be used in the syntax used with the simplified mnemonic. table 282. bi operand settings for cr fields for branch comparisons cr n bit bit expression cr bits bi description aim (bi operand) book e 0?2 3?4 cr n [0] 4 * cr0 + lt (or lt ) 4 * cr1 + lt 4 * cr2 + lt 4 * cr3+ lt 4 * cr4 + lt 4 * cr5 + lt 4 * cr6 + lt 4 * cr7 + lt 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 000 001 010 011 100 101 110 111 00 less than (lt). for integer compare instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). cr n [1] 4 * cr0 + gt (or gt ) 4 * cr1 + gt 4 * cr2 + gt 4 * cr3+ gt 4 * cr4 + gt 4 * cr5 + gt 4 * cr6 + gt 4 * cr7 + gt 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 000 001 010 011 100 101 110 111 01 greater than (gt). for integer compare instructions: ra > simm or r b (signed comparison) or r a > uimm or r b (unsigned comparison). cr n [2] 4 * cr0 + eq (or eq ) 4 * cr1 + eq 4 * cr2 + eq 4 * cr3+ eq 4 * cr4 + eq 4 * cr5 + eq 4 * cr6 + eq 4 * cr7 + eq 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 000 001 010 011 100 101 110 111 10 equal (eq). for integer compare instructions: r a = simm, uimm, or r b. cr n [3] 4 * cr0 + so (or so ) 4 * cr1 + so 4* cr2 + so 4* cr3 + so 4* cr4 + so 4* cr5 + so 4* cr6 + so 4* cr7 + so 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 000 001 010 011 100 101 110 111 11 summary overflow (so). for integer compare instructions, this is a copy of xer[so] at instruction completion. RM0004 simplified mnemonics for powerpc instructions 1120/1176 to identify a cr bit, an expression in whic h a cr field symbol is multiplied by 4 and then added to a bit-number-within-cr-field symbol can be used, (for example, cr0 * 4 + eq ). b.4.5 simplified mnemonics t hat incorporate the bo operand the mnemonics in table 284 allow common bo operand encodings to be specified as part of the mnemonic, along with the absolute address (aa) and set link register bits (lk). there are no simplified mnemonics for relative and absolute unconditional branches. for these, the basic mnemonics b , ba , bl , and bla are used. table 284 shows the syntax for basic simplified branch mnemonics table 283. cr field identification symbols symbol bi[0?2] cr bits cr0 (default, can be eliminated from syntax) 000 32?35 cr1 001 36?39 cr2 010 40?43 cr3 011 44?47 cr4 100 48?51 cr5 101 52?55 cr6 110 56?59 cr7 111 60?63 table 284. branch simplified mnemonics branch semantics lr update not enabled lr update enabled bc bca bclr bcctr bcl bcla bclrl bcctrl branch unconditionally (1) ?? blr bctr ?? blrl bctrl branch if condition true bt bta btlr btctr btl btla btlrl btctrl branch if condition false bf bfa bflr bfctr bfl bfla bflrl bfctrl decrement ctr, branch if ctr 0 1 bdnz bdnza bdnzlr ? bdnzl bdnzla bdnzlrl ? decrement ctr, branch if ctr 0 and condition true bdnzt bdnzta bdnztlr ? bdnztl bdnztla bdnztlrl ? decrement ctr, branch if ctr 0 and condition false bdnzf bdnzfa bdnzflr ? bdnzfl bdnzfla bdnzflrl ? decrement ctr, branch if ctr = 0 1 bdz bdza bdzlr ? bdzl bdzla bdzlrl ? decrement ctr, branch if ctr = 0 and condition true bdzt bdzta bdztlr ? bdztl bdztla bdztlrl ? decrement ctr, branch if ctr = 0 and condition false bdzf bdzfa bdzflr ? bdzfl bdzfla bdzflrl ? 1. simplified mnemonics for branch instru ctions that do not test cr bits shou ld specify only a target. otherwise a programming error may occur. simplified mnemonics for powerpc instructions RM0004 1121/1176 the simplified mnemonics in ta bl e 2 8 4 that test a condition require a corresponding cr bit as the first operand (as examples 2?5 below show). the symbols in ta b l e 2 8 3 can be substituted for numeric values. examples that eliminate the bo operand the simplified mnemonics in ta bl e 2 8 4 are used in the following examples: 1. decrement ctr and branch if it is still nonz ero (closure of a loop controlled by a count loaded into ctr) (note that no cr bits are tested). bdnz target equivalent to bc 16,0, target because this instruction does not test a cr bit, the simplified m nemonic should specify only a target operand. specifying a cr (for example, bdnz 0, target or bdnz cr0, target ) may be considered a programming error. subsequent examples test conditions). 2. same as (1) but branch only if ctr is nonzero and equal condition in cr0. bdnzt eq, target equivalent to bc 8,2, target other equivalents include bdnzt 2, target or the unlikely bdnzt 4*cr0+eq, target 3. same as (2), but equ al condition is in cr5. bdnzt 4 * cr5 + eq, target equivalent to bc 8,22, target bdnzt 22, target would also work 4. branch if bit 59 of cr is false. bf 27, target equivalent to bc 4,27, target bf 4*cr6+so, target would also work 5. same as (4), but set the link regist er. this is a form of conditional call. bfl 27, target equivalent to bcl 4,27, target table 286 lists simplified mnemonics and syntax for bc and bca without lr updating. table 285. branch instructions instruction standard mnemonic syntax simplified mnemonic syntax branch b (ba bl bla) target_addr n/a, syntax does not include bo branch conditional bc (bca bcl bcla) bo , bi,target_addr b x (1) ( b x a b x l b x la )bi (2) target_addr branch conditional to link register bclr (bclr l )bo , bi b x lr (b x lr l )bi branch conditional to count register bcctr (bcctr l )bo , bi b x ctr (b x ctr l )bi 1. x stands for one of the symbols in table 280 , where applicable. 2. bi can be a numeric value or an expression as shown in table 283 . table 286. simplified mnemonics for bc and bca without lr update branch semantics bc simplified mnemonic bca simplified mnemonic branch unconditionally ? ? ? ? branch if condition true (1) bc 12,bi, target bt bi, target bca 12,bi, target bta bi, target branch if condition false 1 bc 4,bi, target bf bi, target bca 4,bi, target bfa bi, target decrement ctr, branch if ctr 0 bc 16,0, target bdnz target (2) bca 16,0, target bdnza target 2 RM0004 simplified mnemonics for powerpc instructions 1122/1176 table 287 lists simplified mnemonics and syntax for bclr and bcctr without lr updating. table 288 provides simplified mnemonics and syntax for bcl and bcla . decrement ctr, branch if ctr 0 and condition true bc 8,bi, target bdnzt bi, target bca 8,bi, target bdnzta bi, target decrement ctr, branch if ctr 0 and condition false bc 0,bi, target bdnzf bi, target bca 0,bi, target bdnzfa bi, target decrement ctr, branch if ctr = 0 bc 18,0, target bdz target 2 bca 18,0, target bdza target 2 decrement ctr, branch if ctr = 0 and condition true bc 10,bi, target bdzt bi, target bca 10,bi, target bdzta bi, target decrement ctr, branch if ctr = 0 and condition false bc 2,bi, target bdzf bi, target bca 2,bi, target bdzfa bi, target 1. instructions for which b0 is either 12 (branch if conditi on true) or 4 (branch if condition false) do not depend on the ctr value and can be alternately coded by incorporating the condi tion specified by the bi field, as described in chapter b.4.6: simplified mnemonics that inco rporate cr conditions (eliminates bo and replaces bi with crs) .? 2. simplified mnemonics for branch instru ctions that do not test cr bits shou ld specify only a target. otherwise a programming error may occur. table 286. simplified mnemonics for bc and bca without lr update (continued) branch semantics bc simplified mnemonic bca simplified mnemonic table 287. simplified mnemonics for bclr and bcctr without lr update branch semantics bclr simplified mnemonic bcctr simplified mnemonic branch unconditionally bclr 20,0 blr (1) bcctr 20,0 bctr 1 branch if condition true (2) bclr 12,bi btlr bi bcctr 12,bi btctr bi branch if condition false 2 bclr 4,bi bflr bi bcctr 4,bi bfctr bi decrement ctr, branch if ctr 0 bclr 16,bi bdnzlr bi ?? decrement ctr, branch if ctr 0 and condition true bclr 8,bi bdnztlr bi ?? decrement ctr, branch if ctr 0 and condition false bclr 0,bi bdnzflr bi ?? decrement ctr, branch if ctr = 0 bclr 18,0 bdzlr 1 ?? decrement ctr, branch if ctr = 0 and condition true bclr 8,bi bdnztlr bi ?? decrement ctr, branch if ctr = 0 and condition false bclr 2,bi bdzflr bi ?? 1. simplified mnemonics for branch instru ctions that do not test a cr bit shoul d not specify one; a programming error may occur. 2. instructions for which b0 is 12 (branc h if condition true) or 4 (b ranch if condition false) do not depend on a ctr value and can be alternately coded by incorporating t he condition specified by the bi field. see chapter b.4.6: simplified mnemonics that incorporate cr conditions (eliminat es bo and replaces bi with crs) .? table 288. simplified mnemonics for bcl and bcla with lr update branch semantics bcl simplified mnemonic bcla simplified mnemonic branch unconditionally ? ? ? ? branch if condition true (1) bcl 12,bi, target btl bi, target bcla 12,bi, target btla bi, target simplified mnemonics for powerpc instructions RM0004 1123/1176 table 289 provides simplified mnemonics and syntax for bclrl and bcctrl with lr updating. b.4.6 simplified mnemonics that i ncorporate cr conditi ons (eliminates bo and replaces bi with crs) the mnemonics in table 292 are variations of the branch-if-condition-true (bo = 12) and branch-if-condition-false (bo = 4) encodings. be cause these instructions do not depend on the ctr, the true/false conditions specified by bo can be combined with the cr test bit specified by bi to create a different set of simplified mnemonics that eliminates the bo operand and the portion of the bi operand (bi[3?4]) that specifies one of the four possible branch if condition false 1 bcl 4,bi, target bfl bi, target bcla 4,bi, target bfla bi, target decrement ctr, branch if ctr 0 bcl 16,0, target bdnzl target (2) bcla 16,0, target bdnzla target 2 decrement ctr, branch if ctr 0 and condition true bcl 8,0, target bdnztl bi, target bcla 8,bi, target bdnztla bi, target decrement ctr, branch if ctr 0 and condition false bcl 0,bi, target bdnzfl bi, target bcla 0,bi, target bdnzfla bi, target decrement ctr, branch if ctr = 0 bcl 18,bi, target bdzl target 2 bcla 18,bi, target bdzla target 2 decrement ctr, branch if ctr = 0 and condition true bcl 10,bi, target bdztl bi, target bcla 10,bi, target bdztla bi, target decrement ctr, branch if ctr = 0 and condition false bcl 2,bi, target bdzfl bi, target bcla 2,bi, target bdzfla bi, target 1. instructions for which b0 is either 12 (branch if conditi on true) or 4 (branch if condition false) do not depend on the ctr value and can be alternately coded by incorporating the condition specified by the bi field. see chapter b.4.6: simplified mnemonics that incorporate cr conditions (eliminates bo and repl aces bi with crs) .? 2. simplified mnemonics for branch instruct ions that do not test cr bits should specify only a target. a programming error may occur. table 288. simplified mnemonics for bcl and bcla with lr update (continued) branch semantics bcl simplified mnemonic bcla simplified mnemonic table 289. simplified mnemonics for bclrl and bcctrl with lr update branch semantics bclrl simplified mnemonic bcctrl simplified mnemonic branch unconditionally bclrl 20,0 blrl (1) bcctrl 20,0 bctrl 1 branch if condition true bclrl 12,bi btlrl bi bcctrl 12,bi btctrl bi branch if condition false bclrl 4,bi bflrl bi bcctrl 4,bi bfctrl bi decrement ctr, branch if ctr 0 bclrl 16,0 bdnzlrl 1 ?? decrement ctr, branch if ctr 0, condition true bclrl 8,bi bdnztlrl bi ?? decrement ctr, branch if ctr 0, condition false bclrl 0,bi bdnzflrl bi ?? decrement ctr, branch if ctr = 0 bclrl 18,0 bdzlrl 1 ?? decrement ctr, branch if ctr = 0, condition true bclrl 10, bi bdztlrl bi ?? decrement ctr, branch if ctr = 0, condition false bclrl 2,bi bdzflrl bi ?? 1. simplified mnemonics for branch instru ctions that do not test a cr bit shoul d not specify one. a programming error may occur. RM0004 simplified mnemonics for powerpc instructions 1124/1176 test bits. however, the simplified mnemonic cannot specify in which of the eight cr fields the test bit falls, so the bi operand is replaced by a cr s operand. the standard codes shown in ta bl e 2 9 0 are used for the most common combinations of branch conditions. note that for ease of programming, these codes include synonyms; for example, less than or equal ( le ) and not greater than ( ng ) achieve the same result. note: a cr field symbol, cr0 ? cr7 , is used as the first operand after the simplified mnemonic. if cr0 is used, no cr s is necessary. table 291 shows the syntax for simplified branch mnemonics that incorporate cr conditions. here, cr s replaces a bi operand to specify only a cr field (because the specific cr bit within the field is now part of the simplif ied mnemonic. note that the default is cr0; if no cr s is specified, cr0 is used. table 292 shows the simplified branch mnemonics incorporating conditions. table 290. standard coding for branch conditions code description equivalent bit tested lt less than ? lt le less than or equal (equivalent to ng ) ng gt eq equal ? eq ge greater than or equal (equivalent to nl ) nl lt gt greater than ? gt nl not less than (equivalent to ge ) ge lt ne not equal ? eq ng not greater than (equivalent to le ) le gt so summary overflow ? so ns not summary overflow ? so table 291. branch instructions and simplified mnemonics that incorporate cr conditions instruction standard mnemonic syntax simplified mnemonic syntax branch b (ba bl bla) target_addr ? branch conditional bc (bca bcl bcla) bo , bi,target_addr b x (1) ( b x a b x l b x la ) cr s (2) ,target_addr branch conditional to link register bclr (bclr l ) bo , bi b x lr (b x lr l ) cr s branch conditional to count register bcctr (bcctr l ) bo , bi b x ctr (b x ctr l ) cr s 1. x stands for one of the symbols in table 290 , where applicable. 2. bi can be a numeric value or an expression as shown in table 283 . simplified mnemonics for powerpc instructions RM0004 1125/1176 instructions using the mnemonics in ta bl e 2 9 2 indicate the condition bit, but not the cr field. if no field is specified, cr0 is used. the cr field symbols defined in ta bl e 2 8 3 ( cr0 ? cr7 ) are used for this operand, as shown in examples 2?4 below. branch simplified mnemonics that incorporate cr conditions: examples the following examples use the simplified mnemonics shown in ta bl e 2 9 2 : 1. branch if cr0 reflects not-equal condition. bne target equivalent to bc 4,2, target 2. same as (1) but condition is in cr3. bne cr3, target equivalent to bc 4,14, target 3. branch to an absolute target if cr4 specifies greater than condition, setting the lr. this is a form of conditional call. bgtla cr4, target equivalent to bcla 12,17, target 4. same as (3), but target address is in the ctr. bgtctrl cr4 equivalent to bcctrl 12,17 branch simplified mnemonics that incorporate cr conditions: listings table 293 shows simplified branch mnemonics and syntax for bc and bca without lr updating. table 292. simplified mnemonics with comparison conditions branch semantics lr update not enabled lr update enabled bc bca bclr bcctr bcl bcla bclrl bcctrl branch if less than blt blta bltlr bltctr bltl bltla bltlrl bltctrl branch if less than or equal ble blea blelr blectr blel blela blelrl blectrl branch if equal beq beqa beqlr beqctr beql beqla beqlrl beqctrl branch if greater than or equal bge bgea bgelr bgectr bgel bgela bgelrl bgectrl branch if greater than bgt bgta bgtlr bgtctr bgtl bgtla bgtlrl bgtctrl branch if not less than bnl bnla bnllr bnlctr bnll bnlla bnllrl bnlctrl branch if not equal bne bnea bnelr bnectr bnel bnela bnelrl bnectrl branch if not greater than bng bnga bnglr bngctr bngl bngla bnglrl bngctrl branch if summary overflow bso bsoa bsolr bsoctr bsol bsola bsolrl bsoctrl branch if not summary overflow bns bnsa bnslr bnsctr bnsl bnsla bnslrl bnsctrl branch if unordered bun buna bunlr bunctr bunl bunla bunlrl bunctrl branch if not unordered bnu bnua bnulr bnuctr bnul bnula bnulrl bnuctrl RM0004 simplified mnemonics for powerpc instructions 1126/1176 table 294 shows simplified branch mnemonics and syntax for bclr and bcctr without lr updating. table 293. simplified mnemonics for bc and bca without comparison conditions or lr update branch semantics bc simplified mnemonic bca simplified mnemonic branch if less than bc 12, bi (1) , target blt cr s target bca 12, bi 1 , target blta cr s target branch if less than or equal bc 4, bi (2) , target ble cr s target bca 4, bi 2 , target blea cr s target branch if not greater than bng cr s target bnga cr s target branch if equal bc 12, bi (3) , target beq cr s target bca 12, bi 3 , target beqa cr s target branch if greater than or equal bc 4, bi 1 , target bge cr s target bca 4, bi 1 , target bgea cr s target branch if not less than bnl cr s target bnla cr s target branch if greater than bc 12, bi 2 , target bgt cr s target bca 12, bi 2 , target bgta cr s target branch if not equal bc 4, bi 3 , target bne cr s target bca 4, bi 3 , target bnea cr s target branch if summary overflow bc 12, bi (4) , target bso cr s target bca 12, bi 4 , target bsoa cr s target branch if unordered bun cr s target buna cr s target branch if not summary overflow bc 4, bi 4 , target bns cr s target bca 4, bi 4 , target bnsa cr s target branch if not unordered bnu cr s target bnua cr s target 1. the value in the bi operand selects cr n [0], the lt bit. 2. the value in the bi operand selects cr n [1], the gt bit. 3. the value in the bi operand selects cr n [2], the eq bit. 4. the value in the bi operand selects cr n [3], the so bit. table 294. simplified mnemonics for bclr and bcctr without comparison conditions or lr update branch semantics bclr simplified mnemonic bcctr simplified mnemonic branch if less than bclr 12, bi (1) , target bltlr cr s target bcctr 12, bi 1 , target bltctr cr s target branch if less than or equal bclr 4, bi (2) , target blelr cr s target bcctr 4, bi 2 , target blectr cr s target branch if not greater than bnglr cr s target bngctr cr s target branch if equal bclr 12, bi (3) , target beqlr cr s target bcctr 12, bi 3 , target beqctr cr s target branch if greater than or equal bclr 4, bi 1 , target bgelr cr s target bcctr 4, bi 1 , target bgectr cr s target branch if not less than bnllr cr s target bnlctr cr s target branch if greater than bclr 12, bi 2 , target bgtlr cr s target bcctr 12, bi 2 , target bgtctr cr s target branch if not equal bclr 4, bi 3 , target bnelr cr s target bcctr 4, bi 3 , target bnectr cr s target branch if summary overflow bclr 12, bi (4) , target bsolr cr s target bcctr 12, bi 4 , target bsoctr cr s target branch if not summary overflow bclr 4, bi 4 , target bnslr cr s target bcctr 4, bi 4 , target bnsctr cr s target 1. the value in the bi operand selects cr n [0], the lt bit. 2. the value in the bi operand selects cr n [1], the gt bit. 3. the value in the bi operand selects cr n [2], the eq bit. 4. the value in the bi operand selects cr n [3], the so bit. simplified mnemonics for powerpc instructions RM0004 1127/1176 table 295 shows simplified branch mnemonics and syntax for bcl and bcla . table 296 shows the simplified branch mnemonics and syntax for bclrl and bcctrl with lr updating. table 295. simplified mnemonics for bcl and bcla with comparison conditions, lr update branch semantics bcl simplified mnemonic bcla simplified mnemonic branch if less than bcl 12, bi (1) , target bltl cr s target bcla 12, bi 1 , target bltla cr s target branch if less than or equal bcl 4, bi (2) , target blel cr s target bcla 4, bi 2 , target blela cr s target branch if not greater than bngl cr s target bngla cr s target branch if equal bcl 12, bi (3) , target beql cr s target bcla 12, bi 3 , target beqla cr s target branch if greater than or equal bcl 4, bi 1 , target bgel cr s target bcla 4, bi 1 , target bgela cr s target branch if not less than bnll cr s target bnlla cr s target branch if greater than bcl 12, bi 2 , target bgtl cr s target bcla 12, bi 2 , target bgtla cr s target branch if not equal bcl 4, bi 3 , target bnel cr s target bcla 4, bi 3 , target bnela cr s target branch if summary overflow bcl 12, bi (4) , target bsol cr s target bcla 12, bi 4 , target bsola cr s target branch if not summary overflow bcl 4, bi 4 , target bnsl cr s target bcla 4, bi 4 , target bnsla cr s target 1. the value in the bi operand selects cr n [0], the lt bit. 2. the value in the bi operand selects cr n [1], the gt bit. 3. the value in the bi operand selects cr n [2], the eq bit. 4. the value in the bi operand selects cr n [3], the so bit. table 296. simplified mnemonics for bclrl and bcctrl with comparison conditions, lr update branch semantics bclrl simplified mnemonic bcctrl simplified mnemonic branch if less than bclrl 12, bi (1) , target bltlrl cr s target bcctrl 12, bi 1 , target bltctrl cr s target branch if less than or equal bclrl 4, bi (2) , target blelrl cr s target bcctrl 4, bi 2 , target blectrl cr s target branch if not greater than bnglrl cr s target bngctrl cr s target branch if equal bclrl 12, bi (3) , target beqlrl cr s target bcctrl 12, bi 3 , target beqctrl cr s target branch if greater than or equal bclrl 4, bi 1 , target bgelrl cr s target bcctrl 4, bi 1 , target bgectrl cr s target branch if not less than bnllrl cr s target bnlctrl cr s target branch if greater than bclrl 12, bi 2 , target bgtlrl cr s target bcctrl 12, bi 2 , target bgtctrl cr s target branch if not equal bclrl 4, bi 3 , target bnelrl cr s target bcctrl 4, bi 3 , target bnectrl cr s target branch if summary overflow bclrl 12, b (4) , target bsolrl cr s target bcctrl 12, bi 4 , target bsoctrl cr s target branch if not summary overflow bclrl 4, bi 4 , target bnslrl cr s target bcctrl 4, bi 4 , target bnsctrl cr s target 1. the value in the bi operand selects cr n [0], the lt bit. 2. the value in the bi operand selects cr n [1], the gt bit. 3. the value in the bi operand selects cr n [2], the eq bit. 4. the value in the bi operand selects cr n [3], the so bit. RM0004 simplified mnemonics for powerpc instructions 1128/1176 b.5 compare word simplified mnemonics in compare word instructions, the l operand indicates a word (l = 0) or a double-word (l = 1). simplified mnemonics in ta b l e 2 9 7 eliminate the l operand for word comparisons. as with branch mnemonics, the cr d field of a compare instruction can be omitted if cr0 is used, as shown in examples 1 and 3 below. otherwise, the target cr field must be specified as the first operand. the following examples use word compare mnemonics: 1. compare r a with immediate value 100 as signed 32-bit integers and place result in cr0. cmpwi r a ,100 equivalent to cmpi 0,0,r a ,100 2. same as (1), but place results in cr4. cmpwi cr4,r a ,100 equivalent to cmpi 4,0 , r a ,100 3. compare r a and r b as unsigned 32-bit integers and place result in cr0. cmplw r a ,r b equivalent to cmpl 0,0,r a ,r b b.6 condition register logical simplified mnemonics the cr logical instructions, shown in ta b l e 2 9 8 , can be used to set, clear, copy, or invert a given cr bit. simplified mnemonics allow these operations to be coded easily. note that the symbols defined in ta b l e 2 8 2 can be used to identify the cr bit. examples using the cr logical mnemonics follow: table 297. word compare simplified mnemonics operation simplified mnemonic equivalent to: compare word immediate cmpwi cr d ,r a , simm cmpi cr d ,0,r a , simm compare word cmpw cr d ,r a ,r b cmp cr d ,0,r a ,r b compare logical word immediate cmplwi cr d ,r a , uimm cmpli cr d ,0,r a , uimm compare logical word cmplw cr d ,r a ,r b cmpl cr d ,0,r a ,r b table 298. condition register logical simplified mnemonics operation simplified mnemonic equivalent to condition register set crset b x creqv b x ,b x ,b x condition register clear crclr b x crxor b x ,b x ,b x condition register move crmove b x ,b y cror b x ,b y ,b y condition register not crnot b x ,b y crnor b x ,b y ,b y simplified mnemonics for powerpc instructions RM0004 1129/1176 1. set cr[57]. crset 25 equivalent to creqv 25,25,25 2. clear cr0[so]. crclr so equivalent to crxor 3,3,3 3. same as (2), but clear cr3[so]. crclr 4 * cr3 + so equivalent to crxor 15,15,15 4. invert the cr0[eq]. crnot eq,eq equivalent to crnor 2,2,2 5. same as (4), but cr4[eq] is inverted and the result is placed into cr5[eq]. crnot 4 * cr5 + eq, 4 * cr4 + eq equivalent to crnor 22,18,18 b.7 trap instructions simplified mnemonics the codes in table 299 are for the most common combinations of trap conditions. the mnemonics in table 300 are variations of trap instructions, with the most useful to values represented in the mnemonic rather than specified as a numeric operand. table 299. standard codes for trap instructions code description to encoding < > = u (2) lt less than 16 1 0 0 0 0 le less than or equal 20 1 0 1 0 0 eq equal 4 0 0 1 0 0 ge greater than or equal 12 0 1 1 0 0 gt greater than 8 0 1 0 0 0 nl not less than 12 0 1 1 0 0 ne not equal 24 1 1 0 0 0 ng not greater than 20 1 0 1 0 0 llt logically less than 2 0 0 0 1 0 lle logically less than or equal 6 0 0 1 1 0 lge logically greater than or equal 5 0 0 1 0 1 lgt logically greater than 1 0 0 0 0 1 lnl logically not less than 5 0 0 1 0 1 lng logically not greater than 6 0 0 1 1 0 ? unconditional 31 1 1 1 1 1 1. the symbol ? RM0004 simplified mnemonics for powerpc instructions 1130/1176 the following examples use the trap mnemonics shown in ta bl e 3 0 0 : 1. trap if r a is not zero. twnei r a ,0 equivalent to twi 24,r a ,0 2. trap if r a is not equal to r b. twne r a , r b equivalent to tw 24,r a ,r b 3. trap if r a is logically greater than 0x7ff. twlgti r a , 0x7ff equivalent to twi 1,r a , 0x7ff 4. trap unconditionally. trap equivalent to tw 31,0,0 trap instructions evaluate a trap condition as follows: the contents of r a are compared with either the sign-extended simm field or the contents of r b, depending on the trap instruction. the comparison results in five conditions that are anded with operand to. if the result is not 0, the trap exception handler is invoked. see table 301 for these conditions. table 300. trap simplified mnemonics trap semantics 32-bit comparison twi immediate tw register trap unconditionally ? trap trap if less than twlti twlt trap if less than or equal twlei twle trap if equal tweqi tweq trap if greater than or equal twgei twge trap if greater than twgti twgt trap if not less than twnli twnl trap if not equal twnei twne trap if not greater than twngi twng trap if logically less than twllti twllt trap if logically less than or equal twllei twlle trap if logically greater than or equal twlgei twlge trap if logically greater than twlgti twlgt trap if logically not less than twlnli twlnl trap if logically not greater than twlngi twlng table 301. to operand bit encoding to bit anded with condition 0 less than, using signed comparison 1 greater than, using signed comparison 2 equal 3 less than, using unsigned comparison 4 greater than, using unsigned comparison simplified mnemonics for powerpc instructions RM0004 1131/1176 b.8 simplified mnemonics for accessing sprs the mtspr and mfspr instructions specify a special-purpose register (spr) as a numeric operand. simplified mnemonics are provided that represent the spr in the mnemonic rather than requiring it to be coded as a numeric operand. the pattern for mtspr and mfspr simplified mnemonics is straightforward: replace the - spr portion of the mnemonic with the abbreviation for the spr (for example xer, srr0, or lr), eliminate the sprn operand, leaving the source or destination gpr operand, r s or r d. following are examples using the spr simplified mnemonics: 1. copy the contents of r s to the xer. mtxer r s equivalent to mtspr 1,r s 2. copy the contents of the lr to r d. mflr r d equivalent to mfspr r d ,8 3. copy the contents of r s to the ctr. mtctr r s equivalent to mtspr 9,r s the examples above show simplified mnemonics for accessing sprs defined by the aim version of the powerpc architecture; however, the same formula is used for book e, eis, and implementation-specific sprs, as shown in the following examples: 1. copy the contents of r s to csrr0. mtcsrr0 r s equivalent to mtspr 58,r s 2. copy the contents of ivor0 to r d. mfivor0 r d equivalent to mfspr r d ,400 3. copy the contents of r s to the mas1. mtmas1 r s equivalent to mtspr 625,r s there is an additional simplified mnemonic formula for accessing sprgs, although not all of these more complicated simplified mnemonics are supported by all assemblers. these are shown in ta b l e 3 0 2 along with the equivalent simplified mnemonic using the formula described above. b.9 recommended simp lified mnemonics this section describes commonly-used operations (such as no-op, load immediate, load address, move register, and complement register). b.9.1 no-op (nop) many instructions can be coded so that, effectively, no operation is performed. a mnemonic is provided for the preferred form of no-op. if an implementation performs any type of run- time optimization related to no-ops, the preferred form is the following: nop equivalent to ori 0,0,0 table 302. additional simplified mnemonics for accessing sprgs spr move to spr move from spr simplified mnemonic equivalent to simplified mnemonic equivalent to sprgs mtspr g n, r s mtspr 272 + n ,r s mfsprg r d , n mfspr r d , 272 + n mtspr g n, r s mfsprg n r d RM0004 simplified mnemonics for powerpc instructions 1132/1176 b.9.2 load immediate (li) the addi and addis instructions can be used to load an immediate value into a register. additional mnemonics are provided to convey the idea that no addition is being performed but that data is being moved from the immediate operand of the instruction to a register. 1. load a 16-bit signed immediate value into r d. li r d , value equivalent to addi r d ,0, value 2. load a 16-bit signed immediate value, shifted left by 16 bits, into r d. lis r d , value equivalent to addis r d ,0, value b.9.3 load address (la) this mnemonic permits computing the value of a base-displacement operand, using the addi instruction that normally requires a separate register and immediate operands. la r d , d( r a) equivalent to addi r d ,r a , d the la mnemonic is useful for obtaining the address of a variable specified by name, allowing the assembler to supply the base register number and compute the displacement. if the variable v is located at offset d v bytes from the address in r v, and the assembler has been told to use r v as a base for references to the data structure containing v , the following line causes the address of v to be loaded into r d: la r d , v equivalent to addi r d ,r v , d v b.9.4 move register (mr) several instructions can be coded to copy the contents of one register to another. a simplified mnemonic is provided that signifies that no computation is being performed, but merely that data is being moved from one register to another. the following instruction copies the contents of r s into r a. this mnemonic can be coded with a dot ( . ) suffix to cause the rc bit to be set in the underlying instruction. mr r a ,r s equivalent to or r a ,r s ,r s b.9.5 complement register (not) several instructions can be coded in a way that they complement the contents of one register and place the result into another register. simplified mnemonics allows this operation to be coded easily. the following instruction comp lements the contents of r s and places the result into r a. this mnemonic can be coded with a dot ( . ) suffix to cause the rc bit to be set in the underlying instruction. not r a ,r s equivalent to nor r a ,r s ,r s b.9.6 move to conditi on register (mtcr) this mnemonic permits copying gpr contents to the cr, using the same syntax as the mfcr instruction. mtcr r s equivalent to mtcrf 0xff ,r s simplified mnemonics for powerpc instructions RM0004 1133/1176 b.10 eis-specific simplified mnemonics this section describes simplifie d mnemonics for instructions de fines by auxiliary processing units (apus) defined as part of the motorola book e implementation standards. b.10.1 integer select (isel) the following mnemonics simplify the most common variants of the isel instruction that access cr0: integer select less than isellt r d ,r a ,r b equivalent to isel r d ,r a ,r b ,0 integer select greater than iselgt r d ,r a ,r b equivalent to isel r d ,r a ,r b ,1 integer select equal iseleq r d ,r a ,r b equivalent to isel r d ,r a ,r b ,2 b.10.2 spe mnemonics the following mnemonic handles mo ving of the full 64-bit spe gpr: vector move evmr r d ,r a equivalent to evor r d ,r a ,r a the following mnemonic performs a complement register: vector not evnot r d ,r a equivalent to evnor r d ,r a ,r a b.11 comprehensive list of simplified mnemonics table 303 lists simplified mnemonics. note that compiler designers may implement additional simplified mnemonics not listed here. table 303. simplified mnemonics simplified mnemonic mnemonic instruction bctr (1) bcctr 20,0 branch unconditionally ( bcctr without lr update) bctrl 1 bcctrl 20,0 branch unconditionally ( bcctrl with lr update) bdnz target 1 bc 16,0, target decrement ctr, branch if ctr 0 ( bc without lr update) bdnza target 1 bca 16,0, target decrement ctr, branch if ctr 0 ( bca without lr update) bdnzf bi, target bc 0,bi, target decrement ctr, branch if ctr 0 and condition false ( bc without lr update) bdnzfa bi, target bca 0,bi, target decrement ctr, branch if ctr 0 and condition false ( bca without lr update) bdnzfl bi, target bcl 0,bi, target decrement ctr, branch if ctr 0 and condition false ( bcl with lr update) bdnzfla bi, target bcla 0,bi, target decrement ctr, branch if ctr 0 and condition false ( bcla with lr update) RM0004 simplified mnemonics for powerpc instructions 1134/1176 bdnzflr bi bclr 0,bi decrement ctr, branch if ctr 0 and condition false ( bclr without lr update) bdnzflrl bi bclrl 0,bi decrement ctr, branch if ctr 0 and condition false ( bclrl with lr update) bdnzl target 1 bcl 16,0, target decrement ctr, branch if ctr 0 ( bcl with lr update) bdnzla target 1 bcla 16,0, target decrement ctr, branch if ctr 0 ( bcla with lr update) bdnzlr bi bclr 16,bi decrement ctr, branch if ctr 0 ( bclr without lr update) bdnzlrl 1 bclrl 16,0 decrement ctr, branch if ctr 0 ( bclrl with lr update) bdnzt bi, target bc 8,bi, target decrement ctr, branch if ctr 0 and condition true ( bc without lr update) bdnzta bi, target bca 8,bi, target decrement ctr, branch if ctr 0 and condition true ( bc a without lr update) bdnztl bi, target bcl 8,0, target decrement ctr, branch if ctr 0 and condition true ( bcl with lr update) bdnztla bi, target bcla 8,bi, target decrement ctr, branch if ctr 0 and condition true ( bcla with lr update) bdnztlr bi bclr 8,bi decrement ctr, branch if ctr 0 and condition true ( bclr without lr update) bdnztlr bi bclr 8,bi decrement ctr, branch if ctr = 0 and condition true ( bclr without lr update) bdnztlrl bi bclrl 8,bi decrement ctr, branch if ctr 0 and condition true ( bclrl with lr update) bdz target 1 bc 18,0, target decrement ctr, branch if ctr = 0 ( bc without lr update) bdza target 1 bca 18,0, target decrement ctr, branch if ctr = 0 ( bca without lr update) bdzf bi, target bc 2,bi, target decrement ctr, branch if ctr = 0 and condition false ( bc without lr update) bdzfa bi, target bca 2,bi, target decrement ctr, branch if ct r = 0 and condition false ( bca without lr update) bdzfl bi, target bcl 2,bi, target decrement ctr, branch if ct r = 0 and condition false ( bcl with lr update) bdzfla bi, target bcla 2,bi, target decrement ctr, branch if ctr = 0 and condition false ( bcla with lr update) bdzflr bi bclr 2,bi decrement ctr, branch if ctr = 0 and condition false ( bclr without lr update) bdzflrl bi bclrl 2,bi decrement ctr, branch if ctr = 0 and condition false ( bclrl with lr update) bdzl target 1 bcl 18,bi, target decrement ctr, branch if ctr = 0 ( bcl with lr update) bdzla target 1 bcla 18,bi, target decrement ctr, branch if ctr = 0 ( bcla with lr update) table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction simplified mnemonics for powerpc instructions RM0004 1135/1176 bdzlr 1 bclr 18,0 decrement ctr, branch if ctr = 0 ( bclr without lr update) bdzlrl 1 bclrl 18,0 decrement ctr, branch if ctr = 0 ( bclrl with lr update) bdzt bi, target bc 10,bi, target decrement ctr, branch if ctr = 0 and condition true ( bc without lr update) bdzta bi, target bca 10,bi, target decrement ctr, branch if ctr = 0 and condition true ( bca without lr update) bdztl bi, target bcl 10,bi, target decrement ctr, branch if ctr = 0 and condition true ( bcl with lr update) bdztla bi, target bcla 10,bi, target decrement ctr, branch if ctr = 0 and condition true ( bcla with lr update) bdztlrl bi bclrl 10, bi decrement ctr, branch if ctr = 0 and condition true ( bclrl with lr update) beq cr s target bc 12, bi (2) , target branch if equal ( bc without comparison conditions or lr updating) beqa cr s target bca 12, bi 2 , target branch if equal ( bca without comparison conditions or lr updating) beqctr cr s target bcctr 12, bi 2 , target branch if equal ( bcctr without comparison conditions and lr updating) beqctrl cr s target bcctrl 12, bi 2 , target branch if equal ( bcctrl with comparison conditions and lr update) beql cr s target bcl 12, bi 2 , target branch if equal ( bcl with comparison conditions and lr updating) beqla cr s target bcla 12, bi 2 , target branch if equal ( bcla with comparison conditions and lr updating) beqlr cr s target bclr 12, bi 2 , target branch if equal ( bclr without comparison conditions and lr updating) beqlrl cr s target bclrl 12, bi 2 , target branch if equal ( bclrl with comparison conditions and lr update) bf bi, target bc 4,bi, target branch if condition false (3) ( bc without lr update) bfa bi, target bca 4,bi, target branch if condition false 3 ( bca without lr update) bfctr bi bcctr 4,bi branch if condition false 3 ( bcctr without lr update) bfctrl bi bcctrl 4,bi branch if condition false 3 ( bcctrl with lr update) bfl bi, target bcl 4,bi, target branch if condition false 3 ( bcl with lr update) bfla bi, target bcla 4,bi, target branch if condition false 3 ( bcla with lr update) bflr bi bclr 4,bi branch if condition false 3 ( bclr without lr update) bflrl bi bclrl 4,bi branch if condition false 3 ( bclrl with lr update) bge cr s target bc 4, bi (4) , target branch if greater than or equal ( bc without comparison conditions or lr updating) table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction RM0004 simplified mnemonics for powerpc instructions 1136/1176 bgea cr s target bca 4, bi 4 , target branch if greater than or equal ( bca without comparison conditions or lr updating) bgectr cr s target bcctr 4, bi 4 , target branch if greater than or equal ( bcctr without comparison conditions and lr updating) bgectrl cr s target bcctrl 4, bi 4 , target branch if greater than or equal ( bcctrl with comparison conditions and lr update) bgel cr s target bcl 4, bi 4 , target branch if greater than or equal ( bcl with comparison conditions and lr updating) bgela cr s target bcla 4, bi 4 , target branch if greater than or equal ( bcla with comparison conditions and lr updating) bgelr cr s target bclr 4, bi 4 , target branch if greater than or equal ( bclr without comparison conditions and lr updating) bgelrl cr s target bclrl 4, bi 4 , target branch if greater than or equal ( bclrl with comparison conditions and lr update) bgt cr s target bc 12, bi (5) , target branch if greater than ( bc without comparison conditions or lr updating) bgta cr s target bca 12, bi 5 , target branch if greater than ( bca without comparison conditions or lr updating) bgtctr cr s target bcctr 12, bi 5 , target branch if greater than ( bcctr without comparison conditions and lr updating) bgtctrl cr s target bcctrl 12, bi 5 , target branch if greater than ( bcctrl with comparison conditions and lr update) bgtl cr s target bcl 12, bi 5 , target branch if greater than ( bcl with comparison conditions and lr updating) bgtla cr s target bcla 12, bi 5 , target branch if greater than ( bcla with comparison conditions and lr updating) bgtlr cr s target bclr 12, bi 5 , target branch if greater than ( bclr without comparison conditions and lr updating) bgtlrl cr s target bclrl 12, bi 5 , target branch if greater than ( bclrl with comparison conditions and lr update) ble cr s target bc 4, bi 5 , target branch if less than or equal ( bc without comparison conditions or lr updating) blea cr s target bca 4, bi 5 , target branch if less than or equal ( bca without comparison conditions or lr updating) blectr cr s target bcctr 4, bi 5 , target branch if less than or equal ( bcctr without comparison conditions and lr updating) blectrl cr s target bcctrl 4, bi 5 , target branch if less than or equal ( bcctrl with comparison conditions and lr update) blel cr s target bcl 4, bi 5 , target branch if less than or equal ( bcl with comparison conditions and lr updating) table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction simplified mnemonics for powerpc instructions RM0004 1137/1176 blela cr s target bcla 4, bi 5 , target branch if less than or equal ( bcla with comparison conditions and lr updating) blelr cr s target bclr 4, bi 5 , target branch if less than or equal ( bclr without comparison conditions and lr updating) blelrl cr s target bclrl 4, bi 5 , target branch if less than or equal ( bclrl with comparison conditions and lr update) blr 1 bclr 20,0 branch unconditionally ( bclr without lr update) blrl 1 bclrl 20,0 branch unconditionally ( bclrl with lr update) blt cr s target bc 12, bi , target branch if less than ( bc without comparison conditions or lr updating) blta cr s target bca 12, bi 4 , target branch if less than ( bca without comparison conditions or lr updating) bltctr cr s target bcctr 12, bi 4 , target branch if less than ( bcctr without comparison conditions and lr updating) bltctrl cr s target bcctrl 12, bi 4 , target branch if less than ( bcctrl with comparison conditions and lr update) bltl cr s target bcl 12, bi 4 , target branch if less than ( bcl with comparison conditions and lr updating) bltla cr s target bcla 12, bi 4 , target branch if less than ( bcla with comparison conditions and lr updating) bltlr cr s target bclr 12, bi 4 , target branch if less than ( bclr without comparison conditions and lr updating) bltlrl cr s target bclrl 12, bi 4 , target branch if less than ( bclrl with comparison conditions and lr update) bne cr s target bc 4, bi 3 , target branch if not equal ( bc without comparison conditions or lr updating) bnea cr s target bca 4, bi 3 , target branch if not equal ( bca without comparison conditions or lr updating) bnectr cr s target bcctr 4, bi 3 , target branch if not equal ( bcctr without comparison conditions and lr updating) bnectrl cr s target bcctrl 4, bi 3 , target branch if not equal ( bcctrl with comparison conditions and lr update) bnel cr s target bcl 4, bi 3 , target branch if not equal ( bcl with comparison conditions and lr updating) bnela cr s target bcla 4, bi 3 , target branch if not equal ( bcla with comparison conditions and lr updating) bnelr cr s target bclr 4, bi 3 , target branch if not equal ( bclr without comparison conditions and lr updating) bnelrl cr s target bclrl 4, bi 3 , target branch if not equal ( bclrl with comparison conditions and lr update) table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction RM0004 simplified mnemonics for powerpc instructions 1138/1176 bng cr s target bc 4, bi 5 , target branch if not greater than ( bc without comparison conditions or lr updating) bnga cr s target bca 4, bi 5 , target branch if not greater than ( bca without comparison conditions or lr updating) bngctr cr s target bcctr 4, bi 5 , target branch if not greater than ( bcctr without comparison conditions and lr updating) bngctrl cr s target bcctrl 4, bi 5 , target branch if not greater than ( bcctrl with comparison conditions and lr update) bngl cr s target bcl 4, bi 5 , target branch if not greater than ( bcl with comparison conditions and lr updating) bngla cr s target bcla 4, bi 5 , target branch if not greater than ( bcla with comparison conditions and lr updating) bnglr cr s target bclr 4, bi 5 , target branch if not greater than ( bclr without comparison conditions and lr updating) bnglrl cr s target bclrl 4, bi 5 , target branch if not greater than ( bclrl with comparison conditions and lr update) bnl cr s target bc 4, bi 4 , target branch if not less than ( bc without comparison conditions or lr updating) bnla cr s target bca 4, bi 4 , target branch if not less than ( bca without comparison conditions or lr updating) bnlctr cr s target bcctr 4, bi 4 , target branch if not less than ( bcctr without comparison conditions and lr updating) bnlctrl cr s target bcctrl 4, bi 4 , target branch if not less than ( bcctrl with comparison conditions and lr update) bnll cr s target bcl 4, bi 4 , target branch if not less than ( bcl with comparison conditions and lr updating) bnlla cr s target bcla 4, bi 4 , target branch if not less than ( bcla with comparison conditions and lr updating) bnllr cr s target bclr 4, bi 4 , target branch if not less than ( bclr without comparison conditions and lr updating) bnllrl cr s target bclrl 4, bi 4 , target branch if not less than ( bclrl with comparison conditions and lr update) bns cr s target bc 4, bi (6) , target branch if not summary overflow ( bc without comparison conditions or lr updating) bnsa cr s target bca 4, bi 6 , target branch if not summary overflow ( bca without comparison conditions or lr updating) bnsctr cr s target bcctr 4, bi 6 , target branch if not summary overflow ( bcctr without comparison conditions and lr updating) bnsctrl cr s target bcctrl 4, bi 6 , target branch if not summary overflow ( bcctrl with comparison conditions and lr update) table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction simplified mnemonics for powerpc instructions RM0004 1139/1176 bnsl cr s target bcl 4, bi 6 , target branch if not summary overflow ( bcl with comparison conditions and lr updating) bnsla cr s target bcla 4, bi 6 , target branch if not summary overflow ( bcla with comparison conditions and lr updating) bnslr cr s target bclr 4, bi 6 , target branch if not summary overflow ( bclr without comparison conditions and lr updating) bnslrl cr s target bclrl 4, bi 6 , target branch if not summary overflow ( bclrl with comparison conditions and lr update) bso cr s target bc 12, bi 6 , target branch if summary overflow ( bc without comparison conditions or lr updating) bsoa cr s target bca 12, bi 6 , target branch if summary overflow ( bca without comparison conditions or lr updating) bsoctr cr s target bcctr 12, bi 6 , target branch if summary overflow ( bcctr without comparison conditions and lr updating) bsoctrl cr s target bcctrl 12, bi 6 , target branch if summary overflow ( bcctrl with comparison conditions and lr update) bsol cr s target bcl 12, bi 6 , target branch if summary overflow ( bcl with comparison conditions and lr updating) bsola cr s target bcla 12, bi 6 , target branch if summary overflow ( bcla with comparison conditions and lr updating) bsolr cr s target bclr 12, bi 6 , target branch if summary overflow ( bclr without comparison conditions and lr updating) bsolrl cr s target bclrl 12, bi 6 , target branch if summary overflow ( bclrl with comparison conditions and lr update) bt bi, target bc 12,bi, target branch if condition true 3 ( bc without lr update) bta bi, target bca 12,bi, target branch if condition true 3 ( bca without lr update) btctr bi bcctr 12,bi branch if condition true 3 ( bcctr without lr update) btctrl bi bcctrl 12,bi branch if condition true 3 ( bcctrl with lr update) btl bi, target bcl 12,bi, target branch if condition true 3 ( bcl with lr update) btla bi, target bcla 12,bi, target branch if condition true 3 ( bcla with lr update) btlr bi bclr 12,bi branch if condition true 3 ( bclr without lr update) btlrl bi bclrl 12,bi branch if condition true 3 ( bclrl with lr update) clrlslwi r a ,r s , b , n ( n b 31) rlwinm r a ,r s , n , b ? n , 31 ? n clear left and shift left word immediate clrlwi r a ,r s , n ( n < 32) rlwinm r a ,r s ,0, n ,31 clear left word immediate clrrwi r a ,r s , n ( n < 32) rlwinm r a ,r s ,0,0, 31 ? n clear right word immediate cmplw cr d ,r a ,r b cmpl cr d ,0,r a ,r b compare logical word table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction RM0004 simplified mnemonics for powerpc instructions 1140/1176 cmplwi cr d ,r a , uimm cmpli cr d ,0,r a , uimm compare logical word immediate cmpw cr d ,r a ,r b cmp cr d ,0,r a ,r b compare word cmpwi cr d ,r a , simm cmpi cr d ,0,r a , simm compare word immediate crclr bx crxor bx , bx , bx condition register clear crmove bx , by cror bx , by , by condition register move crnot bx , by crnor bx , by , by condition register not crset bx creqv bx , bx , bx condition register set evmr r d ,r a evor r d ,r a ,r a vector move register evnot r d ,r a evnor r d ,r a ,r a vector complement register evsubiw r d ,r b,uimm evsubifw r d , uimm ,r b vector subtract word immediate evsubw r d ,r b ,r a evsubfw r d ,r a ,r b vector subtract word extlwi r a ,r s , n , b ( n > 0) rlwinm r a ,r s , b ,0, n ? 1 extract and left justify word immediate extrwi r a ,r s , n , b ( n > 0) rlwinm r a ,r s , b + n , 32 ? n ,31 extract and right justify word immediate inslwi r a ,r s , n , b ( n > 0) rlwimi r a ,r s , 32 ? b , b , ( b + n ) ? 1 insert from left word immediate insrwi r a ,r s , n , b ( n > 0) rlwimi r a ,r s , 32 ? ( b + n ) , b , ( b + n ) ? 1 insert from right word immediate iseleq r d ,r a ,r b isel r d ,r a ,r b ,2 integer select equal iselgt r d ,r a ,r b isel r d ,r a ,r b ,1 integer select greater than isellt r d ,r a ,r b isel r d ,r a ,r b ,0 integer select less than la r d , d( r a) addi r d, r a , d load address li r d , value addi r d ,0, value load immediate lis r d , value addis r d ,0, value load immediate signed mf spr rd mfspr rd,sprn move from spr (see chapter b.8: simplified mnemonics for accessing sprs on page 1131 .? ) mr r a ,r s or r a ,r s ,r s move register mtcr r s mtcrf 0xff ,r s move to condition register mt spr rs mfspr sprn,rs move to spr (see chapter b.8: simplified mnemonics for accessing sprs on page 1131 .? ) nop ori 0,0,0 no-op not r a ,r s nor r a ,r s ,r snot not r a ,r s nor r a ,r s ,r s complement register table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction simplified mnemonics for powerpc instructions RM0004 1141/1176 rotlw r a ,r s ,r b rlwnm r a ,r s ,r b ,0,31 rotate left word rotlwi r a ,r s , n rlwinm r a ,r s , n ,0,31 rotate left word immediate rotrwi r a ,r s , n rlwinm r a ,r s , 32 ? n ,0,31 rotate right word immediate slwi r a ,r s , n ( n < 32) rlwinm r a ,r s , n ,0, 31 ? n shift left word immediate srwi r a ,r s , n ( n < 32) rlwinm r a ,r s , 32 ? n , n ,31 shift right word immediate sub r d ,r a ,r b subf r d ,r b ,r a subtract from subc r d ,r a ,r b subfc r d ,r b ,r a subtract from carrying subi r d ,r a , value addi r d ,r a , ?value subtract immediate subic r d ,r a , value addic r d ,r a , ?value subtract immediate carrying subic. r d ,r a , value addic. r d ,r a , ? value subtract immediate carrying subis r d ,r a , value addis r d ,r a , ?value subtract immediate signed tweq r a , simm tw 4,r a , simm trap if equal tweqi r a , simm twi 4,r a , simm trap immediate if equal twge r a , simm tw 12,r a , simm trap if greater than or equal twgei r a , simm twi 12,r a , simm trap immediate if greater than or equal twgt r a , simm tw 8,r a , simm trap if greater than twgti r a , simm twi 8,r a , simm trap immediate if greater than twle r a , simm tw 20,r a , simm trap if less than or equal twlei r a , simm twi 20,r a , simm trap immediate if less than or equal twlge r a , simm tw 12,r a , simm trap if logically greater than or equal twlgei r a , simm twi 12,r a , simm trap immediate if logically greater than or equal twlgt r a , simm tw 1,r a , simm trap if logically greater than twlgti r a , simm twi 1,r a , simm trap immediate if logically greater than twlle r a , simm tw 6,r a , simm trap if logically less than or equal twllei r a , simm twi 6,r a , simm trap immediate if logically less than or equal twllt r a , simm tw 2,r a , simm trap if logically less than twllti r a , simm twi 2,r a , simm trap immediate if logically less than twlng r a , simm tw 6,r a , simm trap if logically not greater than twlngi r a , simm twi 6,r a , simm trap immediate if logically not greater than twlnl r a , simm tw 5,r a , simm trap if logically not less than table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction RM0004 simplified mnemonics for powerpc instructions 1142/1176 twlnli r a , simm twi 5,r a , simm trap immediate if logically not less than twlt r a , simm tw 16,r a , simm trap if less than twlti r a , simm twi 16,r a , simm trap immediate if less than twne r a , simm tw 24,r a , simm trap if not equal twnei r a , simm twi 24,r a , simm trap immediate if not equal twng r a , simm tw 20,r a , simm trap if not greater than twngi r a , simm twi 20,r a , simm trap immediate if not greater than twnl r a , simm tw 12,r a , simm trap if not less than twnli r a , simm twi 12,r a , simm trap immediate if not less than 1. simplified mnemonics for branch instructions that do not test a cr bit should not specify one; a programming error may occur. 2. the value in the bi operand selects cr n [2], the eq bit. 3. instructions for which b0 is either 12 (branch if condition true) or 4 (branch if condition false) do not depend on the ctr value and can be alternately coded by incorporating the condition specified by the bi field, as described in chapter b.4.6: simplified mnemonics that in corporate cr condition s (eliminates bo and replaces bi with crs) on page 1123 .? 4. the value in the bi operand selects cr n [0], the lt bit. 5. the value in the bi operand selects cr n [1], the gt bit. 6. the value in the bi operand selects cr n [3], the so bit. table 303. simplified mnemonics (continued) simplified mnemonic mnemonic instruction programming examples RM0004 1143/1176 appendix c programming examples this appendix gives examples of how memory synchronization instructions can be used to emulate various synchronization primitives and to provide more complex forms of synchronization. it also describes multiple precision shifts. c.1 synchronization examples in this appendix have a common form. after possible initializ ation, a conditional sequence begins with a load and reserve instruction that may be followed by memory accesses and computations that include neither a load and reserve nor a store conditional. the sequence ends with a store conditional with the same target address as the initial load and reserve. in most of the examples, failure of the store conditional causes a branch back to the load and reserve for a repeated attempt. on the assumption that contention is low, the conditional branch in the examples is optimized for the case in which the store conditional succeeds, by setting the branch-prediction bit appropriately. these examples focus on techniques for the correct modification of shared memory locations: see note 4 in chapter c.1.4: synchronization notes on page 1147 ,? for a discussion of how the retry strategy can affect performance. load and reserve and store conditional instructions depend on the coherence mechanism of the system. stores to a given location are coherent if they are serialized in some order, and no processor is able to observe a subset of those stores as occurring in a conflicting order. each load operation, whether ordinary or load and reserve, returns a value that has a well- defined source. the source can be the store or store conditional instruction that wrote the value, an operation by some other mechanism that accesses memory (for example, an i/o device), or the initial state of memory. the function of an atomic read/modify/write operation is to read a location and write its next value, possibly as a function of its current value, all as a single atomic operation. we assume that locations accessed by read/modify/write operations are accessed coherently, so the concept of a value being the next in the sequence of values for a location is well defined. the conditional sequence, as defined above, provides the effect of an atomic read/modify/write operation, but not with a single atomic instruction. let addr be the location that is the common target of the load and reserve and store conditional instructions. then the guarantee the architecture makes for the successful execution of the conditional sequence is that no store into addr by another processor or mechanism has intervened between the source of the load and reserve and the store conditional. for each of these examples, it is assumed that a similar sequence of instructions is used by all processes requiring synchronization on the accessed data. note: because memory synchronization instructions have implementation dependencies (for example, the granularity at which reservations are managed), they must be used with care. the operating system should provide system library programs that use these instructions to implement the high-level synchronization functions (such as, test and set or compare and swap) needed by application programs. application programs should use these library programs, rather than use memory synchronization instructions directly. RM0004 programming examples 1144/1176 c.1.1 synchronization primitives the following examples show how the lwarx and stwcx. instructions can be used to implement various synchronization primitives. the sequences used to emulate the various pr imitives consist primar ily of a loop using lwarx and stwcx. . no additional synchronization is necessary, because the stwcx. will fail, clearing eq, if the word loaded by lwarx has changed before the stwcx. is executed: see : atomic update primitives using lwarx and stwcx. on page 176 for details. fetch and no-op the fetch and no-op primitive atomically loads the current value in a word in memory. in this example it is assumed that the address of the word to be loaded is in gpr3 and the data loaded are returned in gpr4. loop: lwarx r4,0,r3 #load and reserve stwcx. r4,0,r3 #store old value if still reserved bc 4,2,loop #loop if lost reservation if the stwcx. succeeds, it stores to the target location the same value that was loaded by the preceding lwarx . while the store is redundant with respect to the value in the location, its success ensures th at the value loaded by the lwarx was the current value, that is, that the source of the value loaded by the lwarx was the last store to the location that preceded the stwcx. in the coherence order for the location. fetch and store the fetch and store primitive atomically loads and replaces a word in memory. in this example it is assumed that the address of the word to be loaded and replaced is in gpr3, the new value is in gpr4, and the old value is returned in gpr5. loop: lwarx r5,0,r3 #load and reserve stwcx. r4,0,r3 #store new value if still reserved bc 4,2,loop #loop if lost reservation fetch and add the fetch and add primitive atomically increments a word in memory. in this example it is assumed that the address of the word to be incremented is in gpr3, the increment is in gpr4, and the old value is returned in gpr5. loop: lwarx r5,0,r3 #load and reserve add r0,r4,r5 #increment word stwcx. r0,0,r3 #store new value if still reserved bc 4,2,loop #loop if lost reservation fetch and and the fetch and and primitive atomically ands a value into a word in memory. in this example it is assumed that the address of the word to be anded is in gpr3, the value to and into it is in gpr4, and the old value is returned in gpr5. loop: lwarx r5,0,r3 #load and reserve and r0,r4,r5 #and word programming examples RM0004 1145/1176 stwcx. r0,0,r3 #store new value if still reserved bc 4,2,loop #loop if lost reservation this sequence can be changed to perform another boolean operation atomically on a word in memory by changing the and to the desired boolean instruction ( or , xor , etc.). test and set this version of the test and set primitive atomically loads a word from memory, sets the word in memory to a nonzero value if the value loaded is zero, and sets the eq bit of cr field 0 to indicate whether the value loaded is zero. in this example it is assumed that the address of the word to be tested is in gpr3, the new value (nonzero) is in gpr4, and the old value is returned in gpr5. loop: lwarx r5,0,r3 #load and reserve cmpwi r5,0 #done if word bc 4,2,done #not equal to 0 stwcx. r4,0,r3 #try to store non-0 bc 4,2,loop #loop if lost reservation done: compare and swap the compare and swap primitive atomically compares a value in a register with a word in memory, if they are equal stores the value from a second register into the word in memory, if they are unequal loads the word from memory into the first register, and sets cr0[eq] to indicate the result of the comparison. in this example it is assumed that the address of the word to be tested is in gpr3, the comparand is in gpr4 and the old value is re turned there, and the new value is in gpr5. loop: lwarx r6,0,r3 #load and reserve cmpw r4,r6 #1st 2 operands equal? bc 4,2,exit #skip if not stwcx. r5,0,r3 #store new value if still reserved bc 4,2,loop #loop if lost reservation exit: or r4,r6,r6 #return value from memory note: 1 the semantics given for compare and swap above are based on those of the ibm system/370 compare and swap instruction. other architectures may define a compare and swap instruction differently. 2 compare and swap is shown primarily for pedagogical reasons. it is useful on machines that lack the better sy nchronization facilit ies provided by lwarx and stwcx. . a major weakness of a system/370-style compare and swap instructio n is that, although the instruction itself is atomic, it checks only that the old and current values of the word being tested are equal, with the result that programs that use such a compare and swap to control a shared resource can err if the word has been modified and the old value subsequently restored. the sequence shown above has the same weakness. 3 in some applications the second bc and/or the or can be omitted. the bc is needed only if the application requires that if cr0[eq] on exit indicates not equal then gpr4 and gpr6 are not equal. the or is needed only if the application requires that if the comparands are not equal then the word from memory is loaded into the register with which it was compared (rather than into a third register). if any of these instructions is omitted, the resulting compare and swap does not obey system/370 semantics. RM0004 programming examples 1146/1176 c.1.2 lock acquisition and release this example gives an algorithm for locking that demonstrates the use of synchronization with an atomic read/modify/write operation. a shared memory location, the address of which is an argument of the lock and unlock procedures, given by gpr3, is used as a lock, to control access to some sh ared resource such as a shared data structure. the lock is open when its value is 0 and closed (locked) when its value is 1. before accessing the shared resource the program executes the lock procedure, which sets the lock by changing its value from 0 to 1. to do this, the lock procedure calls test_and_set, which executes the code sequence shown in the test and set example of chapter c.1.1 on page 1144 ,? thereby atomically loading the old value of the lock, wr iting to the lock the new value (1) given in gpr4, returning the old value in gpr5 (not used below), and setting the eq bit of cr field 0 according to whether the value loaded is 0. the lock procedure repeats the test_and_set until it succeeds in changing the value of the lock from 0 to 1. because the shared resource must not be accessed until the lock has been set, the lock procedure contains an isync after the bc that checks for the success of test_and_set. the isync delays all subsequent instructions until all preceding instructions have completed. lock: mfspr r6,lr #save link register addi r4,r0,1 #obtain lock: loop: bl test_and_set# test-and-set bc 4,2,loop # retry til old = 0 # delay subsequent instructions til prior instructions finish isync mtspr lr,r6 #restore link register blr #return the unlock procedure stores a 0 to the lock location. most applications that use locking require, for correctness, that if the access to the shared resource includes stores, the program must execute an msync before releasing the lock. the msync ensures that the program?s modifications are performed with respect to other processors before the store that releases the lock is performed with respect to th ose processors. in this example, the unlock procedure begins with an msync for this purpose. unlock: msync #order prior stores addi r1,r0,0 #before lock release stw r1,0(r3) #store 0 to lock location blr #return c.1.3 list insertion this example shows how lwarx and stwcx. can be used to implement simple insertion into a singly linked list. (complicated list inserti on, in which multiple values must be changed atomically, or in which the correct order of insertion depends on the contents of the elements, cannot be implemented in the manner shown below and requires a more complicated strategy such as using locks.) the next element pointer from the list element after which the new element is to be inserted, here called the parent element, is stored into the new element, so that the new element points to the next element in the list: this store is performed unconditionally. then the address of the new element is conditionally stored into the parent element, thereby adding the new element to the list. in this example it is assumed that the address of the parent element is in gpr3, the address of the new element is in gpr4, and the next element pointer is at offset 0 from the start of programming examples RM0004 1147/1176 the element. it is also assumed that the next element pointer of each list element is in a reservation granule separate from that of the next element pointer of all other list elements: see : atomic update primitives using lwarx and stwcx. on page 176 loop: lwarx r2,0,r3 #get next pointer stw r2,0(r4) #store in new element msync #order stw before stwcx.(can omit if not mp) stwcx. r4,0,r3 #add new element to list bc 4,2,loop #loop if stwcx. failed in the preceding example, if two list elements have next element pointers in the same reservation granule then, in a multiprocessor, livelock can occur. (livelock is a state in which processors interact in a way such that no processor makes progress.) if list elements cannot be allocated such that each element?s next element pointer is in a different reservation granule, livelock can be avoided with this more complicated sequence: lwz r2,0(r3) #get next pointer loop1: or r5,r2,r2 #keep a copy stw r2,0(r4) #store in new element msync #order stw before stwcx. loop2: lwarx r2,0,r3 #get it again cmpw r2,r5 #loop if changed (someone bc 4,2,loop1 # else progressed) stwcx. r4,0,r3 #add new element to list bc 4,2,loop #loop if failed c.1.4 synchronization notes 1. in general, lwarx and stwcx. should be paired, with the same effective address used for both. the only exception is that an unpaired stwcx. to any (scratch) effective address can be used to clear any reservation held by the processor. 2. it is acceptable to execute a lwarx for which no stwcx. is executed. for example, this occurs in the test and set sequence shown above if the value loaded is not zero. 3. to increase the likelihood that forward progress is made, it is important that looping on lwarx / stwcx. pairs be minimized. for example, in the sequence shown above for test and set, this is achieved by testing the old value before attempting the store: were the order reversed, more stwcx. instructions might be executed, and reservations might more often be lost between the lwarx and the stwcx. . 4. the manner in which lwarx and stwcx. are communicated to other processors and mechanisms, and between levels of the memo ry subsystem within a given processor is implementation-dependent (see : atomic update primitives using lwarx and stwcx. on page 176 ). in some implementations performance may be improved by minimizing looping on a lwarx instruction that fails to return a desired value. for example, in the test and set example shown above, to stay in the loop until the word loaded is zero, bne- $+12 can be changed to bne- loop . however, in some implementations better performance may be obtained by using an ordinary load instruction to do the initial checking of the value, as follows. loop: lwz r5,0(r3) #load the word cmpi cr0,0,r5,0 #loop back if word bc 4,2,loop # not equal to 0 lwarx r5,0,r3 #try again, reserving cmpi cr0,0,r5,0 # (likely to succeed) RM0004 programming examples 1148/1176 bc 4,2,loop stwcx. r4,0,r3 #try to store non-0 bc 4,2,loop #loop if lost reservation 5. in a multiprocessor, livelock is possible if a loop containing a lwarx / stwcx. pair also contains an ordinary store instruction for which any byte of the affected memory area is in the reservation granule: see : atomic update primitives using lwarx and stwcx. on page 176 . for example, the first code sequence shown in chapter c.1.3 on page 1146 ,? can cause livelock if two list elements have next element pointers in the same reservation granule. c.2 multiple-precision shifts this section gives examples of how multiple-precision shifts can be programmed. a multiple-precision shift is defined to be a shift of an n-word quantity (32-bit implementations), where n>1. the quantity to be shifted is contained in n registers. the shift amount is specified either by an immediate value in the instruction or by a value in a register. the examples shown below distinguish between the cases n=2 and n>2. if n=2, the shift amount may be in the range 0?63, which are the maximum ranges supported by the shift instructions used. however if n>2, the shift amount must be in the range 0?31 for the examples to yield the desired result. the specif ic instance shown for n>2 is n=3: extending those code sequences to larger n is straightfo rward, as is reducing them to the case n=2 when the more stringent restriction on shift amount is met. for shifts with immediate shift amounts only the case n=3 is shown, because the more stringent restriction on shift amount is always met. in the examples it is assumed that gprs 2 and 3 (and 4) contain the quantity to be shifted, and that the result is to be placed into the same registers. in all cases, for both input and result, the lowest-numbered register contains the highest-order part of the data and highest- numbered register contains the lowest-order part. for non-immediate shifts, the shift amount is assumed to be in gpr6. for immediate shifts, the shift amount is assumed to be greater than 0. gprs 0 and 31 are used as scratch registers. for n>2, the number of instructions required is 2n?1 (immediate shifts) or 3n?1 (non- immediate shifts). programming examples RM0004 1149/1176 table 304. shifts left shifts right shifts shift left immediate, n=3 (shift amount < 32) rlwinm r2,r2,sh,0,31-sh rlwimi r2,r3,sh,32-sh,31 rlwinm r3,r3,sh,0,31-sh rlwimi r3,r4,sh,32-sh,31 rlwinm r4,r4,sh,0,31-sh shift right immediate, n=3 (shift amount < 32) rlwinm r4,r4,32-sh,sh,31 rlwimi r4,r3,32-sh,0,sh-1 rlwinm r3,r3,32-sh,sh,31 rlwimi r3,r2,32-sh,0,sh-1 rlwinm r2,r2,32-sh,sh,31 shift left, n=2 (shift amount < 64) subfic r31,r6,32 slw r2,r2,r6 srw r0,r3,r31 or r2,r2,r0 addi r31,r6,-32 slw r0,r3,r31 or r2,r2,r0 slw r3,r3,r6 shift right, n=2 (shift amount < 64) subfic r31,r6,32 srw r3,r3,r6 slw r0,r2,r31 or r3,r3,r0 addi r31,r6,-32 srw r0,r2,r31 or r3,r3,r0 srw r2,r2,r6 shift left, n=3 (shift amount < 32) subfic r31,r6,32 slw r2,r2,r6 srw r0,r3,r31 or r2,r2,r0 slw r3,r3,r6 srw r0,r4,r31 or r3,r3,r0 slw r4,r4,r6 shift right, n=3 (shift amount < 32) subfic r31,r6,32 srw r4,r4,r6 slw r0,r3,r31 or r4,r4,r0 srw r3,r3,r6 slw r0,r2,r31 or r3,r3,r0 srw r2,r2,r6 shift right algebraic immediate, n=3 (shift amnt < 32) rlwinm r4,r4,32-sh,sh,31 rlwimi r4,r3,32-sh,0,sh-1 rlwinm r3,r3,32-sh,sh,31 rlwimi r3,r2,32-sh,0,sh-1 srawi r2,r2,sh RM0004 programming examples 1150/1176 c.3 floating point conversions this section gives examples of how floating-point conversion instructions can be used to perform various conversions. note: some of the examples use the optional fsel instruction. care must be taken in using fsel if ieee compatibility is required, or if the values being tested can be nans or infinities. c.3.1 conversion from floating-poi nt number to signed integer word the full convert to signed integer word function can be implemented with the sequence shown below, assuming the floating-point value to be converted is in fpr1, the result is returned in gpr3, and a double word at displacement ?disp? from the address in gpr1 can be used as scratch space. shift right algebraic, n=2 (shift amount < 64) subfic r31,r6,32 srw r3,r3,r6 slw r0,r2,r31 or r3,r3,r0 addic. r31,r6,-32 sraw r0,r2,r31 bc 4,1,$+8 ori r3,r0,0 sraw r2,r2,r6 shift right algebraic, n=3 (shift amount < 32) subfic r31,r6,32 srw r4,r4,r6 slw r0,r3,r31 or r4,r4,r0 srw r3,r3,r6 slw r0,r2,r31 or r3,r3,r0 sraw r2,r2,r6 table 304. shifts (continued) left shifts right shifts fctiw[z] f2,f1 #convert to integer stfd f2,disp(r1) #store float lwa r3,disp+4(r1) #load word algebraic #(use lwz on a 32-bit implementation) programming examples RM0004 1151/1176 c.3.2 conversion from floating-point number to unsigned integer word in a 32-bit implementation the full convert to unsigned integer word function can be implemented with the sequence shown below, assuming the floating-point value to be converted is in fpr1, the value 0 is in fpr0, the value 232?1 is in fpr3, the value 231 is in fpr4, the result is returned in gpr3, and a double word at displacement ?disp? from the address in gpr1 can be used as scratch space. c.4 floating point selection this section gives examples of how the optional floating select instruction (fsel) can be used to implement floating-point minimum and maximum functions, and certain simple forms of if- then-else constructions, without branching. the examples show program fragments in an imaginary, c-like, high-level programming language, and the corresponding program fragment using fsel and other book e instructions. in the examples, a, b, x, y, and z are floating-point variables, which are assumed to be in fprs fa, fb, fx, fy, and fz. fpr fs is assumed to be available for scratch space. warning: care must be taken in us ing fsel if ieee compatibility is required, or if the values being tested can be nans or infinities: see section c.4.1, ?notes.? fsel f2,f1,f1,f0 #use 0 if < 0 fsub f5,f3,f1 #use max if > max fsel f2,f5,f2,f3 fsub f5,f2,f4 #subtract 2 31 fcmpu cr2,f2,f4 #use diff if 2 31 fsel f2,f5,f5,f2 fctiw[z] f2,f2 #convert to integer stfd f2,disp(r1) #store float lwz r3,disp+4(r1) #load word bc 12,8,$+8 #add 2 31 if input xoris r3,r3,0x8000 # was 2 31 RM0004 programming examples 1152/1176 c.4.1 notes the following notes apply to the preceding exam ples and to the corresponding cases using the other three arithmetic relations (<, , and ). they should also be considered when any other use of fsel is contemplated. table 305. comparison to zero high-level language: book e: notes if a ? 0.0 then x y else x z fsel fx,fa,fy,fz (1) if a > 0.0 then x y else x z fneg fs,fa fsel fx,fs,fz,fy (1,2) if a = 0.0 then x y else x z fsel fx,fa,fy,fz fneg fs,fa fsel fx,fs,fx,fz (1) table 306. minimum and maximum high-level language: book e: notes x min(a,b) fsub fs,fa,fb fsel fx,fs,fb,fa (3,4,5) x max(a,b) fsub fs,fa,fb fsel fx,fs,fa,fb (3,4,5) table 307. simple if-then-else constructions high-level language: book e: notes if a ? b then x y else x z fsub fs,fa,fb fsel fx,fs,fy,fz (4,5) if a > b then x y else x z fsub fs,fb,fa fsel fx,fs,fz,fy (3,4,5) if a = b then x y else x z fsub fs,fa,fb fsel fx,fs,fy,fz fneg fs,fs fsel fx,fs,fx,fz (4,5) programming examples RM0004 1153/1176 in these notes, the optimized program is the book e program shown, and the unoptimized program (not shown) is the corresponding book e program that uses fcmpu and branch conditional instruct ions instead of fsel . 1. the unoptimized program affects fpscr[vxsnan] and therefore may cause the system error handler to be invoked if the corresponding exception is enabled; the optimized program does not affect this bit. this property of the optimized program is incompatible with the ieee standard. 2. the optimized program gives the incorrect result if a is a nan. 3. the optimized program gives the incorrect result if a and/or b is a nan (except that it may give the correct result in some cases for the minimum and maximum functions, depending on how those functions are defined to operate on nans). 4. the optimized program gives the incorrect result if a and b are infinities of the same sign. (here it is assumed that invalid operation exceptions are disabled, in which case the result of the subtraction is a nan. th e analysis is more complicated if invalid operation exceptions are enabled, because in that case the target register of the subtraction is unchanged.) 5. the optimized program affects fpscr[ox, ux, xx,vxisi], and therefore may cause the system error handler to be invoked if the corresponding exceptions are enabled; the unoptimized program does not affect these bits. this property of the optimized program is incompatible with the ieee standard. RM0004 guidelines for 32-bit book e 1154/1176 appendix d guidelines for 32-bit book e this appendix provides guidelines used by 32-bit book e implementations; a set of guidelines is also outlined for software developers. application software written to these guidelines can be labeled 32-bit book e applications and can be expected to execute properly on all implementations of book e, both 32-bit and 64-bit implementations. 32-bit book e implementations execute applications that adhere to the software guidelines for 32-bit book e software outlined in this appendix and are not expected to properly execute 64-bit book e applications or any applications not adhering to these guidelines (that is, 64-bit book e applications). d.1 registers on 32-bit book e implementations book e defines 32- and 64-bit registers. all 32-bit registers are supported as defined in book e. however, except for the 64-bit fprs, only bits 32?63 of book e?s 64-bit registers are required to be implemented in hardware in 32-bit book e implementation. such 64-bit registers include lr, ctr, 32 gprs, srr0, and csrr0. book e makes no restrictions regarding implementing a subset of the 64-bit floating-point architecture. likewise, other than floating-point instructions, all instructions defined to return a 64-bit result return only bits 32?63 of the result on a 32-bit book e implementation. d.2 addressing on 32-bit book e implementations only bits 32?63 of the 64-bit book e instruction and data memory effective addresses need to be calculated and presented to main memory, so a 32-bit implementation can bypass prepending the 32 zeros when implementing these instructions. for branch to lr and branch to cr instructions, given that lr and ctr are implemented as 32-bit registers, only 2 zeros need to be concatenated to the right of bits 32?61 of these registers to form the 32- bit branch target address. the simplest implementation of next sequential instruction address computation suggests allowing effective address computations to wrap from 0xffff_fffc to 0x0000_0000. this wrapping is required of powerpc implementations. for 32-bit book e applications, there appears little if any benefit to allowing this wrapping behavior. book e specifies that the situation where the computation of the next sequential instruction address after address 0xffff_fffc is undefined. (note that the next sequential instruction address after address 0xffff_fffc on a 64-bit book e implementation is 0x0000_0001_0000_0000.) d.3 tlb fields on 32-bit book e implementations 32-bit book e implementations should support bits 32?53 of the effective page number (epn) field in the tlb. this size provides support for a 32-bit effective address, which powerpc abis may have come to expect to be available. 32-bit book e implementations may support greater than 32-bit real addresses by supporting more than bits 32?53 of the real page number (rpn) field in the tlb. guidelines for 32-bit book e RM0004 1155/1176 d.4 32-bit book e software guidelines d.4.1 32-bit instruction selection generally speaking, 32-bit software should avoid instructions that depend on any particular setting of bits 0?31 of any 64-bit application-a ccessible system register, including gprs, for producing the correct 32-bit results. context switching is not required to preserve the upper 32 bits of application-accessible 64-bit system registers and insertion of arbitrary settings of those upper 32 bits at arbitrary times during the execution of the 32-bit application must not affect the final result. d.4.2 32-bit addressing book e provides a complete set of data memory access instructions that perform a modulo 2 32 on the computed effective address and then prepend 32 zeros to produce the full 64-bit address. book e also provides a complete set of branch instructions that perform a modulo 2 32 on the computed branch target effective address and then prepend 32 zeros to produce the full 64-bit branch target address. on a 32-bit book e implementation, these instructions are executed as defined, but without prepending the 32 zeros (only the low-order 32 bits of the address are calculated). on a 64-bit implementation, executing these instructions as defined provides the effect of restricting the application to the lowest 32-bit address space. however, there is one exception. next sequential instruction address computations (not a taken branch) are not defined for 32-bit book e applications when the current instruction address is 0xffff_fffc. on a 32-bit book e implementation, the instruction address could simply wrap to 0x0000_0000, providing the same effect that is required in the powerpc architecture. however, when the 32-bit book e application is executed on a 64-bit book e implementation, the next sequential instructio n address calculated will be 0x0000_0001_0000_0000 and not 0x0000_0000_0000_0000. to avoid this problem the 32- bit book e application must either avoid this situation by not allowing code to span this address boundary, or requiring a branch absolute to address 0 be placed at address 0xffff_fffc to emulate the wrap. either of these approaches allows the application to execute on 32-bit and 64-bit book e implementations. RM0004 embedded floating-point results 1156/1176 appendix e embedded floating-point results this appendix summarizes results of various types of floating-point operations on various combinations of input operands. flag settings are performed on appropriate element flags. e.1 notation conventions and general rules for all tables in this appendix, the annotation and general rules in ta bl e 3 0 8 apply. table 308. notation conventions and general rules notation description * denotes that this status flag is set based on the results of the calculation _calc_ denotes that the result is updated with the results of the computation max denotes the maximum normalized number with the si gn set to the computation [sign(operand a) xor sign(operand b)] amax denotes the maximum normalized number wit h the sign set to the sign of operand a bmax denotes the maximum normalized number wit h the sign set to the sign of operand b pmax denotes the maximum normalized positive number. the encoding for single-precision is 0x7f7_fffff. the encoding for double-p recision is 0x7fef_ffff_ffff_ffff. nmax denotes the maximum normalized negative number. the encoding for single-precision is 0xff7f_ffff. the encoding for double -precision is 0xffef_ffff_ffff_ffff. pmin denotes the minimum normalized positive number. the encoding for single-precision is 0x00800000. the encoding for double-precision is 0x0010_0000_0000_0000. nmin denotes the minimum normalized negative number. the encoding for single-precision is 0x8080_0000. the encoding for double-precision is 0x8010_0000_0000_0000. calculations that overflow or underflow saturate. overflow for operations that have a fl oating-point result force the result to max . underflow for operations that have a floating-point result force the result to zero. overflow for operations that have a signed integer result force the result to 0x 7fff_ffff (positive) or 0x8000_0000 (negative). overflow for operations that have an unsigned integer result force the result to 0xffff_ffff (positive) or 0x0000_0000 (negative). 1 (superscript) denotes that the sign of the result is positive when the signs of operand a and operand b are different, for all rounding modes except round to mi nus infinity, where the sign of the result is then negative 2 (superscript) denotes that the sign of the result is positive when the signs of operand a and operand b are the same, for all rounding modes except round to minus infinity, where the sign of the result is then negative 3 (superscript) denotes that the sign for any multiply or divide is always the result of the operation [sign(operand a) xor sign(operand b)] 4 (superscript) denotes that if an overflow is de tected, the result may be saturated embedded floating-point results RM0004 1157/1176 e.2 add, subtract, multiply, and divide results table 309 lists results for add, subtract, multiply, and divide operations. table 309. floating-point results summary?add, sub, mul, div operation operand a operand b result finv fovf funf fdbz finx add add ? amax 1 0 0 0 0 add nan amax 10000 add denorm amax 1 0 0 0 0 add zero amax 1 0 0 0 0 add norm amax 1 0 0 0 0 add nan amax 1 0 0 0 0 add nan nan amax 10000 add nan denorm amax 1 0 0 0 0 add nan zero amax 1 0 0 0 0 add nan norm amax 1 0 0 0 0 add denorm bmax 1 0 0 0 0 add denorm nan bmax 1 0 0 0 0 add denorm denorm zero 1 10000 add denorm zero zero 1 10000 add denorm norm operand_b 4 10000 add zero bmax 1 0 0 0 0 add zero nan bmax 1 0 0 0 0 add zero denorm zero 1 10000 add zero zero zero 1 00000 add zero norm operand_b 4 00000 add norm bmax 1 0 0 0 0 add norm nan bmax 1 0 0 0 0 add norm denorm operand_a 4 10000 add norm zero operand_a 4 00000 add norm norm _calc_ 0 * * 0 * subtract sub ? amax 1 0 0 0 0 sub nan amax 10000 sub denorm amax 1 0 0 0 0 sub zero amax 1 0 0 0 0 RM0004 embedded floating-point results 1158/1176 sub norm amax 1 0 0 0 0 sub nan amax 1 0 0 0 0 sub nan nan amax 10000 sub nan denorm amax 1 0 0 0 0 sub nan zero amax 1 0 0 0 0 sub nan norm amax 1 0 0 0 0 sub denorm ?bmax 1 0 0 0 0 sub denorm nan ?bmax 1 0 0 0 0 sub denorm denorm zero 2 10000 sub denorm zero zero 2 10000 sub denorm norm ?operand_b 4 10000 sub zero ?bmax 1 0 0 0 0 sub zero nan ?bmax 1 0 0 0 0 sub zero denorm zero 2 10000 sub zero zero zero 2 00000 sub zero norm ?operand_b 4 00000 sub norm ?bmax 1 0 0 0 0 sub norm nan ?bmax 1 0 0 0 0 sub norm denorm operand_a 4 10000 sub norm zero operand_a 4 00000 sub norm norm _calc_ 0 * * 0 * multiply 3 mul ? max 10000 mul nan max 10000 mul denorm zero 1 0 0 0 0 mul zero zero 1 0 0 0 0 mul norm max 10000 mul nan max 10000 mul nan nan max 10000 mul nan denorm zero 1 0 0 0 0 mul nan zero zero 1 0 0 0 0 mul nan norm max 1 0 0 0 0 mul denorm zero 10000 mul denorm nan zero 1 0 0 0 0 table 309. floating-point results summ ary?add, sub, mul, div (continued) operation operand a operand b result finv fovf funf fdbz finx embedded floating-point results RM0004 1159/1176 mul denorm denorm zero 1 0 0 0 0 mul denorm zero zero 1 0 0 0 0 mul denorm norm zero 1 0 0 0 0 mul zero zero 10000 mul zero nan zero 1 0 0 0 0 mul zero denorm zero 1 0 0 0 0 mul zero zero zero 0 0 0 0 0 mul zero norm zero 0 0 0 0 0 mul norm max 10000 mul norm nan max 1 0 0 0 0 mul norm denorm zero 1 0 0 0 0 mul norm zero zero 0 0 0 0 0 mul norm norm _calc_ 0 * * 0 * divide 3 div ? zero 10000 div nan zero 10000 div denorm max 1 0 0 0 0 div zero max 1 0 0 0 0 div norm max 10000 div nan zero 10000 div nan nan zero 1 0 0 0 0 div nan denorm max 1 0 0 0 0 div nan zero max 1 0 0 0 0 div nan norm max 1 0 0 0 0 div denorm zero 10000 div denorm nan zero 1 0 0 0 0 div denorm denorm max 1 0 0 0 0 div denorm zero max 1 0 0 0 0 div denorm norm zero 1 0 0 0 0 div zero zero 10000 div zero nan zero 10000 div zero denorm max 1 0 0 0 0 div zero zero max 1 0 0 0 0 div zero norm zero 0 0 0 0 0 table 309. floating-point results summ ary?add, sub, mul, div (continued) operation operand a operand b result finv fovf funf fdbz finx RM0004 embedded floating-point results 1160/1176 e.3 double- to single-precision conversion table 310 lists results for double- to single-precision conversion. div norm zero 10000 div norm nan zero 1 0 0 0 0 div norm denorm max 1 0 0 0 0 div norm zero max 0 0 0 1 0 div norm norm _calc_ 0 * * 0 * table 309. floating-point results summ ary?add, sub, mul, div (continued) operation operand a operand b result finv fovf funf fdbz finx table 310. floating-point results summary?single convert from double operand b efscfd result finv fovf funf fdbz finx + pmax 1 0 0 0 0 ? nmax 1 0 0 0 0 +nan pmax 1 0 0 0 0 ?nan nmax 1 0 0 0 0 +denorm +zero 1 0 0 0 0 ?denorm ?zero 1 0 0 0 0 +zero +zero 00000 ?zero ?zero 0 0 0 0 0 norm _calc_ 0 * * 0 * embedded floating-point results RM0004 1161/1176 e.4 single- to double-precision conversion table 311 lists results for single- to double-precision conversion. e.5 conversion to unsigned table 312 lists results for conversion to unsigned operations. table 311. floating-point results summary?double convert from single operand b efdcfs result finv fovf funf fdbz finx + pmax 1 0 0 0 0 ? nmax 1 0 0 0 0 +nan pmax 1 0 0 0 0 ?nan nmax 1 0 0 0 0 +denorm +zero 1 0 0 0 0 ?denorm ?zero 1 0 0 0 0 +zero +zero 00000 ?zero ?zero 0 0 0 0 0 norm _calc_ 0 0 0 0 0 table 312. floating-point results summary?convert to unsigned operand b integer result ctui[d][z] fractional result ctuf finv fovf funf fdbz finx + 0xffff_ffff 0x7fff_ffff 1 0 0 0 0 ? 0010000 +nan 0 0 1 0 0 0 0 ?nan 0 0 1 0 0 0 0 denorm 0 0 1 0 0 0 0 zero 0 0 0 0 0 0 0 +norm _calc_ _calc_ * 0 0 0 * ?norm _calc_ _calc_ * 0 0 0 * RM0004 embedded floating-point results 1162/1176 e.6 conversion to signed table 313 lists results for conversion to signed operations. e.7 conversion from unsigned table 314 lists results for conversion from unsigned operations. e.8 conversion from signed table 315 lists results for conversion from signed operations. table 313. floating-point results summary?convert to signed operand b integer result ctsi[d][z] fractional result ctsf finv fovf funf fdbz finx + 0x7fff_ffff 0x7fff_ffff 1 0 0 0 0 ? 0x8000_0000 0x8000_0000 1 0 0 0 0 +nan 0 0 10000 ?nan 0 0 10000 denorm 0 0 1 0 0 0 0 zero 0 0 00000 +norm _calc_ _calc_ * 0 0 0 * ?norm _calc_ _calc_ * 0 0 0 * table 314. floating-point results summary?convert from unsigned operand b integer source cfui fractional source cfuf finv fovf funf fdbz finx zero zero zero 0 0 0 0 0 norm _calc_ _calc_ 0 0 0 0 * table 315. floating-point results summary?convert from signed operand b integer source cfsi fractional source cfsf finv fovf funf fdbz finx zero zero zero 0 0 0 0 0 norm _calc_ _calc_ 0 0 0 0 * embedded floating-point results RM0004 1163/1176 e.9 *abs, *nabs, and *neg operations table 316 lists results for *abs, *nabs, and *neg operations. table 316. floating-point results summary?*abs, *nabs, *neg operand a *abs *nabs *neg finv fovf funf fdbz finx + pmax | + nmax | ? ?amax | ? 10000 ? pmax | + nmax | ? ?amax | + 10000 +nan pmax | nan nmax | ?nan ?amax | ?nan 1 0 0 0 0 ?nan pmax | nan nmax | ?nan ?amax | +nan 1 0 0 0 0 +denorm +zero | +denorm ?zero | ?denorm ?zero | ?denorm 1 0 0 0 0 ?denorm +zero | +denorm ?zero | ?denorm +zero | +denorm 1 0 0 0 0 +zero +zero ?zero ?zero 0 0 0 0 0 ?zero +zero ?zero +zero 0 0 0 0 0 +norm +norm ?norm ?norm 0 0 0 0 0 ?norm +norm ?norm +norm 0 0 0 0 0 RM0004 glossary 1164/1176 15 glossary the glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. some of the terms and definitions included in the glossary are reprinted from ieee standard 754-1985, ieee standard for binary floating-point arithmetic , copyright ?1985 by the institute of electrical and electronics engineers, inc. with the permission of the ieee. a architecture. a detailed specification of requirements for a processor or computer system. it does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible implementations . asynchronous interrupt. interrupts that are caused by events external to the processor?s execution. in this document, the term asynchronous interrupt is used interchangeably with the word interrupt . atomic access. a bus access that attempts to be part of a read-write operation to the same address uninterrupted by any other access to that address (the term refers to the fact that the transactions are indivisible). the powerpc architecture implements atomic accesses through the lwarx / stwcx. instruction pair. b biased exponent. an exponent whose range of values is shifted by a constant (bias). typically a bias is provided to allow a range of positive values to express a range that includes both positive and negative values. big-endian. a byte-ordering method in memory where the address n of a word corresponds to the most- significant byte . in an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most-significant byte . see little-endian . boundedly undefined. a characteristic of certain operation results that are not rigidly prescribed by the powerpc architecture. boundedly-undefined results for a given operation may vary among implementations and between execution attempts in the same implementation. although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined , the results of executing instruct ions in contexts where results are allowed to be boundedly undefined are constrained to ones that could have been achieved by executing an arbitrary sequence of defined instructions, in valid form, starting in the state the machine was in before attempting to execute the given instruction. branch prediction. the process of guessing whether a branch will be taken. such predicti ons can be correct or incorrect; the term ?predicted? as it is used he re does not imply that the prediction is correct glossary RM0004 1165/1176 (successful). the powerpc architecture defines a means for static branch prediction as part of the instruction encoding. branch resolution. the determination of whether a branch is taken or not taken. a branch is said to be resolved when the processor can determine which instruction path to take. if the branch is resolved as predicted, the instructions following the predicted branch that may have been speculatively executed can complete (see completion ). if the branch is not resolved as predicted, instructions on the mispredicted path, and any results of speculative execution, are purged from the pipeline and fetching continues from the nonpredicted path. c cache. high-speed memory containing recently a ccessed data or instru ctions (subset of main memory). cache block. a small region of contiguous memory that is copied from memory into a cache . the size of a cache block may vary among processors; the maximum block size is one page . in powerpc processors, cache coherency is maintained on a cache-block basis. note that the term cache block is often used interchangeably with ?cache line.? cache coherency. an attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system. caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor?s cache. cache flush. an operation that removes from a cache any data from a specified address range. this operation ensures that any modified data within the specified address range is written back to main memory. this operation is generated typically by a data cache block flush ( dcbf ) instruction. caching-inhibited. a memory update policy in which the cache is bypassed and the load or store is performed to or from main memory. cast out. a cache block that must be written to memory when a cache miss causes a cache block to be replaced. changed bit. one of two page history bits found in each page table entry (pte). the processor sets the changed bit if any store is performed into the page . see also page access history bits and referenced bit . clean. an operation that causes a cache block to be written to memory, if modified, and then left in a valid, unmodified state in the cache. clear. to cause a bit or bit field to register a value of zero. see also set . completion. completion occurs when an instruction has finished executing, written back any results, and is removed from the completion queue (cq). when an instruction completes, it is guaranteed that this instruction and all previous instructions can cause no interrupts. context synchronization. an operation that ensures that all instructions in execution complete past the point where they can produce an interrupt , that all instructions in execution complete in the context in which they began execution, and that all subsequent instructions are fetched and executed in the new context. context synchronization may result from executing specific instructions (such as isync or rfi ) or when certain events occur (such as an interrupt ). RM0004 glossary 1166/1176 d denormalized number. a nonzero floating-point number whose exponent has a reserved value, usually the format's minimum, and whose explicit or implic it leading significand bit is zero. e effective address (ea). the 32-bit address specified for a load, store, or an instruction fetch. this address is then submitted to the mmu for translation to either a physical memory address or an i/o address. exception. a condition that, if enabled, generates an interrupt. execution synchronization. a mechanism by which all instructions in execution are architecturally complete before beginning execution (appearing to begin execution) of the next instruction. similar to context synchronization but doesn't force the contents of the instruction buffers to be deleted and refetched. exponent. in the binary representation of a floating-point number, the exponent is the component that normally signifies the integer power to which the value two is raised in determining the value of the represented number. see also biased exponent . f fetch. instruction retrieval from either the cache or main memory and placing them into the instruction queue. finish. finishing occurs in the last cycle of executio n. in this cycle, the cq entry is updated to indicate that the instruction has finished executing. floating-point register (fpr). any of the 32 registers in the floating-point register file. these registers provide the source operands and destination results for floating-point instructions. load instructions move data from memory to fprs and store instructions move data from fprs to memory. the fprs are 64 bits wide and store floating-point values in double-precision format. floating-point unit. the functional unit in a processor responsible for executing all floating- point instructions. flush. an operation that causes a cache block to be invalidated and the data, if modified, to be written to memory. fraction. in the binary representation of a floating-point number, the field of the significand that lies to the right of its implied binary point. g general-purpose register (gpr). any of the 32 registers in the general-purpose register file. these registers provide the source operands and destination results for all integer data manipulation instructions. integer load instructions move data from memory to gprs and store instructions move data from gprs to memory. guarded. the guarded attribute pertains to out-of-order execution. when a page is designated as guarded, instructions and data cannot be accessed out-of-order. glossary RM0004 1167/1176 h harvard architecture. an architectural model featuring separate caches and other memory management resources for instructions and data. i ieee 754. a standard written by the institute of electrical and electronics engineers that defines operations and representations of binary floating-point numbers. illegal instructions. a class of instructions that are not implemented for a particular powerpc processor. these include instructions not defined by the powerpc architecture. in addition, for 32-bit implementations, instructions that are defined only for 64-bit implementations are considered to be illegal instructions. for 64-bit implementations instructions that are defined only for 32-bit implementations are co nsidered to be ille gal instructions. implementation. a particular processor that conforms to the powerpc architecture, but may differ from other architecture-compliant implementations for example in design, feature set, and implementation of optional features. the powerpc architecture has many different implementations. imprecise interrupt. a type of synchronous interrupt that is allowed not to adhere to the precise interrupt model (see precise interrupt ). the powerpc architecture allows only floating-point exceptions to be handled imprecisely. integer unit. the functional unit responsible for executing all integer instructions. in order. an aspect of an operation that adheres to a sequential model. an operation is said to be performed in-order if, at the time that it is performed, it is known to be required by the sequential execution model. see out-of-order . instruction latency. the total number of clock cycles necessary to execute an instruction and make ready the results of that instruction. interrupt. a condition encountered by the processor that re quires special, supervisor-level processing. interrupt handler. a software routine that executes when an interrupt is taken. normally, the interrupt handler corrects the condition that caused the interrupt, or performs some other meaningful task (that may include aborting the program that caused the interrupt). RM0004 glossary 1168/1176 k kill. an operation that causes a cache block to be invalidated without wr iting any modified data to memory. l latency. the number of clock cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction. l2 cache. see secondary cache . least-significant bit (lsb). the bit of least value in an address, register, field, data element, or instruction encoding. least-significant byte (lsb). the byte of least value in an address, register, data element, or instruction encoding. little-endian. a byte-ordering method in memory where the address n of a word corresponds to the least- significant byte . in an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte . see big-endian . m mantissa. the decimal part of logarithm. memory access ordering. the specific order in which the processor performs load and store memory accesses and the order in which those accesses complete. memory-mapped accesses. accesses whose addresses use the page or block address translation mechanisms provided by the mmu and that occur externally with the bus protocol defined for memory. memory coherency. an aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that sh are system memory. memory consistency. refers to agreement of levels of memory with respect to a single processor and system memory (for example, on-chip cache, secondary cache, and system memory). memory management unit (mmu). the functional unit that is capable of translating an effective (logical) address to a physical address, providing protection mechanisms, and defining caching methods. most-significant bit (msb). glossary RM0004 1169/1176 the highest-order bit in an address, registers, data element, or instruction encoding. most-significant byte (msb). the highest-order byte in an address, registers, data element, or instruction encoding. n nan. an abbreviation for not a number; a symbolic entity encoded in floating-point format. there are two types of nans?signa ling nans and quiet nans. no-op. no-operation. a single-cycle operation that does not affect registers or generate bus activity. normalization. a process by which a floating-point value is manipulated such that it can be represented in the format for the appropriate precision (single- or double-precision). for a floating-point value to be representable in the single- or double-precision format, the leading implied bit must be a 1. o oea (operating environment architecture). the level of the architecture that describes powerpc memory management model, supervisor-level registers, synchronization requirements, and the interrupt model. it also defines the time-base feature from a supervis or-level perspective. implementations that conform to the powerpc oea also conform to the powerpc uisa and vea. optional. a feature, such as an instruction, a register, or an interrupt, that is defined by the powerpc architecture but not required to be implemented. out-of-order. an aspect of an operation that allows it to be performed ahead of one that may have preceded it in the sequential model, for example, speculative operations. an operation is said to be performed out-of-order if, at the time that it is performed, it is not known to be required by the sequential execution model. see in-order . out-of-order execution. a technique that allows instructions to be issued and completed in an order that differs from their sequence in the instruction stream. overflow. an condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register(s). for example, if two 32-bit numbers are multiplied, the result may not be representable in 32 bits. since 32-bit registers cannot represent this sum, an overflow condition occurs. RM0004 glossary 1170/1176 p page. a region in memory. the oea defines a page as a 4-kbyte area of memory, aligned on a 4- kbyte boundary. page fault. a page fault is a condition that occurs when the processor attempts to access a memory location that does not reside within a page not currently resident in physical memory . on powerpc processors, a page fault interrupt condition occurs when a matching, valid page table entry (pte[v] = 1) cannot be located. physical memory. the actual memory that can be accessed through the system?s memory bus. pipelining. a technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed. precise interrupts. a category of interrupt for which the pipeline can be stopped so instructions that preceded the faulting instruction can complete and subsequent instructions can be flushed and redispatched after interrupt handling has completed. see imprecise interrupts . primary opcode. the most-significant 6 bits (bits 0?5) of the instruction encoding that identifies the type of instruction. program order. the order of instructions in an executing program. more specifically, this term is used to refer to the original order in which program instructions are fetched into the instruction queue from the cache. protection boundary. a boundary between protection domains . q quiet nan. a type of nan that can propagate through most arithmetic operations without signaling interrupts. a quiet nan is used to represent the results of certain invalid operations, such as invalid arithmetic operations on infini ties or on nans, when invalid. see signaling nan . r record bit. bit 31 (or the rc bit) in the instruction encoding. when it is set, updates the condition register (cr) to reflect the result of the operation. referenced bit. glossary RM0004 1171/1176 one of two page history bits found in each page table entry . the processor sets the referenced bit whenever the page is accessed for a read or write. see also page access history bits . register indirect addressing. a form of addressing that specifies one gpr that contains the address for the load or store. register indirect with immediate index addressing. a form of addressing that specifies an immedi ate value to be added to the contents of a specified gpr to form the target address for the load or store. register indirect with index addressing. a form of addressing that specifies that the contents of two gprs be added together to yield the target address for the load or store. rename register. temporary buffers used by instructions that have finished execution but have not completed. reservation. the processor establishes a reservation on a cache block of memory space when it executes an lwarx instruction to read a memory semaphore into a gpr. reservation station. a buffer between the dispatch and execute stages that allows instructions to be dispatched even though the results of instructions on which the dispatched instruction may depend are not available. risc (reduced instruction set computing). an architecture characterized by fixed-length instructions with nonoverlapping functionality and by a separate set of load and store instructions that perform memory accesses. s secondary cache. a cache memory that is typically larger and has a longer access time than the primary cache. a secondary cache may be shared by multiple devices. also referred to as l2, or level-2, cache. set ( v ) . to write a nonzero value to a bit or bit field; the opposite of clear . the term ?set? may also be used to generally describe the updating of a bit or bit field. set ( n ) . a subdivision of a cache . cacheable data can be stored in a given location in one of the sets, typically corresponding to its lower-order address bits. because several memory locations can map to the same location, cached data is typically placed in the set whose cache block corresponding to that address was used least recently. see set-associative . set-associative. aspect of cache organization in which the cache space is divided into sections, called sets . the cache controller associates a particular main memory address with the contents of a particular set, or region, within the cache. RM0004 glossary 1172/1176 signaling nan. a type of nan that generates an invalid operation program interrupt when it is specified as arithmetic operands. see quiet nan . significand. the component of a binary floating-point number that consists of an explicit or implicit leading bit to the left of its implied binary point and a fraction field to the right. simplified mnemonics. assembler mnemonics that represent a more complex form of a common operation. snooping. monitoring addresses driven by a bus master to detect the need for coherency actions. split - transaction. a transaction with independent request and response tenures. stall. an occurrence when an instruction cannot proceed to the next stage. static branch prediction. mechanism by which software (for example, compilers) can hint to the machine hardware about the direction a branch is likely to take. superscalar. a superscalar processor is one that can dispatch multiple instructions concurrently from a conventional linear instruction stream. in a super scalar implementation, multiple instructions can be in the same stage at the same time. supervisor mode. the privileged operation state of a processor. in supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. synchronization. a process to ensure that operations occur strictly in order . see context synchronization and execution synchronization . synchronous interrupt. an interrupt that is generated by the execution of a particular instruction or instruction sequence. there are two types of synchronous interrupts, precise and imprecise . system memory. the physical memory available to a processor. glossary RM0004 1173/1176 t tlb (translation lookaside buffer). a cache that hold s recently-used page table entries . throughput. the measure of the number of instructions that are processed per clock cycle. u uisa (user instruction set architecture). the level of the architecture to which user-level software should conform. the uisa defines the base user-level instruction set, user-level registers, data types, floating-point memory conventions and interrupt model as seen by user programs, and the memory and programming models. underflow. a condition that occurs during arithmetic oper ations when the result cannot be represented accurately in the destination register. for example, underflow can happen if two floating- point fractions are multiplied and the result requires a smaller exponent and/or mantissa than the single-precision format can provide. in other words, the result is too small to be represented accurately. user mode. the operating state of a processor used typically by application software. in user mode, software can access only certain control registers and can access only user memory space. no privileged operations can be performed. also referred to as problem state. v vea (virtual environment architecture). the level of the architecture that describes the memory model for an environment in which multiple devices can access memory, defines aspects of the cache model, defines cache control instructions, and defi nes the time-base facility from a user-level perspective. implementations that conform to the powerpc vea al so adhere to the uisa, but may not necessarily adhere to the oea. virtual address. an intermediate address used in the translation of an effective address to a physical address. virtual memory. the address space created us ing the memory mana gement facilities of the processor. program access to virtual memory is possible only when it coinc RM0004 glossary 1174/1176 w way. a location in the cache that holds a cache block, its tags and status bits. word. a 32-bit data element. write-back. a cache memory update policy in which processo r write cycles are directly written only to the cache. external memory is updated only indirectly, for example, when a modified cache block is cast out to make room for newer data. write-through. a cache memory update policy in which all pr ocessor write cycles are written to both the cache and memory. revision history RM0004 1175/1176 16 revision history table 317. document revision history date revision changes 29-nov-2007 1 initial release. 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